JPH0314820Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a gain control circuit that controls gain by a gain control signal supplied to a control input terminal.

[Prior art]

Various gain control circuits using differential amplifiers have been developed and put into practical use. FIG. 3 is a circuit diagram for explaining the operating principle of this type of gain control circuit. In the figure, Q1 and Q2 are transistors (NPN transistors) constituting a differential amplifier.
The emitters of these transistors Q1 and Q2 are commonly connected and then grounded through a variable current source 1, and the collectors of each are connected to the positive power supply terminal ( Voltage is +Vcc)
It is connected to the. And transistor Q1,
A gain control voltage is connected between each base of Q2 and ground.
V _B1 and V _B2 are each supplied, a current I _p corresponding to the input signal to be amplified is caused to flow through the variable current source 1, and an output signal is taken out from the collector of each of the transistors Q1 and Q2. In this case, collector currents Ic ₁ and Ic ₂ of transistors Q1 and Q2 are respectively expressed by the following equations.

Ic ₁ = α ₁・I ₀ /1 + exp〓〓〓 (V _B2 − V _B1 ) …(1) Ic ₂ = α ₂・I ₀ /1 + exp〓〓〓 (V _B1 − V _B2 ) …(2) However, K: Boltzmann constant 1.381×10 ^-23 [J/deg] q: Electron charge 1.602×10 ^-19 [Coulomb] α ₁ , α ² : Common base current amplification factor of transistors Q ₁ and Q ₂ T: Absolute temperature [deg] As can be seen from equations (1) and (2), the third
The gain control circuit shown in the figure consists of transistors Q1, Q
The gain is controlled by utilizing the fact that the shunt ratio of the current I _p due to 2 is determined by the control voltages V _B1 and V _B2 . In addition, the bias current (current I _p when there is no signal, which is a direct current superimposed on the signal component) in conventional gain control circuits is set relatively high to correspond to the maximum amount of current handled by the gain control circuit. The transistors Q1 and Q2 are configured to perform class A amplification.

[Problem that the invention attempts to solve]

By the way, it is known that the noise voltage en in the output signal is generally expressed by the following equation.

However, k ₁ , k ₂ : proportionality constant re : emitter resistance value R _L : load resistance value Δf : equivalent noise bandwidth In addition, the emitter resistance value re in equation (3) can be approximated by the following equation. It is known that re≒26/I _E [mA] [Ω] ...(4) From equations (3) and (4) above, the smaller the emitter resistance value re is, the smaller the emitter current I _E It can be seen that the noise generation is smaller.

However, as mentioned above, in conventional gain control circuits, the bias component of current I _p , which is the common emitter current of transistors Q1 and Q2, is large, resulting in poor S/N ratio and large noise, especially when there is no signal. There was a problem. In order to avoid these drawbacks, for example, there is a method of stacking several stages of differential transistor pairs (transistors Q1 and Q2) in series, thereby increasing the apparent emitter resistance value and suppressing noise. However, this created a problem in that the structure became complicated.

This invention was made in view of the above-mentioned circumstances, and aims to provide a gain control circuit that can significantly suppress noise generation when there is no signal.

[Means for solving problems]

In order to solve the above-mentioned problems, this invention connects each collector of the first differential transistor pair and each collector of the second differential transistor pair in common, and also connects the collectors of the first and second differential transistor pairs. The differential transistor pair is biased to class B so as to operate near the cutoff point, and when the input signal is positive, the first differential transistor pair is driven, and when the input signal is negative, the second differential transistor pair is driven. A feedback loop is provided for driving the pair, extracting an output signal from each of the common collectors, and feeding back the output signal to the input terminal in order to remove crossover distortion due to class B operation, The gain is controlled by the base voltage of each transistor constituting the two differential transistor pairs.

[Effect]

With the above-described configuration, the emitter resistance of the first and second differential transistor pairs increases significantly, and noise generation, especially when a small signal is generated, is significantly suppressed.

〔Example〕

Embodiments of this invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a first embodiment of this invention. In the figure, 5 is an input signal source, and one end of this input signal source 5 is connected to one end of each of resistors 8 and 9 via an input terminal 6 and a summing point 7, and the other end is grounded. The other end of the resistor 8 is connected to the output end of the constant current source 10,
It is connected to the common emitter of transistors Q3 and Q4 (PNP transistors) forming the differential transistor pair 12. Transistors Q3, Q4
The collectors of each differential transistor pair 13
The bases of transistors Q3 and Q5 are both connected to the ground. Further, voltages +Vc and -Vc, which are gain control signals, are applied to the bases of transistors Q4 and Q6, respectively.
The common collector of transistors Q4 and Q6 is I-V
It is connected to the input terminal of a converter (current-voltage converter) 15, and the common collector of transistors Q3 and Q5 is connected to I
- connected to each input terminal of the V converter 16. The emitters of the transistors Q5 and Q6 are connected in common and then connected to the other end of the resistor 9 and the input end of the constant current source 14. IV converter 15, 16
The output terminals of are connected to output terminals 17 and 18, respectively, and resistors 19 and 20 connected in series are inserted between the output terminals 17 and 18. Resistance 19,2
The connection point 0 is connected to the input end of NIC (negative impedance converter) 22, and the NIC
The output terminal of 22 is connected to the summing point 7. In this case, the NIC22 is a so-called voltage inversion type that outputs a voltage that is a negative real number multiple of the voltage applied to the input terminal.
It is NIC.

Further, the input terminal of the constant current source 10 and the output terminal of the constant current source 14 in the above-described configuration are respectively connected to the power supply +
B and -B, and both set current values are Icc, and the value of this current Icc is set to a current value slightly larger than the cut-off point of transistors Q3 to Q6, for example, 5 to 15 μA. It is set to a very small value. Also, the voltage +Vc, -
The absolute value of Vc is set in a range of about 0.6 to 0.8 V, and as a result, transistors Q3 to Q6 are in an operating region extremely close to cut-off when there is no signal. That is, transistors Q3 to Q6 are each biased to class B.

Next, the operation of this embodiment with the above-described configuration will be explained.

First, during a period in which the signal output from the signal source 5 is positive, a signal current flows through the resistor 8 into the common emitter of the transistors Q3 and Q4, and also flows through the resistor 9 into the constant current source 14. In this case, the set current Icc of the constant current source 14 is 10 to 15 μA
Therefore, the current flowing through the resistor 9 will not exceed this minute set value. Note that even if it tries to flow into the transistors Q5 and Q6, it will not flow because it will be reverse biased. Therefore, the signal current (mA
Most of the current _i1 flows through the resistor 8 to the common emitter of the transistors Q3 and Q4. That is, the voltage drop across resistor 9 is significantly smaller than the voltage drop across resistor 8, and the common emitter potential of transistors Q5 and Q6 rises to become reverse biased.
6 is in the cut-off state. Then, the current _I1 is shunted to the transistors Q3 and Q4 according to the shunt ratio determined by the value of the voltage +Vc, and all of these shunted currents are transferred to the transistors Q3 and Q4.
flows into each input terminal of the IV converter 15, 16 through the collector of the voltage. and an IV converter 15,
Each of the 16 output terminals outputs a voltage signal having a value corresponding to the inflowing current.

Next, when the current output from the signal source 5 enters a negative period, the current flows from the output terminal of the constant current source to the signal source 5 side via the resistor 8, and from the common emitter of the transistors Q5 and Q6 to the resistor. A current flows into the signal source 5 side via 9. In this case, resistor 8
Since the current flowing through the constant current source 10 does not exceed the set current Icc of the constant current source 10, most of the signal current is the current
i ₂ and flows out from the common emitter of transistors Q5 and Q6. That is, the voltage drop across resistor 8 is significantly smaller than the voltage drop across resistor 9, and the common emitter potential of transistors Q3 and Q4 drops to become reverse biased, causing transistors Q3 and Q4 to be cut off. On the other hand, since transistors Q5 and Q6 are in the operating state, I-V
From each input terminal of converters 15 and 16, voltage -Vc
Current flows out in accordance with the shunt ratio determined by , and these currents flow into the resistor 9 via the emitters of the transistors Q5 and Q6, becoming the aforementioned current i ₂ . Then, the IV converters 15 and 16 output a voltage signal having a value corresponding to the flowing current.

In this way, in the circuit described above, during the period when the output signal of the signal source 5 is positive, the transistor pair 1
3 is cut off, transistor pair 12 becomes active, and current _i1 flows. During the period when the output signal of signal source 5 is negative, transistor pair 12 is cut off, transistor pair 13 becomes active, and current I1 flows. ₂ flows. Further, in this case, since the transistor pair 12 and 13 are reverse biased when cut off, the base-emitter capacitance is reversely charged, and the next turn-on is delayed due to the influence of this reversely charged charge. That is, there is a possibility that large crossover distortion will occur at the joint between the currents i ₁ and i ₂ . The aforementioned NIC22 is provided to remove this crossover distortion,
An inverted voltage of the composite value of the output voltages of the IV converters 15 and 16 is outputted to the addition point 7 to eliminate the turn-on delay. That is, the NIC 22 forms a feedback loop that corrects crossover distortion.

In addition, in the circuit described above, when there is no signal, an extremely small current Icc flows through the transistor Q3.
Since the current flows only by being shunted to Q4, Q5, and Q6, the emitter resistance value of each transistor becomes extremely high (see equation (4)), and noise generation is significantly reduced.

FIG. 2 is a circuit diagram showing the configuration of a second embodiment of this invention, and parts corresponding to those in FIG. 1 are given the same reference numerals and their explanations will be omitted.

This second embodiment differs from the first embodiment described above in that a full-wave rectifier circuit 25, a waveform inversion circuit 26, and resistors 27, 28 are used instead of the NIC 22.
The point is that this is provided. The operation will be explained below.

Now, assuming that the signal output from the signal source 5 is in a positive period, this signal current attempts to flow into the common emitter of the transistor pair 12 and the constant current source 14 via the resistors 8 and 9. In this case, the output signal ea of the full-wave rectifier circuit 25, which is the absolute value signal of the signal current, is supplied to the common emitter of the transistor pair 12 via the resistor 27. Almost twice as much current flows into it. On the other hand, since the inverted signal of the signal ea is output from the output end of the waveform inversion circuit 26, the current flowing through the resistor 9 is absorbed by the output end of the waveform inversion circuit 26 via the resistor 28. As a result, the common emitter potential of the transistor pair 13 remains almost unchanged, and the transistor pair 13 remains very close to cutoff. Therefore, the current flowing into the common emitter of the transistor pair 12 through the resistors 8 and 27 is shunted to the transistors Q3 and Q4 according to the shunt ratio determined by the voltage +Vc, and the current flows through the collectors of the transistors Q3 and Q4. It flows into each input terminal of the IV converter 15, 16 through it.

Furthermore, when the signal output from the signal source 5 is in a negative period, the operating states of the transistor pair 12 and 13 are switched, and the other operations are the same as in the above case.

Thus, in the second embodiment, the transistor pair 12 (or 13) in the non-operating state
Instead of being reverse biased, it is forward biased at a point very close to the cutoff point, thereby avoiding reverse charging between the base and emitter due to reverse bias, preventing turn-on delay, and eliminating the occurrence of crossover distortion. ing. Furthermore, when there is no signal, only an extremely small current Icc flows through the transistor pair 12 and 13, as in the first embodiment described above, so that these transistor pairs 12 and 13 are extremely close to the cut-off point. This significantly suppresses noise generation when there is no signal.

In each of the above embodiments, the gain control signal is given by grounding the bases of transistors Q3 and Q5 and applying voltages +Vc and -Vc to the bases of transistors Q4 and Q6. However, this invention is not limited to this, and it goes without saying that various methods can be applied in which the shunt ratio of each transistor pair can be changed in a predetermined manner.

[Effect of idea]

As explained above, according to this invention, each collector of the first differential transistor pair and each collector of the second differential transistor pair are respectively commonly connected, and the first and second differential transistors Biasing the pair to class B to operate near the cutoff point, driving the first differential transistor pair when the input signal is positive and driving the second differential transistor pair when the input signal is negative. And,
A feedback loop is provided to extract an output signal from each of the common collectors and return the output signal to the input terminal in order to remove crossover distortion due to class B operation, and further includes a feedback loop that extracts the output signal from each of the common collectors and returns the output signal to the input terminal. Since the gain is controlled by the base voltage of each transistor, the value of the apparent emitter resistance re can be made extremely large with a simple configuration, which reduces noise generation when there is no signal or when a small signal is present. can be significantly suppressed.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the configuration of the first embodiment of this invention, Figure 2 is a circuit diagram showing the configuration of the second embodiment of this invention, and Figure 3 shows the configuration of a conventional gain control circuit. FIG. Q3, Q4...Transistor (PNP transistor), Q5, Q6...Transistor (NPN transistor), 12, 13...Transistor pair (first and second differential transistor pair).

Claims (1)

[Scope of utility model registration request] Each collector of the first differential transistor pair and each collector of the second differential transistor pair are connected in common, and the first and second differential transistor pairs are operated near a cutoff point. when the input signal is positive, the first differential transistor pair is driven; when the input signal is negative, the second differential transistor pair is driven; and the output signal is output from each of the common collectors. A feedback loop is provided to feed back the output signal to the input terminal in order to extract the cross-over distortion due to class B operation, and furthermore, the base voltage of each transistor constituting the first and second differential transistor pair is A gain control circuit characterized in that the gain is controlled by.