JPH03145377A - Deflection circuit - Google Patents

Abstract

PURPOSE:To surely control the phase of horizontal deflection by controlling a pause period so that a deflection current is equal in a forward and return paths thereby avoiding effectively duplicate short of a display picture and deterioration in the resolution. CONSTITUTION:Deflection current detection circuits 25, 26, 28, 30, 32 detect a deflection current IDY in the timing displaying a prescribed picture element of a forward and a return path based on a horizontal synchronizing signal H2D and pause period control circuits 14-16, 22, 23, 34, 36, 38, 40 control the pause period so that the detected deflection current IDY is equal. Thus, relevant picture elements in the forward and return paths is displayed on a same horizontal deflection position. Thus, the deterioration in the picture quality is effectively avoided and the phase in the horizontal deflection is surely controlled.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Overview of the invention C. Conventional technology D. Problems to be solved by the invention E. Means for solving the problems (Figs. 1, 4, and 5) F. Effects (Fig. 1) (Fig. 4 and Fig. 5) G Example (Fig. 1 to Fig. 10) (G1) First Example (Fig. 1 to Fig. 4) (G2) Second
Embodiments (FIGS. 5 to 10) (G3) Other embodiments H Effects of the invention A Field of industrial application The present invention relates to deflection circuits, and is particularly suitable for application to bidirectional deflection circuits. .

B Summary of the Invention The first invention reliably controls the phase of horizontal deflection by controlling the pause period in the deflection circuit so that the deflection currents are equal at the timing of displaying corresponding pixels in the forward and backward paths. can do.

The second invention is to control the error signal by separating it into low frequency components when controlling the pause period in the deflection circuit so that the deflection currents are equal at the timing of displaying corresponding pixels in the forward and backward paths. Therefore, even if the frequency of the horizontal synchronization signal deviates, the phase of horizontal deflection can be reliably controlled.

C. Prior Art Conventionally, in this type of deflection circuit, a drive signal such as a sine wave signal, in which the signal level changes symmetrically before and after a predetermined point in time, has been used instead of a sawtooth wave signal. A deflection circuit (hereinafter referred to as bidirectional deflection) that drives a horizontal deflection yoke using a horizontal deflection yoke (hereinafter referred to as an axially symmetrical drive signal) has been proposed (US Pat. No. 4,672,449).

According to this bidirectional deflection circuit, the displayed image can be scanned from the left to the right of the screen (hereinafter referred to as forward scanning) and conversely from the right to the left of the screen (hereinafter referred to as backward scanning). can be formed and the deflection frequency can be reduced to 172.

Further, since sudden changes in the deflection current such as sawtooth wave signals can be prevented, unnecessary radiation and the like can be reduced, and the burden on the deflection circuit elements can also be reduced.

Furthermore, when driving the deflection yoke with a sine wave signal, the power required for deflection can be reduced with a simple configuration by forming a resonant circuit and using the resonant current as the deflection current of the deflection yoke (patent application 1-208537).

Problems to be solved by the invention D By the way, in a bidirectional deflection circuit, AFC (auto
The matic frequency control circuit needs to control the phase of horizontal deflection with higher precision than a deflection circuit using a sawtooth signal.

That is, in a deflection circuit using a sawtooth wave signal,
Even if the phase of the horizontal deflection shifts, as long as the synchronization is not completely lost, a practically sufficient display image can be formed by simply moving the display image as a whole.

On the other hand, in a bidirectional deflection circuit, a display image is formed on the outward and return passes of horizontal deflection, so if the phase of horizontal deflection shifts, the pixels displayed on the outward pass and the pixels displayed on the return pass are reversed. move in the direction.

Therefore, in a bidirectional deflection circuit, even if the synchronization is not completely lost, if there is a large phase shift, the image will be displayed as a double copy, whereas if the phase is even slightly shifted, the resolution etc. will deteriorate and the image will end up being high. If the phase is not controlled with precision, the quality of the displayed image will deteriorate significantly.

Therefore, it is difficult to form a correct display image by simply controlling the repetition period of the resonant circuit based on the horizontal deflection output and the phase comparison result with the synchronization signal, such as in a deflection circuit that uses a sawtooth wave signal. There was a problem.

One possible method for solving this problem is to control the phase of the color signal applied to the cathode ray tube in accordance with the resonant frequency of the deflection circuit, instead of controlling the deflection circuit.

However, this method inevitably complicates the overall configuration and is not practical.

The present invention has been made in consideration of the above points, and aims to propose a bidirectional deflection circuit that has a simple configuration and can reliably control the phase of horizontal deflection.

E Means for Solving Problem E In order to solve this problem, in the first invention, after applying an axially symmetrical deflection current II,v to the horizontal deflection coil 10, a predetermined rest period Txyu is provided. Deflection current 1
In the deflection circuit 4 that repeats the application of nv, the deflection current IDY is applied at timings t7 and t6 for displaying predetermined pixels on the forward and backward paths, with reference to the horizontal synchronizing signal () (20).
Deflection current detection circuit for detecting 25.26.28.30.
32 and deflection current detection circuit 25.26.28.30.3
Based on the detection result in step 2, the pause period T
Dormant period control circuit that controls u 14.15.16.22
．． 23.34.36.38.40.

Furthermore, in the second invention, the horizontal deflection coil 10 includes:
After applying the axially symmetrical deflection current rDV, the deflection circuit 50 repeats the application of the deflection current rDy with a predetermined pause period TKyU. Timing to display
7. At t6, based on the detection results of the deflection current detection circuit 25.26.28.30.32 that detects the deflection current IDV and the deflection current detection circuit 25.26.28.30.32,
Deflection current detected on the outward and return journey■. 7 error current (S
an error detection circuit 34 that detects
Based on the low-pass filter circuit 58 that separates the low frequency component ■□ from the detection result S□, the output signal V□ of the low-pass filter circuit 58, and the detection result S□ of the error detection circuit 34, body 1. so that the detected deflection currents IDY have equal values. l: Inactive period control circuit 14.15.16.22.23.4 that controls period TK, .
0.51.52.59.61.62.

The deflection current IDY is detected at timings t6 and t when predetermined pixels are displayed on the forward and backward paths with reference to the F action horizontal synchronizing signal (Hz), and the detected deflection current IDY is set to the same value. , by controlling the idle period TKVU, it is possible to reliably control the phase with high precision.

Furthermore, the error current (S□) is obtained, the low frequency components ■ and 1 are separated, and the low frequency component V□ and the error current detection result SPH are obtained.
Based on the deflection current ll1l detected on the outward and return paths
If the pause period Txvu is controlled so that v has the same value, the horizontal synchronization signal (Hz).

) The phase can be reliably controlled with high precision even if the frequency changes.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) First Embodiment In FIG. 2, l indicates a television receiver as a whole, and a signal processing circuit 2 receives an NTSC video signal Sv.
give to

The signal processing circuit 2 separates a horizontal synchronization signal and a vertical synchronization signal from the video signal Sv, and converts the video signal Sv into a color signal.

Furthermore, the signal processing circuit 2 sequentially stores the color signals in the built-in line memory circuit based on the horizontal synchronization signal and the vertical synchronization signal, and then reads them out in a predetermined order.

As a result, as shown in FIG.
After the color signals for the horizontal scanning line continue in a horizontal scanning period that is 1/2 of the video signal Sv, the arrangement of the color signals for the 1 horizontal scanning line is reversed, and the color signals for the horizontal scanning line are repeated in a horizontal scanning period that is 1/2 of the video signal Sv. A drive signal S (FIG. 3(A)) is created that continues for a horizontal scanning period.

The signal processing circuit 2 amplifies the drive signal S0 and outputs the amplified drive signal S0 to the cathode ray tube 3 (corresponding to the bidirectional deflection, the drive signal S of the cathode ray tube 3 in which the signal arrangement is reversed on the outward and return passes) is generated.
, can be obtained.

Furthermore, the signal processing circuit 2 uses the horizontal synchronization signal as a reference.
A horizontal scanning reference signal HzI whose signal level falls in synchronization with the drive signal S++ (that is, a reference signal that is twice the frequency of the horizontal synchronization signal and synchronized with the horizontal synchronization signal)
is generated and output to the horizontal deflection circuit 4 together with the clock signal CK for generating the drive signal SD.

As a result, in the horizontal deflection circuit 4, the reference signals H0 and CK synchronized with the drive signal S0 of the cathode ray tube 3 can be obtained, and the horizontal scanning reference signal)1z.

The timing of the drive signal SD can be detected based on the clock signal CK and the clock signal CK.

The vertical deflection circuit 5 uses the vertical synchronization signal VD separated by the signal processing circuit 2 as a reference to create a vertical deflection signal Sv whose current value changes stepwise in response to bidirectional deflection, and sends it to the vertical deflection coil. Output.

As shown in FIG. 1, the horizontal deflection circuit 4 is composed of a resonant circuit in which a horizontal deflection coil 10 and a resonant capacitor 12 are connected in parallel via a capacitor 9 for cutting off DC, and the terminal voltage VDY of the horizontal deflection coil 10 is Voltage dividing capacitor 14
After being voltage-divided by 1 and 15, it is fed back to the drive circuit 18 via the comparator circuit 16, thereby forming an automatic oscillation circuit as a whole.

That is, as shown in FIG.
), a comparison output signal SCO□ (FIG. 4(A)) whose signal level rises is output to the drive circuit 1st.

The drive circuit 18 receives the comparison output signal S,. , 41, a pulse output signal SP (FIG. 4(B)) whose signal level rises in a pulse-like manner is generated, and the pulse output signal SP is sent to the resonant capacitor 12 and the horizontal deflection coil 10 via the coil 20. give.

Thereby, the drive circuit 18 supplies the power required for resonance to the resonance capacitor 12 and the horizontal deflection coil 10 during the period when the pulse output signal SP rises.

Therefore, the resonance capacitor 12 and the horizontal deflection coil 1O resonate with the power supplied from the drive circuit 18,
By supplying power from the drive circuit 18 based on the comparison output signal 5CO)+1 every cycle of resonance, resonance is continuously repeated.

As a result, the terminal voltage of the horizontal deflection coil 10 becomes ■. .

(Fig. 4 (C)), the signal level changes in a sinusoidal manner, and the deflection current Lv (Fig. 4 (D)) whose phase is shifted by 90 degrees with respect to the terminal voltage VDV is transmitted to the horizontal deflection coil 1.
0 can be supplied.

As a result, the horizontal deflection coil IO forms an outward deflection magnetic field during the period when the deflection current lov rises from the maximum negative value to the maximum positive value, while the deflection current Ly increases from the maximum positive value to the maximum negative value. During the period of falling to the value, a backward deflection magnetic field is formed, and thus a bidirectional deflection magnetic field can be formed.

Furthermore, in this embodiment, the horizontal deflection coil 10 includes:
Diode 22 and FET (field effe
ct transistor) 23 is connected, and the terminal voltage of the horizontal deflection coil 10 is set.

Predetermined period TK from time t1 when Y rises to O [■]
During VU, the corresponding terminal voltage ■. , is maintained at O(V), the resonance repetition period is switched and the resonance timing is controlled.

That is, the terminal voltage VOW of the horizontal deflection coil 10 is 0 [■
] If the FET 23 is turned on and the diode 22 is grounded at the time t when the voltage falls below the level 1, the terminal voltage of the horizontal deflection coil 10 becomes ■. 0 after 7 falls to the negative maximum value
(V), the terminal voltage vDV of the horizontal deflection coil 10 can be maintained at 0 (V), and the deflection current ID
Y may be held at approximately its maximum negative value.

Therefore, the terminal voltage of the horizontal deflection coil lO. , is the O
During the period held in [■] (hereinafter referred to as the suspension period),
In the cathode ray tube 3, since the electron beam is maintained in a state where it is deflected to the rightmost end, by controlling this period, the timing of starting scanning on the return path can be controlled.

Therefore, it is considered that the phase of the horizontal deflection can be controlled by switching the FET 23 to the OFF state in synchronization with the timing of the start of the return path of the drive signal SI.

However, in bidirectional deflection, since the display image is formed in the forward and backward paths as described above, the drive signal S is simply
In synchronization with the timing of starting the return scan of 0, FET23
If you simply turn off the image, the image may appear double or the resolution may deteriorate.

Therefore, in this embodiment, the deflection current is 1tly at the time point 1g (FIG. 3) when the central pixel is displayed on the outward path, and also at the time point when the pixel displayed at the same horizontal deflection position as the pixel is displayed on the backward path. (FIG. 3(C)) have the same value (so that the deflection current shown by the solid line becomes the deflection current shown by the broken line), and thereby the phase of the horizontal deflection is controlled.

That is, since a deflection magnetic field is formed according to the deflection current Lv, if equal current values are obtained at time points t2 and t3 on the outward and return trips, respectively, the pixels displayed at the time points t2 and t will be different from each other on the outward and return trips. displayed at the same horizontal deflection position.

Therefore, the rest period TK7. By controlling J, it is possible to prevent double images and deterioration of resolution.

Furthermore, at this time, the time t2 at which the central pixel on the outward path is displayed
And, the time point when displaying the backward pixel corresponding to the pixel is also,
By using this as a reference, the central part of the screen where image quality deterioration is most easily perceived can be used as a reference, and a display image with a correspondingly high quality can be formed.

Also, instead of the terminal voltage V7 of the horizontal deflection coil 10, a direct deflection current ■. By controlling so that , are equal, it is possible to control the phase of horizontal deflection with high precision.

That is, the resistor 25 connected in series to the ground side end of the horizontal deflection coil 10 outputs a detection voltage VIDY (FIG. 4(E)) proportional to the deflection current IDY of the horizontal deflection coil 1o to the comparison circuit 26.

The comparison circuit 26 outputs the comparison result between the detected voltage VID'/ and the reference voltage □ of the reference voltage #28.

At this time, the reference voltage V□ is set to a low voltage in the vicinity of O(V), and as a result, when the deflection current ゎゎ rises to a signal level approximately at the center of deflection on the return path through the comparator circuit 26. After the signal level rises at point t4, the signal level falls to the signal level approximately at the center of deflection on the forward path at time t, the comparison output signal 5coxt (Fig. 4 (F
)).

The reference signal generation circuit 30 generates a reference signal S□F+ (fourth horizontal scanning reference signal) whose signal level rises at time t and then falls at time t7 with reference to the horizontal scanning reference signal zu and clock signal CK. Figure (H)) is output.

Here, the time point t is set to the timing for displaying the center pixel on the return path for the drive signal SO (FIG. 4(G)), and the time point 1? is set at the timing to display the center pixel on the outward path.

Therefore, the pixels displayed based on the drive signal sIl at times 1& and t7 are originally pixels displayed at the same horizontal deflection position in the center of the screen.

The reference signal generation circuit 30 generates a reference signal S□ whose signal level is switched at a cycle of 1/2 of the reference signal S□F1. (Figure 4 (I)) is created.

The exclusive OR circuit 32 receives the reference signal 5REFI.
and a comparison output signal SCO□.As a result, on the return trip, the signal level falls at time t6, and then the signal level falls at time t4.
The signal level rises at time t on the outward path, and after falling at time t, the detection signal 5E11 (fourth time (J)) whose signal level rises at time t7 is output.

As a result, in the detection signal SEX, if the deflection current IDY is held at the same value at times t6 and t on the return and outward passes, the signal level falls during the period T1 during which the signal level falls during the return pass and during the outward pass. The period T2 is maintained at the same period.

On the other hand, at times t6 and t on the return and outbound passes, the deflection current is ■. , are held at different values, the balance between the period T of the return trip and the period Tt of the outward trip is lost.

In other words, when the phase of the deflection current IDV advances with respect to the drive signal S0 and is held at the phase, and as a result, when the deflection current IDY takes different values at time 1, and then, during the return path period T1.
becomes shorter, and the outgoing period T2 becomes longer.

On the contrary, the drive signal S. For, the deflection current■. 7 is held in the lagging phase, which causes the times t6 and t
7, when the deflection current toy takes a different value, the period T1 of the return path becomes longer and the period T2 of the outward path becomes shorter.

Therefore, if the pause period T is controlled based on the comparison result between the period T of the return trip and the period T2 of the outward trip, the time point t at which the central pixel of the return trip is displayed and the pixel of the outward trip corresponding to the pixel of the outbound trip are displayed. At time t7, the deflection current tov can be held at the same value, and the phase of horizontal deflection can be controlled with high precision.

The phase detection circuit 34 receives the reference signal S REF□ and the detection signal SEX, and outputs a phase detection signal 5PH (see FIG. 4 (K )).

The low-pass filter circuit (LPF) 36 outputs the average value voltage ■□ of the phase detection signal SPH by suppressing the high frequency component of the phase detection signal S8.

Therefore, at the average value voltage VP)l, the deflection current I also at the time of the return trip and the forward trip, and at t7. If V is held equal, the deflection current ■ is held at 0 [■]. When the phase of , is advanced and the deflection current 1t+y takes different values at times t6 and t7, the signal level rises to the positive side in accordance with the amount of the advanced phase.

On the other hand, the deflection current ■. 7 is held in the lagging phase, which causes the deflection current I at time t, and t, q. V
When they take different values, it is possible to obtain an average value voltage ■□ in which the signal level falls to the negative side according to the amount of the delayed phase.

The monomulti circuit 38 is composed of an integrated circuit, and receives the comparison output signal SCOM+ as a trigger signal, and
The average value voltage ■□ is received at the connection midpoint of the variable resistor and capacitor for setting the time constant externally connected to the integrated circuit.

As a result, the monomulti circuit 38 outputs the comparison output signal S,.

, the output signal S is triggered for a predetermined period at the falling edge of
The signal level of os, (Figure 4 (L)) is raised, and at this time, the rising period of the signal level changes according to the average voltage ■□ around the rising period determined by the variable resistor and capacitor. being done.

The drive circuit 40 outputs an output signal S. , the FET 23 is switched on during the period when the signal level of , , and .

Thus the deflection current■. 7 is held at an advanced phase and the deflection current 1111'/ takes different values at times t6 and L7, the average value voltage VP changes according to the amount of the advanced phase.
14 rises to the positive side and output signal S. 5.4, the period during which the signal level rises is controlled to be long.

As a result, the ON time of the FET 23 becomes longer, and the idle period T xyu is controlled to become longer.

Therefore, the repetition period of the resonance current flowing through the horizontal deflection coil 10 becomes longer, and the leading phase of the deflection current IDV is corrected.

On the other hand, the deflection current I. When the phase of FET 23 is held in a delayed phase and the deflection current IDY takes different values at time points t and t7, the average value voltage VPN falls to the negative side according to the amount of the delayed phase, so that the FET 23 is turned on. Controlled to shorten the time.

This results in a pause period T. U is controlled to be short, and the delayed phase of the deflection current I11 is corrected.

Further, when the deflection current IDY takes the same value at time points t6 and t, the average value voltage vP)I is held at 0 [■], and the FET 23 is turned on only for a period determined by the variable resistor and capacitor of the monomulticircuit 38. state, and the deflection current low is maintained in that phase relationship.

In this way, it is possible to control the pause period TKvu so that the deflection currents in the forward and backward paths are equal at the timing of scanning the pixels displayed in the center of the screen, thereby effectively avoiding image quality deterioration and ensuring The phase of horizontal deflection can be controlled.

Note that the capacitance of the resonant capacitor 12 and the inductance of the horizontal deflection coil 10 are set so that one period of resonance is shorter than the repetition period of deflection by the amount of the rest period determined by the variable resistor and capacitor of the monomulti circuit for three days. is set, so that when the average value voltage ■P is 0 [■],
It is set so that one cycle of the forward pass and the return pass coincides with one horizontal scanning cycle of the video signal Sv.

Thus, in this embodiment, resistor 25, comparator circuit 26
, the reference power supply 28, the reference signal generation circuit 30, and the exclusive OR circuit 32 generate a deflection current ■DV at timings ty and tb for displaying predetermined pixels on the forward and backward paths with reference to the horizontal synchronization signal (H2O). In contrast, the voltage dividing capacitors 14, 15,
The comparator circuit 16, the diode 22, the FET 23, the phase detection circuit 34, the low-pass filter circuit 36, the mono-multi circuit 38, and the drive circuit 40 calculate the deflection current 1tl detected in the forward and return paths based on the detection results of the deflection current detection circuit. A pause period control circuit is configured to control the pause period TKVU so that the pause period TKVU becomes equal.

In the above configuration, the video signal Sv is converted by the signal processing circuit 2 into a drive signal SD whose arrangement is reversed every cycle by repeating 172 horizontal scanning cycles of the video signal Sv, and is output to the cathode ray tube 3. be done.

On the other hand, in the horizontal deflection circuit 4, the deflection current of the horizontal deflection coil 10 is . 7 is the detection voltage viny of the resistor 25
The detection voltage II,v and the reference voltage V
A comparison output signal S C11H2 with RIF is output to the exclusive OR circuit 32.

Here, the comparison output signal S,. . The deflection current ■ is generated at the timing when an exclusive OR is obtained with the reference signal SOF+, thereby displaying the pixels in the center of the backward and forward paths.

The falling period T of the signal level and T
Detection signal S that changes by 2! x is obtained.

The detection signal SEX is sent to the reference signal S by the phase detection circuit 34.
A phase detection result is obtained between *vyt and the result is an average value voltage ■, which changes in accordance with the amount of phase shift when the phase of the deflection current roV shifts through the low-pass filter circuit 36. Obtainable.

The average value voltage ■ is outputted to the monomulti circuit 38, whereby the pause period Tl1YU is controlled according to the average value voltage ■□, and the phase of horizontal deflection is controlled.

According to the above configuration, the forward and backward deflection currents are detected at the timing of scanning the pixels displayed in the center of the screen,
Since the pause period is controlled so that the deflection currents are equal, corresponding pixels can be displayed at the same horizontal deflection position on the outward and return passes, thus effectively avoiding image quality deterioration and ensuring that the horizontal The phase of deflection can be controlled.

(G2) Second Embodiment 5. Corresponding parts to those in FIG. 1 are denoted by the same reference numerals.
In the figure, 50 indicates a horizontal deflection circuit as a whole, and even if the frequency of the horizontal synchronizing signal of the video signal Sv (Fig. 2) changes, the phase of horizontal deflection is controlled by following the change in frequency. This is what I did.

That is, a television receiver not only demodulates and displays a video signal from a standard television signal transmitted from a broadcasting station, but also displays a video signal output from, for example, a video tape recorder.

Among the video signals outputted from such video tape recorders and the like, there are some in which the frequency of the horizontal synchronizing signal is outputted at a frequency different from the value standardized by the NTSC system.

In this case, for example, in a horizontal deflection circuit as shown in FIG. 1, if the frequency of the horizontal synchronizing signal shifts, it is necessary to change the pause period to follow the frequency shift.

In other words, as shown in FIG. 6, when the phase of the horizontal deflection is synchronized with the video signal, in the phase detection signal S□ (FIG. 6 (A)), the backward period T2 and the forward path period T , are held for the same period, and an average value voltage VPM (FIG. 6(B)) held at voltage 0 (V) is obtained.

As a result, the output signal SosM of the monomulti circuit 38 (FIG. 6(C)) rises for a time determined by the external variable resistor and capacitor, and the terminal voltage Vow of the horizontal deflection coil 10 (FIG. 6(D)) rises. is the pause time T determined by the variable resistor and capacitor. Only U is kept at O(V).

On the other hand, as shown in FIG. 7, when displaying a video signal whose horizontal synchronization frequency has changed to a lower one, the phase of the deflection current IDY advances relatively and changes to the phase. A phase detection signal 5FN (FIG. 7(A)) is obtained in which the period Tz of the return path is short and the return period Tz is long.

Therefore, in the average voltage VPN (Fig. 7(B)),
The voltage rises from 0 (V) due to the relative phase advance and change in phase, and the rising time of the output signal SO3M (FIG. 7(C)) increases accordingly.

Accordingly, the terminal voltage of the deflection coil 10 becomes ■. , (Figure 7 (
D)) The pause time T K,u of (D)) becomes longer, and the horizontal deflection repetition period is controlled to become longer.

However, in this case, since the mono multi circuit 38 is set to be phase synchronized with the video signal when the average value voltage VFM is 0 [■], For this purpose, it is necessary to raise the average value voltage VFH from 0 [■] to compensate for the low frequency.

On the other hand, since the phase detection signal 5PII consists of the detection results of the deflection current in the forward and backward paths, when the phase synchronization is completely achieved, the average value voltage VPH held at 0 [■] is output. .

In other words, in the horizontal deflection circuit 4 having the configuration shown in FIG. 1, if the frequency of the reference horizontal synchronizing signal shifts, a phase error will inevitably occur, and if a phase error occurs, an image will be duplicated. or the resolution may deteriorate.

Therefore, in this embodiment, in addition to the mono multi-circuit 51 for horizontal deflection phase correction, a mono multi-circuit 52 for horizontal synchronization frequency correction is used to control the phase of horizontal deflection.

That is, as shown in FIG. 8, in the horizontal deflection circuit 4, there is a loop from the drive circuit 18 to the resonant capacitor 12 and the horizontal deflection coil IO, and a loop from the comparison circuit 16 to the monomulti circuit 3, the drive circuit 40, and the FET 23. The whole can be represented by a voltage controlled oscillation circuit 55, and the phase comparator circuit 26
The components from the reference signal generation circuit 30 to the phase detection circuit 34 can be represented by a phase comparison circuit 56.

Therefore, the horizontal deflection circuit 4 as a whole is a PLL (pha
se 1ocked 1oop) circuit.

In this case, the human input signal H of the phase comparator circuit 56 serves as a comparison standard.
When the frequency of 2I changes, the low-pass filter circuit 3
6 output voltage (in the horizontal deflection circuit 4, the average value voltage V
(corresponding to pH), a phase error occurs.

Therefore, as shown in FIG. 9, in this embodiment, the horizontal synchronization frequency is A correction loop,
A loop for horizontal deflection phase control is formed.

In other words, in the horizontal synchronization frequency correction loop, the horizontal synchronization frequency is changed based on the average voltage V□ (hereinafter referred to as standard average voltage) when the phase is synchronized with the video signal with the correct horizontal synchronization frequency. Detects the deviation of the average voltage VPH that changes due to ,
The average value voltage (2) is band-limited in a low frequency band and directly output) is fed back to the voltage-controlled oscillation circuit 55.

On the other hand, in the phase control loop, the average value voltage VPM remaining after correcting the deviation is fed back to the voltage controlled oscillation circuit 55.

In this way, even if the horizontal synchronization frequency changes, the phase error can be prevented from occurring and the phase of horizontal deflection can be controlled.

That is, the low-pass filter circuit 58 has a cutoff frequency selected to be approximately 10 (Hz), and thereby outputs a detection voltage V pH1 whose signal level changes in accordance with the frequency change of the horizontal synchronizing signal.

If the cutoff frequency is selected to be approximately 10 (Hz), even if the playback mode is changed, such as variable speed playback on a video tape recorder, the change in horizontal synchronization frequency that accompanies the change in playback mode will be followed. Therefore, it is possible to prevent phase errors from occurring.

On the other hand, the low-pass filter circuit 59 has a cutoff frequency selected to be several (kHz), and thereby outputs a detection voltage V pH2 whose signal level changes in accordance with the phase change of the horizontal deflection.

Amplifier circuits 61 and 62 receive detection voltages VPMI and
, 1 is amplified and output to mono multi circuits 52 and 51,
At this time, the gain of the amplifier circuit 61 is selected to be sufficiently higher than the gain of the amplifier circuit 62.

The monomulti circuit 52 receives the output signal of the comparison circuit 16 as a trigger signal, and raises the signal level of the output signal according to the output voltage of the amplifier circuit 61.

(Thus, via the monomulti circuit 52, a correction signal S.8.II in which the rising period of the signal level changes in accordance with the change in the horizontal synchronization frequency can be obtained.

On the other hand, the mono multi circuit 51 uses the correction signal SO3M
+ as a trigger signal, the mono multi circuit 38 (first
The correction signal S operates in the same manner as in the figure), and the signal level rises following the phase change of the horizontal deflection. , outputs □.

As a result, the correction signal SOS is generated via the monomulti circuit 51 in which the rising period of the signal level changes in accordance with the phase change of the horizontal deflection. can be obtained.

The drive circuit 40 receives a correction signal S. FET based on 3□
23 to the on state.

As a result, the FET 23 is switched to the on state with a delay corresponding to the change in the horizontal synchronization frequency, and the switching time T Kvu is controlled to be longer.

Thus, as shown in FIG. 10, the terminal voltage of the deflection coil 10 is -. From the time t when y (Fig. 10(A)) falls to O(V), the correction signal sos+4+ (Fig. 10(B)
)) until the time tlo when tlo falls changes in accordance with the change in the horizontal synchronization frequency, and from the time tto to the correction signal S. , 2 (Figure 1.0 (C)) falls at the time t
, changes following the phase change of the horizontal deflection.

As a result, even if the horizontal synchronization frequency changes, the periods T2 and T1 of the phase detection signal 5PII (FIG. 10 (D)) are maintained at the same period, and the low-pass filter circuit 6
The average value voltage VpHt output from 2 (Fig. 1O (
E)) can be maintained at approximately 0 [V], thus effectively avoiding the occurrence of phase errors and effectively avoiding image quality deterioration.

Furthermore, if the horizontal synchronization frequency change and the phase change are controlled separately in this way, even if the resonant frequency of the deflection coil IO and the resonant capacitor 12 changes due to temperature, for example, the phase shift of the horizontal deflection can be corrected. can do.

Thus, in this embodiment, resistor 25, comparator circuit 26
, the reference power supply 28, the reference signal generation circuit 30, and the exclusive OR circuit 32, based on the horizontal synchronization signal (Ho), perform predetermined timing Lq, L of the corresponding outward and return paths.
b constitutes a deflection current detection circuit that detects the deflection current IDY, whereas the phase detection circuit 34 detects the deflection current (2) detected on the outward and return passes based on the detection result of the deflection current detection circuit. An error detection circuit is configured to detect the error current (SPH) of .

Further, the low-pass filter circuit 58 constitutes a low-pass filter circuit that separates the low frequency component VFI11 from the detection result SPH of the error detection circuit, while the voltage dividing capacitor 14.15, the comparison circuit 16, the diode 22, and the FET2
3. The drive circuit 40, the mono-multi circuit 51.52, the low-pass filter circuit 59, and the amplifier circuit 61.62 operate on the outbound and return routes based on the output signal V PHI of the low-pass filter circuit 58 and the detection result S0 of the error detection circuit. Deflection current detected by■. , have equal values, the rest period T
A pause period control circuit is configured to control KYU.

According to the configuration shown in FIG. 5, the forward and backward deflection currents are detected at the timing of scanning the pixels displayed in the center of the screen, and the horizontal synchronization frequency change and phase change are detected so that the deflection currents are equal. Since the pause period is controlled in minutes, even if the horizontal synchronization frequency changes, corresponding pixels can be displayed at the same horizontal deflection position on the outward and return passes, thus effectively avoiding image quality deterioration. Therefore, the phase of horizontal deflection can be reliably controlled.

(G3) Other Embodiments In the above embodiment, the terminal voltage of the resistor 25 is the reference voltage V, I! , the comparison circuit 26 detects the deflection current toy of the horizontal deflection coil 10 by detecting the timing at which the voltage rises to Various deflection current detection means can be widely applied in the case of sample and hold, etc.

Furthermore, when using, for example, a sample hold circuit as the deflection current detection circuit as described above, for example, a subtraction circuit or the like can be applied as the error detection circuit for detecting the error current.

Further, in the above-described embodiment, a case has been described in which the deflection current is detected at the center of the screen, but the present invention is not limited to this, and the deflection current can be detected at various points on the outward and return passes as necessary.

Furthermore, in the above-described embodiment, a case was described in which a sine wave signal was applied as an axially symmetrical deflection current applied to a horizontal deflection coil, but the present invention is not limited to this, and the present invention can widely apply various signals such as a triangular wave signal. Can be applied.

Furthermore, in the above-described embodiment, a case has been described in which the frequency of the horizontal scanning reference signal is set to twice the horizontal synchronization frequency of the input video signal, but the present invention is not limited to this. may be displayed so that the frequency is equal to the horizontal synchronization frequency.

Further, in the above-described embodiment, a case was described in which an NTSC video signal was displayed, but the present invention is not limited to this, and the present invention is applicable to cases in which various video signals are displayed, such as a case in which a PAL video signal is displayed. It can be widely applied to

H Effects of the Invention As described above, according to the present invention, by controlling the pause period so that the deflection current is equal in the forward and return paths, double copying of the displayed image and deterioration in resolution can be effectively avoided. , it is possible to obtain a deflection circuit that can reliably control the phase of horizontal deflection.

Furthermore, at this time, by detecting the error signal from the deflection current in the forward and backward paths, and controlling the error signal by separating it into low frequency components, even if the horizontal synchronization frequency deviates, double copying of the displayed image will not occur. A deflection circuit that can effectively avoid deterioration of resolution and reliably control the phase of horizontal deflection can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a deflection circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a television receiver,
3 and 4 are signal waveform diagrams for explaining the operation, FIG. 5 is a block diagram showing the second embodiment, and FIGS. 6 and 7 are signal waveform diagrams for explaining the operation, 8 and 9 are block diagrams showing a PLL circuit equivalently representing a deflection circuit, and FIG. 10 is a signal waveform diagram for explaining its operation. 1...Television receiver, 4.50...
...Horizontal deflection circuit, 10...Horizontal deflection coil,
12... Resonance capacitor, 16.26...
... Comparison circuit, 34 ... Phase detection circuit, 36.
58.59...Low pass filter circuit, 38.
51.52...Mono multi circuit.

Claims (2)

[Claims] (1) In a deflection circuit that applies an axially symmetrical deflection current to a horizontal deflection coil and then repeats the application of the deflection current with a predetermined pause period, a deflection current detection circuit that detects the deflection current at the timing of displaying a pixel, and a deflection current detection circuit that detects the deflection current so that the deflection current detected in the outward and return passes has the same value based on the detection result of the deflection current detection circuit; A deflection circuit comprising a rest period control circuit that controls a rest period. (2) In a deflection circuit that applies an axially symmetrical deflection current to a horizontal deflection coil and then repeats the application of the deflection current with a predetermined pause period, a deflection current detection circuit that detects the deflection current at the timing of displaying a pixel; and an error detection circuit that detects an error current of the deflection current detected in the outward and return passes based on the detection result of the deflection current detection circuit. and a low-pass filter circuit that separates low-frequency components from the detection result of the error detection circuit; and the deflection detected on the outward and return passes based on the output signal of the low-pass filter circuit and the detection result of the error detection circuit. A deflection circuit comprising a rest period control means for controlling the rest period so that the currents have equal values.