JPH03145156A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03145156A JPH03145156A JP1283668A JP28366889A JPH03145156A JP H03145156 A JPH03145156 A JP H03145156A JP 1283668 A JP1283668 A JP 1283668A JP 28366889 A JP28366889 A JP 28366889A JP H03145156 A JPH03145156 A JP H03145156A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- protrusion
- element package
- printed board
- protrusions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 229910000679 solder Inorganic materials 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 2
- 230000017525 heat dissipation Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 8
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 239000000758 substrate Substances 0.000 description 4
- KDCGOANMDULRCW-UHFFFAOYSA-N 7H-purine Chemical compound N1=CNC2=NC=NC2=C1 KDCGOANMDULRCW-UHFFFAOYSA-N 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- XBCSKPOWJATIFC-UHFFFAOYSA-N cobalt iron nickel Chemical compound [Fe][Ni][Fe][Co] XBCSKPOWJATIFC-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体素子パッケージと放熱板に接触させる構造の半導
体装置に関し、
半導体素子パッケージと放熱板との密着性を良くすると
ともに、このパッケージを容易かつ安価に形成すること
を目的とし、
半導体素子パンケージを装着する領域に開口部を設けた
プリント基板と、前記プリント基板の厚さと同一又はそ
れ以上の厚さの突起を有し、該突起を前記プリント基板
の前記開口部に挿通して前記半導体素子パッケージに接
触させる放熱板とを含み構成する。[Detailed Description of the Invention] [Summary] Regarding a semiconductor device having a structure in which a semiconductor element package and a heat sink are brought into contact with each other, an object of the present invention is to improve the adhesion between the semiconductor element package and the heat sink, and to easily and inexpensively form this package. For the purpose of and a heat dissipation plate that is inserted into the semiconductor element package and brought into contact with the semiconductor element package.
（産業上の利用分野〕
本発明は、半導体装置に関し、より詳しくは、半導体素
子パッケージと放熱板に接触させる構造の半導体装置に
関する。(Industrial Application Field) The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a structure in which a semiconductor element package and a heat sink are brought into contact with each other.
放熱板を有する半導体装置には、第３図に例示するよう
なものがあり、この半導体装２５０は、放熱板５１上の
プリン）ｉ！ｓ２に半導体素子パフケージ５４や抵抗、
コンデンサ等の受動素子５３を接続し、さらに、プリン
ト基板５２全体を樹脂剤５５により清う構造となってい
る。There is an example of a semiconductor device having a heat sink as shown in FIG. A semiconductor element puff cage 54 and a resistor are connected to s2.
Passive elements 53 such as capacitors are connected, and the entire printed circuit board 52 is further cleaned with a resin agent 55.
ところで、この種の半導体装置５０においては、半導体
素子パッケージ５４から発生する熱を外部に放出させる
ために、プリント基板５２に開口部５６を設けるととも
に、半導体素子パッケージ５４の端子５４ａを、第４ｔ
！ｌに示すように上部に取付け、半導体素子パッケージ
５４の下部を開口部５６に挿通してその底面を半田によ
り放熱板５１に接着するようにしている。Incidentally, in this type of semiconductor device 50, in order to release heat generated from the semiconductor element package 54 to the outside, an opening 56 is provided in the printed circuit board 52, and the terminal 54a of the semiconductor element package 54 is connected to the fourth t.
! As shown in FIG. 1, the lower part of the semiconductor element package 54 is inserted into the opening 56 and the bottom surface is bonded to the heat sink 51 by soldering.
そして、半導体素子パッケージ５４を半田により接着す
る際には、放熱板５１の上に塗布した半田５９を加熱溶
融するとともに、半導体素子パッケージ５４を放熱板５
１に擦りつけて、半導体素子パッケージ５４と放熱Ｆｉ
５１との間に存在する気泡を外部に放出させ、Ｖ！着性
を良くして放熱効果を高めるようにしている。When bonding the semiconductor element package 54 with solder, the solder 59 applied on the heat sink 51 is heated and melted, and the semiconductor element package 54 is attached to the heat sink 51.
1, and connect the semiconductor element package 54 and heat dissipation Fi.
51 is released to the outside, and V! It is designed to improve adhesion and enhance heat dissipation.
しかし、上記した構造によれば、プリン）ＩＩ−ｉｆｆ
５２に設けた関ロ部５６内では半導体素子パッケージ５
４をわずかに移動できるだけであり、放熱板５１との間
の気泡を十分に排出することができず、放熱効率が低下
するといった問題がある。もとより、開口部５６を大き
くすることも可能であるが、半導体装置５０の小型化に
支障をきたすことになる。However, according to the above structure, purine) II-iff
In the connecting part 56 provided in the semiconductor element package 52, the semiconductor element package 5 is
4 can only be moved slightly, and air bubbles between the heat dissipation plate 51 and the heat dissipation plate 51 cannot be sufficiently discharged, resulting in a problem that heat dissipation efficiency is reduced. Of course, it is possible to make the opening 56 larger, but this would hinder miniaturization of the semiconductor device 50.
また、半導体素子パッケージ５４は、第４図に示すよう
な構造となっており、その底面から端子５４ａまでの長
さｔを大きくして、プリント異番５２の厚さよりも大き
くする必要があり、半導体素子パッケージ５４内の半導
体チップ５７からパッケージ５４の底部までの熱伝導を
良くするために、半導体素子パフケージ５４の底部にコ
バルト・鉄・ニッケル合金よりなる熱伝導用板５８を取
付けることが行われており、このような構造とする場合
には、製造に手間がかかるばかりでなく、製造コストが
高くなるといった問題がある。Further, the semiconductor element package 54 has a structure as shown in FIG. 4, and the length t from the bottom surface to the terminal 54a needs to be larger than the thickness of the printed version 52. In order to improve heat conduction from the semiconductor chip 57 in the semiconductor element package 54 to the bottom of the package 54, a heat conduction plate 58 made of a cobalt-iron-nickel alloy is attached to the bottom of the semiconductor element puff cage 54. Therefore, when using such a structure, there are problems in that it not only takes time and effort to manufacture, but also increases the manufacturing cost.
本発明はこのような問題に鑑みてなされたものであって
、半導体素子パッケージと放熱板との密着性を良くする
とともに、このパッケージを歩留り良くかつ安価に形成
することができる半導体装置を提供することを目的とす
る。The present invention has been made in view of these problems, and an object of the present invention is to provide a semiconductor device that improves the adhesion between a semiconductor element package and a heat sink, and that can form this package at a high yield and at low cost. The purpose is to
上記した！！ＩＩ題は、第１図に例示するように、半導
体素子パッケージ３を装着する領域に開口部５を設けた
プリント基牟反１と、前記プリント基牟反ｌの厚さと同
一又はそれ以上の厚さの突起７を有し、該突起７を前記
プリント基Ｆｉ１の前記開口部５に挿通して前記半導体
素子パッケージ３に接触させる放熱板６とを備えたこと
を特徴とする半導体装置により解決する。I did the above! ! Problem II is, as illustrated in FIG. 1, a printed substrate 1 having an opening 5 in a region where a semiconductor element package 3 is mounted, and a printed substrate 1 having a thickness equal to or greater than the thickness of the printed substrate 1. The present invention is solved by a semiconductor device characterized in that it has a heat dissipation plate 6 which has a protrusion 7 of a diameter of 1.5 mm and which is inserted into the opening 5 of the printed circuit board Fi1 and comes into contact with the semiconductor element package 3. .
本発明によれば、放熱Ｆｉ６の突起７を設けるとともに
、この突起７をプリント１Ｆｉｌの開口部５に挿通して
プリント基板１上の半導体素子パフケージ３に接触させ
、しかも、突起７がプリント基板ｌの面と同一の高さに
なるか、又はプリント基板１から突出するようにしてい
る。According to the present invention, the protrusion 7 of the heat dissipation Fi 6 is provided, and the protrusion 7 is inserted into the opening 5 of the print 1Fil and brought into contact with the semiconductor element puff cage 3 on the printed circuit board 1. 1 or protrudes from the printed circuit board 1.
このため、ロウ材を塗布した突起７の上面に半導体素子
パッケージ３を押し付け、半導体素子パッケージ３を面
方向に擦りつけることにより、半導体素子パッケージ３
と突起７との間に存在する気泡を確実に除去することが
でき、密着性が向上する。Therefore, by pressing the semiconductor element package 3 onto the upper surface of the protrusion 7 coated with brazing material and rubbing the semiconductor element package 3 in the surface direction, the semiconductor element package 3
Air bubbles existing between the protrusion 7 and the protrusion 7 can be reliably removed, and the adhesion is improved.
また、本発明によれば、端子を上部に形成した半導体素
子パッケージを適用する必要はなく、樹脂材に覆われた
一般的な構造のものをプリント基ＩＢ、１に取付けるこ
とができ、半導体素子パッケージを歩留り良くかつ安価
に形成することが可能になる。Further, according to the present invention, there is no need to apply a semiconductor element package with terminals formed on the upper part, and a general structure covered with a resin material can be attached to the printed board IB, 1, and the semiconductor element package It becomes possible to form packages with high yield and at low cost.
そこで、以下に本発明の実施例を図面に基づいて説明す
る。Therefore, embodiments of the present invention will be described below based on the drawings.
第１図は、本発明の一実施例を示す半導体装置の構成国
であって、図中符号ｌは、表面に破線電極２を形成した
プリント基板で、その配線電極２には、後述する半導体
素子パフケージ３のリード端子３ａや、抵抗素子４等が
半田によって取り付けられ、また、プリント基板ｌのう
ち半導体素子パッケージ３を配置する領域には、半導体
素子バッケージ３の底部を露出させるための開口部５が
形成されている。FIG. 1 shows the components of a semiconductor device showing an embodiment of the present invention, and the reference numeral l in the figure is a printed circuit board with a broken line electrode 2 formed on its surface. The lead terminals 3a of the element puff cage 3, the resistive element 4, etc. are attached by soldering, and an opening for exposing the bottom of the semiconductor element package 3 is provided in the area of the printed circuit board l where the semiconductor element package 3 is arranged. 5 is formed.
６は、アル迷ニウム、銅等よりなる放熱板で、この放熱
板６の上には半田８によりプリント基板ｌが装着され、
また、プリント基板ｌの開口部５に対向する領域には、
プリント基Ｆｉ１の厚さと同じ、又はそれ以上の厚さの
突起７が上面平坦に形成されており、突起７を開口部５
に等してプリント基Ｆｉｌを放熱板１に載置した状態で
、突起７の上に塗布した半田８を加熱溶融し、この上か
ら半導体素子パッケージ３の底面を突起７の上面に擦り
つけてその間の気泡を排出させながら位置決めし、その
後に半田８を冷却して半導体素子パッケージ３を突起７
に固定するように構成されている。Reference numeral 6 denotes a heat sink made of aluminum, copper, etc., and a printed circuit board l is mounted on top of this heat sink 6 with solder 8.
In addition, in the area facing the opening 5 of the printed circuit board l,
A protrusion 7 having a thickness equal to or greater than the thickness of the printed substrate Fi1 is formed with a flat top surface, and the protrusion 7 is connected to the opening 5.
With the printed circuit board Fil placed on the heat dissipation plate 1, the solder 8 applied on the protrusion 7 is heated and melted, and the bottom surface of the semiconductor element package 3 is rubbed on the top surface of the protrusion 7 from above. After positioning while discharging air bubbles between them, the solder 8 is cooled and the semiconductor element package 3 is attached to the protrusion 7.
It is configured to be fixed in place.
プリント基板表面に形成された、例えば、放熱板６を接
地とするマイクロストリップラインとなっている。For example, it is a microstrip line formed on the surface of the printed circuit board, with the heat sink 6 being grounded.
上記した半導体素子パッケージ３は、半導体チップ３ｂ
とリード端子３ａ中央とを樹脂材により覆ったもので、
その中の、例えば、マイクロ波ＩＣの半導体チップ３ｂ
の端子とその周囲に配置したリード３ｂとはボンディン
グによって接続されている。The semiconductor element package 3 described above includes a semiconductor chip 3b
and the center of the lead terminal 3a are covered with a resin material,
Among them, for example, a semiconductor chip 3b of a microwave IC.
The terminal and the leads 3b arranged around it are connected by bonding.
なお、図中符号９は、放熱１６に装着したプリント基板
１、半導体素子パッケージ３及びその他の素子を覆う樹
脂材、１０は、プリント基板ｌの配線電極２に接続され
て側方から突出形成されたビス通孔を示している。In addition, the reference numeral 9 in the figure is a resin material that covers the printed circuit board 1, the semiconductor element package 3, and other elements attached to the heat dissipation 16, and the reference numeral 10 is a resin material that is connected to the wiring electrode 2 of the printed circuit board 1 and is formed to protrude from the side. It shows the screw holes.
次に、上述した実施例の作用について説明する。Next, the operation of the above-described embodiment will be explained.
上記した実施例において、放熱板６のうち、プリント基
板１の載置面及び突起７上面に半田８を塗布し、この後
に、開口部５に突起７を通しながらプリント基板１を放
熱板６の上に載置するとともに、下記後部５から露出累
日突起７に半導体素子パッケージ３を載置する。In the embodiment described above, solder 8 is applied to the mounting surface of the printed circuit board 1 and the upper surface of the projections 7 of the heat sink 6, and then the printed circuit board 1 is placed on the heat sink 6 while passing the projections 7 through the openings 5. At the same time, the semiconductor element package 3 is placed on the exposed progressive protrusion 7 from the rear portion 5 described below.
そして、放熱板６を下から加熱して半田８を溶融した状
態で、半導体素子パッケージ３を突起７の上面で摺動さ
せ、それらの間に入り込んだ気泡を外部に放出させる。Then, while the heat dissipation plate 6 is heated from below and the solder 8 is melted, the semiconductor element package 3 is slid on the upper surface of the projections 7, and air bubbles that have entered between them are released to the outside.
この場合、突起７は、プリント基板ｌの上面と同じ高さ
、又は、それよりも高く形成されているために、半導体
素子パッケージ３を自由に摺動することができ、突起７
との密着性を良くし、半導体素子パッケージ３の熱を放
熱Ｆｉ６を通して放出することが可能になる。In this case, since the protrusion 7 is formed at the same height as or higher than the top surface of the printed circuit board l, the semiconductor element package 3 can freely slide.
It becomes possible to improve the adhesion between the semiconductor element package 3 and the semiconductor element package 3, and to radiate the heat of the semiconductor element package 3 through the heat radiation Fi6.
このような、半導体素子パッケージ３を取り付ける過程
において、放熱板６上の半田８が溶融、冷却してプリン
ト基板ｌの裏面と放熱板６とを接着固定することになる
。In such a process of attaching the semiconductor element package 3, the solder 8 on the heat sink 6 is melted and cooled to adhesively fix the back surface of the printed circuit board 1 and the heat sink 6.
この後に、半導体素子パッケージ３の端子、抵抗素子４
等をプリント基［１上の配線電極２に半田付けを行い、
ついで、放熱板６の両端を除いた部分を樹脂材９により
覆うことになる。After this, the terminals of the semiconductor element package 3, the resistor element 4
Solder the wiring electrode 2 on the printed board [1,
Next, the heat dissipation plate 6 except for both ends is covered with a resin material 9.
なお、上記した実施例では半田を用いて、半導体素子パ
ッケージ、放熱板、プリント基板を取付けるようにした
が、半田の代わりに銀ペーストを適用することができる
。In the above-described embodiment, the semiconductor element package, the heat sink, and the printed circuit board are attached using solder, but silver paste can be used instead of solder.
以上述べたように本発明によれば、放熱板の突起を設け
るとともに、この突起をプリント基板の開口部に挿通し
てプリント基板上の半導体素子パッケージに接触させ、
しかも、突起がプリント基板の面と同一の高さになるか
、又はプリント基板から突出するようにしている。As described above, according to the present invention, the protrusion of the heat sink is provided, and the protrusion is inserted into the opening of the printed circuit board to contact the semiconductor element package on the printed circuit board.
Moreover, the protrusions are made to be at the same height as the surface of the printed circuit board, or to protrude from the printed circuit board.
このため、ロウ材を塗布した突起の上面に半導体素子パ
フケージを押し付け、半導体素子パッケージを面方向に
擦りつけることにより、半導体素子パッケージと突起と
の間に存在する気泡を確実に除去することができ、密着
性が向上する。Therefore, by pressing the semiconductor element puff cage onto the top surface of the protrusion coated with brazing material and rubbing the semiconductor element package in the surface direction, air bubbles existing between the semiconductor element package and the protrusion can be reliably removed. , adhesion is improved.
また、本発明によれば、端子を上部に形成した半導体素
子パッケージを適用する必要はなく、樹脂材に覆われた
一般的な構造のものをプリント基板に取付けることがで
き、半導体素子パッケージを歩留り良くかつ安価に形成
することが可能になる。Furthermore, according to the present invention, there is no need to apply a semiconductor element package with terminals formed on the top, and a semiconductor element package with a general structure covered with a resin material can be attached to a printed circuit board. It becomes possible to form the structure efficiently and inexpensively.
第１図は、本発明の一実施例を示す装置の平面図及び側
断面図、
第２図は、本発明に適用する半導体素子パッケ−ジの一
例を示す断面図、
第３図は、従来′！！２置の一例を示す平面図及び側断
面図、
第４図は、従来装置に適用する半導体素子パッケージの
一例を示す断面図である。
（符号の説明）
１・・・プリント基板、
２・・・配線電極、
３・・・半導体素子パッケージ、
５・・・開口部、
６・・・放熱板、
７・・・突起、
８・・・半田。
出 願 人 富士通株式会社1 is a plan view and a side sectional view of a device showing an embodiment of the present invention, FIG. 2 is a sectional view showing an example of a semiconductor element package applied to the present invention, and FIG. 3 is a conventional ′! ! FIG. 4 is a sectional view showing an example of a semiconductor element package applied to a conventional device. (Explanation of symbols) 1... Printed circuit board, 2... Wiring electrode, 3... Semiconductor element package, 5... Opening, 6... Heat sink, 7... Protrusion, 8... ·solder. Applicant Fujitsu Limited
Claims (1)
プリント基板と、 前記プリント基板の厚さと同一又はそれ以上の厚さの突
起を有し、該突起を前記プリント基板の前記開口部に挿
通して前記半導体素子パッケージに接触させる放熱板と
を備えたことを特徴とする半導体装置。[Scope of Claims] A printed circuit board having an opening in a region where a semiconductor element package is mounted, and a protrusion having a thickness equal to or greater than the thickness of the printed circuit board, the protrusion being connected to the surface of the printed circuit board. A semiconductor device comprising: a heat sink that is inserted into the opening and brought into contact with the semiconductor element package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1283668A JPH03145156A (en) | 1989-10-30 | 1989-10-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1283668A JPH03145156A (en) | 1989-10-30 | 1989-10-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03145156A true JPH03145156A (en) | 1991-06-20 |
Family
ID=17668517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1283668A Pending JPH03145156A (en) | 1989-10-30 | 1989-10-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03145156A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893264A (en) * | 1981-11-24 | 1983-06-02 | シ−メンス・アクチエンゲゼルシヤフト | Cooler for device |
-
1989
- 1989-10-30 JP JP1283668A patent/JPH03145156A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893264A (en) * | 1981-11-24 | 1983-06-02 | シ−メンス・アクチエンゲゼルシヤフト | Cooler for device |
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