JPH03143659A - Head driver for dot printer - Google Patents

Abstract

PURPOSE:To obtain a head driver for dot printer capable of transmitting data from a bit image buffer to a printing buffer without conducting a complicated bit operation by a method wherein the printing buffer to which the printing data is transmitted from the bit image buffer is shifted by a shift amount setting part. CONSTITUTION:A CPU conducts calculation, thereafter transmitting a shift amount resulting from the calculation to a shift amount setting part 4 as a shift command signal. Based on this signal, the shift amount setting part 4 makes shift registers 1 and 2 conduct a shift action. In this manner, the shift registers 1 and 2 receiving the transmission of the printing data from a bit image buffer can be shifted by the shift amount setting part 4 in compliance with a line to be printed. Therefore, the CPU may operate a shift amount only one time before printing of each line is started. In this manner, a time required to a shift operation can be set to be remarkably short, which is preferable for a high-speed printing.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a head drive device for a dot printer that transfers data in a bit image buffer to a print buffer and performs printing using a print strobe signal. Regarding.

(Prior Art) A dot printer is equipped with a head having a predetermined number of printing dot elements in one vertical column, and when printing, it is necessary to print from the bit image buffer while the carriage reaches the printing start position. The data of one vertical dot row is transferred to the print buffer and latched, and when a print strobe signal is issued, the timing generation circuit gives the data latched in the print buffer to the drive circuit at a predetermined timing, and this drive circuit The print dot element of the head is controlled on and off to print one vertical line of dots, and while the carriage reaches the next printing start position, the same process as described above is performed again to print the next vertical line. One row of dots is printed, and this process is repeated to complete printing of one line.

Therefore, when performing the processing described above, if the number of print dot elements (dot number) of the head is a multiple of 8, data is transferred in units of 1 byte when transferring from the bit image buffer to the print buffer. Therefore, efficient transfer can be performed. However, when the number of dots is not a multiple of 8, for example when the number of dots is 10, 2 bytes of data are required to transfer the print data. If it is AD to AD and BD to BD7, the same bits will not always be the print data, so for example, the first line will be printed as AD.

10 bits from AD to BDo and BDl,
The next line is printed from AD2 to AD and BD. ~BD3
The bits to be used for printing change for each row so that there are 10 bits.

Therefore, when processing such a thing with a program, it becomes complicated to transfer this 2-byte data to a register such as an accumulator, shift it with a shift command, and then transfer it to the print buffer, which slows down the processing speed. It becomes a thing. In this way, if the processing speed is slow, the data transfer from the bit image buffer to the print buffer will not be completed before the carriage advances one dot row in the horizontal direction, making printing impossible, which is not suitable for high-speed printing. Appropriate.

Conventionally, the following two examples have been considered as means for solving such problems.

As a first conventional example, in the case of a dot printer equipped with a head with 9 dots, the bottom dots are not used for normal character printing but are used for underlining, graphics, etc., so the top 8 dots are The data corresponding to the dots up to is stored in 1 byte of the first bit image buffer, and the data corresponding to the bottom dot is stored in 1 byte of the second bit image buffer for 8 horizontal dots. . When printing is to be performed, first, one byte of data is transferred from the first bit image buffer to the print buffer, and then only one bit of one byte is transferred from the second bit image buffer. Transfer data to print buffer.

As a second conventional example, for example, if the head has 10 dots, the data structure is 1 byte + 2 bits.
The remaining 6 bits of the 1-byte data containing 2 dots are left blank (all "0" or "1") so that the 6 dots are not used as print data. According to this, it is sufficient to always transfer two bytes to the print buffer.

(Problem to be solved by the invention) Recently, it has been considered to use a 50-dot head in order to improve resolution, and in this case, it is only necessary to transfer 5 bytes of data for 40 dots. , data transfer for the remaining 10 dots becomes a problem.

The first conventional example is a case of 9 dot heads, so 1
The data structure is just byte + 1 bit, but ]O
In the case of a dot head (for example, the remaining 10 dots of a 50-dot head), the data structure is 1 byte + 2 bits, and if these 2 bits are stored in 2 bytes each for 8 horizontal dots, data processing becomes complicated, and as mentioned above, 50
This method is unsuitable for data transfer from a multi-dot head such as a dot head, and furthermore, since two bit image buffers 7 are required, bit operations become complicated.

In addition, in the second conventional example, in the case of 10 dot heads,
Since 1 byte is used for the remaining 2 bits, a large capacity bit image buffer is required.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to print even if the number of printing dot elements in the head is not a multiple of 8.
A dot printer head drive that can transfer data from the bit image buffer to the print buffer without processing the bit image buffer, increasing the capacity of the bit image buffer, or performing complex bit operations. We are in the process of providing equipment.

[Structure of the Invention] (Means for Solving the Problems) A head drive device for a dot printer according to the present invention has a predetermined number of bits, can be shifted, and is a parallel printer in which data in a bit image buffer is transferred. A print buffer of input and parallel output type is provided, and a shift amount setting unit is provided to set the shift amount of this print buffer according to the data to be printed, and by receiving a print strobe signal, parallel output data from the print buffer is provided. H is characterized by a configuration in which a drive section is provided to drive the head at a predetermined timing based on the above.

(Function) According to the dot printer head edict device of the present invention, the data transferred from the bit image buffer to the print buffer is shifted according to the data to be printed by the shift amount setting section and then driven at a predetermined timing. Since only the necessary data is given to the drive section, the head is driven based on this data. Therefore, there is no need to transfer and shift the data from the bit image buffer to a register such as an accumulator, there is no need to use two or more bit image buffers, and furthermore, the data can be stored in the bit image buffer without blank space. can do.

(Example) An example of the present invention will be described below with reference to the drawings.

First, the overall configuration will be explained with reference to FIG. 1 and 2 are 8-bit shift registers serving as print buffers, and these are of a parallel input and parallel output type. Data from a bit image buffer (both not shown) is supplied to the 8-bit input terminals of these shift registers 1 and 2 via an 8-bit data bus 3 under the control of the CPU. There is. Reference numeral 4 denotes a shift amount setting section, to whose input terminal a shift command signal is applied via the data bus 3 under the control of the CPU. The shift amount setting section 4 is configured to output a shift amount signal SF from an output terminal as described later, and is configured to apply the shift amount signal SF to the control terminals of the shift registers 1 and 2. . 5 is a gate circuit consisting of AND circuits 51 to 510, 6 is a CP
A timing generation circuit whose input terminal is supplied with a print strobe signal PS from U, and a drive circuit 7 constitute a drive section 8. That is, one input terminal of each of the AND circuits 51 to 5B is supplied with data from the 8-bit output terminal of the shift register 1, and the AND circuits 59 and 5□. The 8-bit output terminals Do to D of the shift register 2 are connected to each one of the input terminals of the shift register 2.
The data from the output terminals Do and Dl of the upper two bits of 7 is applied. Therefore, the remaining output terminals D1 to D7 of the shift register 2 are unused rest output terminals. The timing generation circuit 6 is configured to output drive timing signals T1 to T1o (see FIG. 4) from an ε, 10-bit output terminal to which the print strobe signal PS is applied, and these drive timing signals TI to TIG is AND circuit 55 to 5! o is applied to each other input terminal of the input terminal.

The drive circuit 7 has an AND circuit 51 connected to a 10-bit input terminal.
When data is given from the output terminals of the heads 9 to 510, output signals are output from the corresponding 10-bit output terminals, and these output signals are given to the 10-bit input terminal of the head 9. It has become. The head 9 is mounted on a carriage (not shown) and has ten printing dot elements 91 to 910 arranged in a vertical line, and when an output signal is given to the corresponding printing dot element from the drive circuit 7, , from the power supply terminal 10 (?! dilX voltage +V) to the printed dot element, the current limiting resistor 11 is connected.
It is designed to be energized through. The head 9 may be of a wire dot type, an inkjet type, or a thermal type, but the thermal type is used here.

Next, the operation of this embodiment will be explained with reference to FIGS. 2 to 4.

As shown in FIG. 2, a bit image buffer (not shown) stores print data of 10 bits in one vertical column. First, when printing the first line, the address r0 is read from the bit image buffer as shown in FIG.
Print data of 1 byte: 1 to 2 bytes each from 000J and "1000" is transferred to shift registers 1 and 2 via data bus 3. Note that in FIG. 3, the number of dots (number of bits) in the horizontal direction is set to 4,096. In this case, 1 byte of print data at address r0000J is transferred to shift register 1 and latched, and 1 byte of print data at address r1000J is transferred to shift register 2 and latched. Further, a shift command signal is given from the CPU to the shift amount setting section 4 via the data bus 3, and the shift amount setting section 4 outputs a shift amount signal SF indicating the shift amount "0", for example, to perform the shift. Apply to registers 1 and 2. Thereafter, the print strobe signal PS is supplied from the CPU to the timing generation circuit 6, and the timing light 1 circuit 6 receives the high-level drive timing signal T1 having a predetermined time difference from each other, as shown in FIG. ~T! . are sequentially output and applied to the andro paths 51 to 51o. Therefore, the print data latched in the shift registers 1 and 2 is transferred from the output terminals Do to D7 of the shift register 1 and the output terminals of the shift register 2, Dl to the AND circuits 5 to 58.
and 59 + 510 to be sequentially applied to the drive circuit 7. As a result, the drive circuit 7 sets the output signal of the corresponding output terminal to a low level when the content indicated by the print data indicates that printing is required (7% blank level), and sets the output signal of the corresponding output terminal to a low level when printing is not required (low level). The output signal is set to a high level, and the print dot probes 91 to 910 of the head 9 operate to form dots on the printing paper when a low level signal is applied, and dots when a high level signal is applied. The operation does not form dots.

In this way, the head 9 prints the first 10 dots in one vertical column of the first row based on the print data of bits "0" to "7" of address ro 000J and bits rOJ and rlJ of address rlooOJ. It turns out. Similarly, the bit image buffer address "
0001'' and rloolJ to addresses rOF FJ and rlFFFJ are sequentially transferred to shift registers 1 and 2,
Based on this, the head 9 starts printing in each vertical column, and the 117th printing operation ends.

When the printing operation of the first line is completed, the printing operation moves to the second line. In this case, first, the 2-byte printing arcs at addresses r1000J and r2000J of the bit image buffer are transferred to shift registers 1 and 2. be done.

Here, 1 byte of print data at address rlooOJ is transferred to shift register 1 and latched, and 1 byte of print data at address "2000J" is transferred to shift register 2 and latched, but address "1000"
The mark 'γ data of bits ``0'' and ``1'' are from the first line, and if printed as is, it will not result in proper printing. Therefore, the CPU again gives a shift command signal to the shift amount setting section 4, and the shift amount setting section 4 outputs, for example, a shift amount No. f3 SF indicating a shift amount of "2" to the shift registers 1 and 2. give. As a result, shift registers 1 and 2 are shifted by "2", and shift register 1 is shifted by bit "2" of address r1000J.
The output terminal outputs the print data of "7".

~D! The shift register 2 outputs the print data of bits "0" and "1" of the address r2000J from the output terminals D6 and D7 of the shift register 1, and also outputs the print data of the bits "2" and "1" of the address r2000J.
3" is output from its own output terminals Do and Dl. As a result, as described above, the timing generation circuit 6 generates drive timing signals T1 to T! based on the print strobe signal PS. . When you output address r100
Bits “2” to “7” of 0J and address “2000”
The mark 'γ data of bits "0" to "3" of "" will be printed in the first vertical column of the second row.

Similar operations are performed thereafter, but the CPU performs the following calculations each time the printed line changes. That is, if the shift amount is S and the line to be printed is (, then S -2x Ce -D-8x lNT[((-1)/
4] is performed. Here, lNT[<<-1)
The box contains only the integer part of (1, -1)/4. Therefore,
The shift S5 in the first row is S s = 2 X (1-1) - 8X INT[(1
-1) C] -0, and the shift amount 82 of the second row is S 2-2 X (2-1)-8X INT[(2-
1) C]-2, and for example, the shift ff in the 18th row
1sta is S18-2X (1g-1)-8X
INT[(1B-1)c]-34-8X 4-2 . The CPU performs such calculations and provides the shift amount S of the calculated resultant to the shift amount setting section 4 as a shift command signal, and the shift amount setting section 4 sends the shift amount S to the shift registers 1 and 2 based on this. Execute the shift operation. Incidentally, such calculation of the shift amount S is performed by the shift type setting section 4.
Of course, it is also possible to have the program perform the task itself.

In addition, the CPU sets buffer pointers P1 and P2 of print data to be transferred to shift registers 1 and 2 at j() as Pl - (< -1) + INT [('! -1) C]
Calculate as P2-Pl+1. For example, as shown by the arrow in FIG. 3, the buffer pointer P1 (2-11+
P2゜2. ) is P 1 +2-s) -(2-1)+INT[(2-1
) C]-1P 212-31″Pl (2-31+ 1-
Therefore, (0002) + (1000) x 1- (10(
12) (0002) + (1000) x 2- (
2002), and the CPU transfers the 2-byte print data at addresses "1002" and "2002" to shift registers 1 and 2.

According to this embodiment, the shift registers 1 and 2 to which print data is transferred from the bit image buffer are shifted by the shift amount setting unit 4 according to the line to be printed, so that the CPU It is only necessary to calculate the shift amount once before starting printing, and therefore the time required for shifting is extremely short, making it suitable for high-speed printing.

In addition, there is no need to perform any processing on the bit image buffer, there is no need to use two or more bit image buffers, and there is no need to perform complicated bit operations for data transfer, making the program simpler and easier to use than existing The advantage is that the software can be used as is. Moreover, the print data can be stored in the bit image buffer without blank space, and there is no need to use a particularly large capacity bit image buffer.

Although the above embodiment describes the case where a 10-dot head is used, even when using a head with a large number of dots such as a 50-dot head, it is possible to increase the number of 8-bit shift registers. It is possible.

Further, in the above embodiment, an 8-bit shift register is used, but if the CPU is 16-bit, a 16-bit shift register may be used.

Further, in the above embodiment, a parallel input/parallel output type shift register is used as the print buffer, but a barrel shifter may be used instead, and in this case, the shift amount can be written as data. does not require a shift clock, and therefore,
This has the advantage of simplifying the groove bottom of the shift amount setting section.

[Effects of the Invention] As explained above, in the head drive device of the dot printer of the present invention, the print buffer to which print data is transferred from the bit image buffer is shifted by the shift amount setting section, so that complicated bit operations can be avoided. It is unnecessary and suitable for high-speed printing, there is no need to use two or more bit image buffers, and print data can be stored in the bit image buffer without blank space, so there is no need to use a particularly large capacity bit image buffer. This has an excellent effect.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention; FIG. 1 is a block diagram showing the electrical configuration, FIG. 2 is a block diagram of the bit image buffer, and FIG. 3 is a diagram showing addresses of print data in the bit image buffer. , FIG. 4 is a time chart for explaining the operation. In the drawings, 1 and 2 are shift registers (print buffers), 4 is a shift amount setting section, 6 is a timing generation circuit, 7 is a drive circuit, 8 is a drive section, and 9 is a helad.

Claims (1)

[Claims] 1. A print buffer with a parallel input and parallel output method that has a predetermined number of bits and can be shifted, and the data in the bit image buffer is transferred, and the amount of shift of this print buffer is used as the data to be printed. A head drive device for a dot printer, comprising: a shift amount setting section that sets a shift amount accordingly; and a drive section that receives a print strobe signal and drives the head at a predetermined timing based on parallel output data from the print buffer. .