KR880001597B1 - Korean language image data transmission circuit by a direct memory access - Google Patents

Abstract

The method is for application to the dot printer, which is exclusive for English or Japanese, with installation of Korean character circuit board. The logic circuit comprises a latch (1) for latching image data, a latch driving circuit (2), an output port (3) for providing data to main Korean character board, a DMA controller (5) for providing Korean character image data to the printer through a main Korean character board, a latch circuit (6) for latching read address of Korean character image data, a DMA demand circuit (7) for asking DMA process, a strobe circuit (8) for providing enable signal of the printer, a clock circuit (9), and a signal control circuit (10) for clearing the DMA demand circuit (7).

Description

Hangul Image Data Transmission Circuit by DMA

1 is a block diagram showing the arrangement of the Hangul logic board according to the present invention.

2 is a circuit diagram of a Hangul image data transmitting circuit using the DMA method according to the present invention.

3 is a waveform diagram according to FIG. 2.

* Explanation of symbols for main parts of the drawings

1: Latch circuit 2: Latch driving circuit

3: output port 4: output circuit

5: DMA controller 6: latch circuit

7: DMA request circuit 8: strobe circuit

9: clock circuit 10: signal control circuit

HC: Host Computer KL: Korean Logic Board

KM: Hangeul Mainboard SP: Printer

IV1 ~ IV11: Inverter OR1 ~ OR7: Oagate

AD1 ~ AD6: AND gate DF1 ~ DF3: D type flip flop

MS: Monostable Multi-Bible Data CPU: Central Processing Unit

According to the present invention, a Korean printer is installed in a dot-trix-type printer connected to a host computer so that only English or Japanese data can be printed, and the Korean image data is output by DMA (Direct Memory Access). The present invention relates to a Hangul image data transmitting circuit using a DMA method that enables printing.

In general, an input / output device is connected to a host computer so that various data can be input and output. A printer, which is one of the dual output devices, prints the output data of the host computer on printing paper, and the like. When composing characters, it is divided into dot type and letter type, and it is divided into printer which prints one letter and prints one line at the same time.

However, if the dot matrix printer connected to the host computer is a dedicated printer capable of printing only English or Japanese data, only the image of English or Japanese is present in the printer and only the data of the dedicated language can be printed. There is a drawback that, for example, Hangul cannot be printed other than a dedicated language.

The present invention has been made in view of the above-described drawbacks, and is provided in English or Japanese by installing a Korean logical board and a Korean main board for generating and outputting Korean image data in a printer connected to a host computer to print English or Japanese. When printing data, English or Japanese data can be sent and printed under the control of Hangul Logic's central processing unit.However, when printing Hangul, the Hangul Logic's system is controlled under Hangul Logic's central processing unit. It is an object of the present invention to provide a Korean image data transmission circuit using a DMA system, which allows the Korean language to be printed by sending the generated Korean image data through a Korean main board under the control of a DMA controller.

Hereinafter, the configuration, operation, and effects of the present invention will be described in detail with reference to the accompanying drawings.

The present invention provides an oragate (OR1 to OR3), an AND gate (AD1), and an inverter (IV1) to enable the latch circuit 1 and the latch circuit 1 to which English or Japanese image data is latched. A Hangul Logic Output circuit (4) consisting of a latch driving circuit (2) and an output port (3) composed of (IV2) is connected to a DMA controller (5) and an inverter (IV6), and the DMA controller (5) ), A latch circuit 6 having an address for Hangul image data is latched, a DMA request circuit 7 composed of an inverter IV4, IV5, a D-type flip-flop DF2, and an AND gate AD2, and a mono. The strobe circuit 8, the clock circuit 9, the AND gates AD3 to AD6 and the OR gates OR5 to OR7 composed of the stable multivibrator MS, the oragate OR4 and the inverter IV7, The signal control circuits 10 constituted by the inverters IV8 to IV11 and the D flip-flop DF3 are connected to each other.

Unmarked DT is data output signal, AEN is address enable signal, WR is write signal, IO / M is input / output / memory signal, DO ~ D7 is data, CE is chip enable signal, ACK is recognition signal, ACKS is Recognition status signal, DR is DMA request signal, HRQ is hold signal, HLDA is hold recognition signal, ADS is address strobe signal, A0 ~ A15 is address signal, DAC is DMA recognition signal, STB is strobe signal, MRD is DMA lead signal Indicates.

1 is a diagram showing the arrangement of the Hangul logic board according to the present invention, in which HC is a host computer, KL is a Hangul logic board, KM is a Hangul mainboard, and SP is a printer. According to the program stored in the memory ROM, the logic board KL receives an input port 8IP for receiving data from the host computer HC and the input data is stored in the Korean image memory KSCG. The central processing unit (CPU), which reads the data and stores it in one line buffer (BF), and the Hangul image data stored in the buffer (BF) under the control of the central processing unit (CPU). ) Is configured as a DMA controller (DMAC; 5) that controls the output through the output circuit (op; 4) by the direct memory access (DMA) method. Hangul Logic (KL) of this configuration is installed between the host computer (HC) and the printer (SP), English or Japanese data input from the host computer (HC) through the input port (IP) is the central processing unit (CPU) Is stored in the buffer (BF) under the control of the control circuit, and if English or Japanese data corresponding to one line is stored in the buffer (BF), the output circuit (OP) 4 is controlled through the output circuit (OP) 4 under the control of the CPU. It is supplied to Korean main board (KL) and printer (SP) to print English or Japanese, and when Korean data is input from the host computer (HC) through the input port (IP), the central processing unit (CPU) Under the control of Korean image data (KSCG), the corresponding Hangul image data is read out and stored in the buffer (BF). In this case, if the amount corresponding to one line is stored in the buffer (BF), the buffer (BF) Control the stored data of the central processing unit (CPU) By changing from the control of the DMA controller 5 to the control of the DMA controller 5, the Hangul image data is sent to the Hangul mainboard KM so that the Hangul can be printed by the printer SP.

That is, in the present invention, the Hangul Logic (KL) is mounted on a printer dedicated to the Japanese or Japanese, and then the English or Japanese data is sent to the rear circuit unit under the control of the CPU of the Logical Logic (KL). While the Korean image data is DMA controller DMAC; The control port of 5) is to be sent to the rear end circuit.

2 is a circuit diagram of a Hangul image data sending circuit by the DMA method which executes the sending of Hangul image data according to the first embodiment of the present invention having the above-described structure, which is first transmitted from the host computer HC. When English or Japanese data is printed by relaying English or Japanese data to a dot matrix printer (SP), the English data sent from the host computer HC is input through an input port and the buffer (BF) is inputted. At this time, under the control of the central processing unit (CPU) of the Hangul logic board (KL), the low level data output signal DT is stored in the oragate OR1 of the latch drive circuit 2, and the DMA controller ( From 5), the high level address enable signal AEN for English (Japanese) data is inverted to a low state in the inverter IV1 and supplied to the oragate OR1, respectively. In addition, as the write signal WR and the input / output / memory signal IO / M of the central processing unit CPU are input to the OR gate OR2 of the latch drive circuit 2 as a low level, the output signal thereof becomes low. As the high level enable signal CE is input to the OR gate OR3, the high level output signal is input to the AND gate AD1, and the low level OR gate OR1. Since the output signal of is inputted to the AND gate AK1, the output signal is supplied to the inverter IV2 as a low state, and accordingly, the high state, which is an output signal of the inverter IV2, is supplied to the latch circuit 3. English (Japanese) data is stored in the buffer (BF) by the central processing unit (CPU) of the board (KL). When this storing data is about one line, the English (Japanese) data (D0 to D79 is a latch circuit. Buffered to the output circuit (4) through the (3) and output to the Hangeul main board (KM) of the next stage.

In other words, the English (Japanese) data (DO-D7) in the output circuit (4) of the Hangul logic board (KL) through the Hangul main board (KM) under the control of the central processing unit (CPU) printer (SP) English (Japanese) data can be printed because it is supplied to.

On the other hand, in the case of printing Hangul by the printer SP through the Hangul mainboard (KM), the Hangul data from the host computer (HC) is applied through the input port of the Hangul LogicBoard (KL) to perform central processing. The device reads the Hangul image data from the Hangul Image Memory (KSCG) and stores the Hangul image data in the buffer (BF). When the Hangul image data of one line is stored in the buffer, the control operation of the CPU is stopped. The control operation of the DMA controller 5 is changed.

The operation performed under the control of the DMA controller 5 will be described with reference to the third embodiment. The clock signal CK of the central processing unit CPU is the same as that of (3-1). Since the output signal is applied to the flip-flop DF1, the output signal becomes a signal as shown in (3-4) of FIG. 3 through the inverter IV3 so that the access time for sufficiently reading data is supplied to the DMA controller 5 [controller]. Is operated by a clock signal as shown in (3-4).

Here, when the hold signal HRQ in the central processing unit CPU is in a high state as shown in (3-2) of FIG. 3, the data through the data bus of the central processing unit CPU are as shown in (3-3). Since the impedance becomes infinite, the central processing unit (CPU) stores the Hangul image data in the buffer (BF). When one line of Hangul image data is stored, the operation of the central processing unit (CPU) becomes DMA controller (5). When the recognition signal ACK, such as (3-5), is checked by the DMA controller 5 and goes from low state to high state, it is transferred through the inverters IV4 and IV5 of the DMA request circuit 7. Since the D-type flip-flop DF2 is input to the clock terminal (where the VDD power is connected to the D terminal), its output signal is supplied to the AND gate AD2 in a high state while the recognition state signal ACKS is centrally processed. As it is supplied to the device CPU and also the other input of the AND gate AD2 is The output signal is changed to the DMA request signal DR such as (3-6) and supplied to the DMA controller 5, so that the hold signal HRQ such as (3-7) is supplied to the CPU. Therefore, the Korean image data is sent out as a DMA method. Accordingly, the central processing unit (CPU) of the Hangul Logic Logic (KL) sends the hold recognition signal (HLDA) to the DMA controller 5, so that the DMA controller 5 becomes the master mode, Since the Korean image data of 16384 bytes is relayed between the memory and the peripheral circuit without relaying the CPU, the Korean image data stored in the buffer BF is transmitted to the Korean main board (KM). Given.

That is, when the Hangul image data stored in the buffer BF is supplied to the Hangul mainboard KM, the address enable signal AEN of the high state such as (3-8) is generated by the DMA controller 5 so that the inverter (IV6) is supplied to the latch circuit 6 and [the address strobe signal ADS in the controller 5 to the latch circuit 6, respectively, so that the address signal in the high state like the latched (3-11) A8 to A15 are the same as (3-9) and are supplied to the Korean image memory (KSCG), so that the corresponding Korean image data is read out, stored in the buffer BF, and then sent out from the buffer as data D0 to D7. The data is latched in the latch circuit 1 as data (3-10).

Subsequently, the data such as (3-10) is a low-state DMA recognition signal (DAC) such as (3-12) in the DMA controller (5), the monostable multivibrator (MS) of the strobe circuit (8) The monostable multivibrator MS is supplied with the high state signal to the OR gate OR4 by the time constant, and then the output signal of the OR gate OR4 is inverted in the inverter IV7. The strobe signal STB in the low state as shown in (3-13) is supplied to the Korean main board KM such that data D0 to D7 as in (3-10) are supplied.

After all data in the output buffer has been sent out, the DMA controller 5 has a low state DMA lead signal MRD as shown in (3-14) of FIG. 3 and the AND gate AD4 in the signal control circuit 10. To the OR gate OR7, the TC signal TC is inverted in the inverter IV11 in the high state as in (3-15) and supplied to the D-type flip-flop DF3, respectively.

At this time, the output signal of the D-type flip-flop DF3 is supplied to the AND gate AD6, the OR gate OR7, and the inverter IV ₁₂ as the high state, and the signal of the low state through the inverter IV12 is first supplied. Since the DMA request signal DR, such as (3-6), is lowered to the DMA controller 5 through the AND gate AD2, data of one line is transmitted through the printer (KM). It is supplied to SP and indicates the end, and since the strobe signal STB in the low state is applied to the AND gate AD6 in the high state through the inverter IV9, its output signal is applied to the oragate OR6 (also The high state signal through the inverter IV9 is inverted in the inverter IV7 through the oragate OR4 and is sent to the Hangul mainboard KM as the strobe signal STB in the low state. Then, as the above-described output signal of the inverter IV8 in the high state is applied to the OR gate OR6, the output signal is inverted in the inverter IV10 as the high state, and the inverter IV ₁₀ output signal in the inverted low state is inverted. Is applied to the cree end CLR of the D flip-flop DF2 in the DMA request circuit 7 as a low state through the AND gate AD5.

In addition, the memory lead signal MED of the DMA controller 5 is applied to the AND gate AD4 and the OR gate OR7. First, the output signal of the OR gate OR7 is the output signal of the D flip-flop DF3. And the output signal is applied to the clear terminal CLR of the D-type flip-flop DF2 in the low state because the output signal is applied to the AND gate AD ₅ in the low state by the memory lead signal MED. It can be seen that the end of the transmission is supplied to the printer (SP) through the Hangeul mainboard (KM).

On the other hand, since the recognition criterion signal d in the signal control circuit 10 is supplied to the OR gate OR5, the signals are supplied in the order of the aforementioned OR gate OR5, inverter IV8 and OR gate OR6, As the memory memory signal MEWR and the input / output memory signal IORW of the DMA controller 5 are applied to the AND gate AD3, the above-described data output signal DT and the OR gate OR5 are supplied to the DMA controller. As the memory lead signal MED and lead signal RD of (5) are inputted to the AND gate AD4, the output signal is supplied to the memory as the memory lead signal a.

As described above, when the TC signal TC in the DMA controller 5 goes from the high state to the low state as shown in (3-15) of FIG. 3, the Hangul logic board KL is again connected to the CPU of the CPU. Is changed to

Therefore, the reason why the DMA controller 5 is used for the transmission of the data D0 to D7 is that only four cycles of time are required to output one byte of data to the Korean mainboard KM. Therefore, as an example, as the clock signal of 1.525MGZ is input from the Korean logic board KL, 384KBYTES / SEC can be output to the Korean main board KM.

As described above, the present invention enables the printing of English (Japanese) or Korean data by installing a Korean logical board and a Korean main board between a host computer and a printer. Through the logic processor's central processing unit, the data is revered as a main board.In contrast, in order to print Korean characters, the Hangul logic data's DMA is collected by collecting the Hangul image data into the output buffer. Since the controller performs the work instead of the central processing unit and operates the printer through the Hangeul mainboard, the printer has the advantage of printing Korean data even as a printer capable of printing English or Japanese data.

Claims (1)

The latch circuit 1 includes an oragate OR1 to OR3, an AND gate AD1, and an inverter IV1 and IV2 to which the English (Japanese) image data or the Korean image data is latched. A latch driving circuit 2 for enabling and an output port 3 for transmitting data to the Hangeul main board are connected to the latch circuit 1, the latch driving circuit 2, and the output port 3, respectively. The DMA controller 5 and the inverter IV6 are connected to the output circuit 4 of the Hangul logic board configured to control the printer image transmission through the Hangul main board in the DMA method. The DMA controller is connected to the DMA controller. (5) includes a latch circuit (6) having a Hangul image data reading address latched, a DMA request circuit (7) requesting DMA processing, and a strobe circuit (8) for supplying a signal to operate the printer through the Hangul mainboard. , The image corresponding to the clock circuit (9) and one line Emitter is then sent to the DMA manner the DMA request circuit 7, the Cree signal control circuit 10 is connected to each Hangul image data sent by the DMA circuit is configured to.

Images