JPH03142368A - Ic measuring probe - Google Patents
Ic measuring probeInfo
- Publication number
- JPH03142368A JPH03142368A JP1282401A JP28240189A JPH03142368A JP H03142368 A JPH03142368 A JP H03142368A JP 1282401 A JP1282401 A JP 1282401A JP 28240189 A JP28240189 A JP 28240189A JP H03142368 A JPH03142368 A JP H03142368A
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- arrangement
- pad
- insulating substrate
- signal extraction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000523 sample Substances 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims abstract description 3
- 238000000605 extraction Methods 0.000 claims description 14
- 238000005259 measurement Methods 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 15
- 239000010931 gold Substances 0.000 abstract description 15
- 229910052737 gold Inorganic materials 0.000 abstract description 15
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明はＩＣ計測用のプローブに関し、特に狭ピツチ多
ピンＬＳＩの計測に適したプローブに関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a probe for IC measurement, and particularly to a probe suitable for measurement of a narrow pitch, multi-pin LSI.
〈従来の技術〉
ＩＣ内部との電気的接続を取るには、従来、基板の中央
部に設けられた開口部を中心として、対象となるＩＣの
各信号取り出し電極にそれぞれ対応した多数のプローブ
ピンを放射状に配列した、いわゆるプローブカードが用
いられている。<Conventional technology> In order to make electrical connections with the inside of an IC, conventionally, a large number of probe pins, each corresponding to each signal extraction electrode of the target IC, are installed around an opening provided in the center of the board. A so-called probe card is used in which probes are arranged in a radial pattern.
〈発明が解決しようとする課題〉
ところで、従来のプローブカードにおいては、プローブ
ピンを１本ずつ機械的に基板上に装着することによって
作成する必要があるため、その位置精度は自ずと限界が
ある。そのため、近年のＬＳＩのように信号取り出しパ
ッドが狭ピッチのものや複雑なパッド配列を持つものに
対しては、カードの作成が非常に困難となってきている
。<Problems to be Solved by the Invention> Incidentally, in the conventional probe card, since the probe pins must be manufactured by mechanically mounting them one by one on the board, there is a natural limit to the positional accuracy. For this reason, it has become extremely difficult to create cards for LSIs in recent years that have narrow pitch pads for signal extraction or have complicated pad arrangements.
本発明はこのような点に鑑みてなされたもので、作成が
容易で極めて簡単なｎｔ造′のもとに、狭ピッチの信号
取り出しパッドを持つものや複雑なパッド配列の素子に
対しても充分に対応でき、しかも、従来のプローブカー
ドに比してより高周波の信号の計測が可能なＩＣ計測用
プローブの提供を目的としている。The present invention has been made in view of these points, and is based on an extremely simple NT structure that is easy to manufacture, and can be applied to devices with narrow pitch signal extraction pads and devices with complicated pad arrangements. The object of the present invention is to provide an IC measurement probe that can sufficiently handle signals at higher frequencies than conventional probe cards.
く課題を解決するための手段〉
上記の目的を遠戚するための構成を、実施例に対応する
第１図を参照しつつ説明すると、本発明では、絶縁性基
板１の表面に、被計測ＩＣ４の信号取り出し電極５・・
・・５の配設パターンと同じパターンで複数の導電体の
突起２・・・・２を形成するとともに、その各突起２・
・・・２に個別に導通する信号取り出し線３・・・・３
を形成している。Means for Solving the Problems> A configuration that is distantly related to the above object will be described with reference to FIG. 1 corresponding to the embodiment. IC4 signal extraction electrode 5...
A plurality of conductor protrusions 2...2 are formed in the same pattern as the arrangement pattern in 5, and each of the protrusions 2...
・・・Signal take-out line 3 that conducts individually to 2...3
is formed.
〈作用〉
！！！縁性縁板基板１上電性突起２・・・・２に被計測
ＩＣ４の信号取り出し電極５・・・・５を押圧密着させ
ることにより、信号取り出し線３・・・・３を介して被
計測ＩＣ４内部との電気的導通を取れる。<Effect>! ! ! By press-fitting the signal extraction electrodes 5 . . . 5 of the IC 4 to be measured to the conductive protrusions 2 . Electrical continuity with the inside of the measurement IC 4 can be established.
ここで、突起２・・・・２および信号取り出し線３、・
・・３は、例えばフォトリソグラフィ等によって形成可
能であるため、容易に高い位置精度が得られる。Here, the protrusion 2...2 and the signal extraction line 3,...
. . 3 can be formed, for example, by photolithography, etc., so that high positional accuracy can be easily obtained.
〈実施例〉
第１図は本発明実施例の外観図で、被測定ＬＳＩチンプ
４を併記して示す図である。<Embodiment> FIG. 1 is an external view of an embodiment of the present invention, and also shows an LSI chimp 4 to be measured.
例えばガラス等の透明なｔＩＡＩ性基板性基−１に複数
の金バンプ２・・・・２と、各金バンプ２と導通する信
号取り出し線３・・・・３が形成されている。For example, a plurality of gold bumps 2 . . . 2 and signal extraction lines 3 .
金バンプ２・・・・２は、測定しようとするＬＳＩチッ
プ４の電極パッド５・・・・５の配設パターンと同一の
パターンとなっている。The gold bumps 2...2 have the same pattern as the arrangement pattern of the electrode pads 5...5 of the LSI chip 4 to be measured.
各信号取り出し線３・・・・３の金バンプ２・・・・２
との接続端と反対側の端部には、それぞれパッド部３ａ
・・・・３ａが形成されている。Gold bumps 2...2 on each signal extraction line 3...3
A pad portion 3a is provided at the end opposite to the end connected to the pad portion 3a.
...3a is formed.
次に、以上の本発明実施例の製法の例を述べる。Next, an example of the manufacturing method of the above embodiment of the present invention will be described.
まず、最終的な大きさよりも所定面積だけ大きな絶縁性
基板１を用意し、その表面に一様に金属薄膜を蒸着等に
よって形成する。次に、その上面に一様にレジスト膜を
塗布し、信号取り出し線３・・・・３およびパッド部３
ａ・・・・３ａ、更には金バンプ２・・・・２との接合
部を含むパターンのマスクを用いてそのレジスト膜を露
光および現像し、エツチングによって金属薄膜をパター
ニングする。First, an insulating substrate 1 larger by a predetermined area than the final size is prepared, and a metal thin film is uniformly formed on its surface by vapor deposition or the like. Next, a resist film is uniformly applied to the upper surface of the signal extraction line 3...3 and the pad portion 3.
The resist film is exposed and developed using a mask with a pattern including the joints with a...3a and the gold bumps 2...2, and the metal thin film is patterned by etching.
このとき、第２図に示すように、次工程の金バンプのメ
ツキ用の電極部となるパターン３ｂを基板１の周囲に形
成しておく。At this time, as shown in FIG. 2, a pattern 3b is formed around the substrate 1 to serve as an electrode portion for plating gold bumps in the next step.
次に、基板１の表面にメツキ用のレジストを一様に塗布
し、金バンプ２・・・・２のパターンを持つマスクを用
いてそのレジストを露光し、金バンプ２・・・・２を形
成すべき箇所のみのレジストを除去する。その状態で、
パターン３ｂを電極部として金メツキを施し、金バンブ
２・・・・２を形成する。Next, a resist for plating is uniformly applied to the surface of the substrate 1, and the resist is exposed using a mask having a pattern of gold bumps 2...2. Remove the resist only in the areas to be formed. In that state,
Gold plating is applied using the pattern 3b as an electrode part to form gold bumps 2...2.
その後、基板１の周囲をダイシングによって除去するこ
とによってパターン３ｂを取り除けば、第１図に示した
構造のプローブが得られる。Thereafter, by removing the pattern 3b by dicing the periphery of the substrate 1, a probe having the structure shown in FIG. 1 is obtained.
第３図は以上の本発明実施例の使用方法の例の説明図で
ある。FIG. 3 is an explanatory diagram of an example of how to use the above embodiment of the present invention.
この例においては、ＬＳＩチップ４を計測するために必
要なコンデンサや周辺ＩＣからなる計測用回路を支持板
１０に実装して、この支持板１０上にＬＳＩチップ４を
電極パッド５・・・・５を上に向けた状態で装着する。In this example, a measurement circuit consisting of a capacitor and peripheral IC necessary for measuring the LSI chip 4 is mounted on a support plate 10, and the LSI chip 4 is mounted on the electrode pads 5, . . . Attach it with 5 facing upward.
また、支持板１０には、その装着状態のＬＳＩチップ４
を囲むように、本発明実施例のパッド部３ａ・・・・３
ａに対応させてバンプを形成しておく。Further, the LSI chip 4 in its attached state is mounted on the support plate 10.
The pad portion 3a of the embodiment of the present invention surrounds the
Bumps are formed corresponding to a.
そして、支持板１０上にＬＳＩチップ４を装着し、その
上方から本発明実施例Ｐをその金バンプ２・・・・２の
形成面を下にして各金バンプ２・・・・２がＬＳＩチッ
プ４の各電極パッド５・・・・５に密着するように押圧
する。このとき、第一４図に示すように、各パッド部３
ａ・・・・３ａが支持板１０に形成されたバンプ１０ａ
・・・・１０ａに同時に押圧密着されるようにすれば、
ＬＳＩチップ４と支持板１０上の計測用回路とが相互に
接続されることになる。 このような使用法によると、
計測すべきＬＳＩチップ４と計測用回路とを接続する配
線引き出し距離が短くて済み、従来のプローブカードを
使用する場合に比してより高周波の計測が可能となる。Then, the LSI chip 4 is mounted on the support plate 10, and the embodiment P of the present invention is placed from above with the formed surface of the gold bumps 2...2 facing down, so that each gold bump 2...2 is an LSI chip. It is pressed so that it comes into close contact with each electrode pad 5...5 of the chip 4. At this time, as shown in FIG.
a...3a is the bump 10a formed on the support plate 10
...If it is pressed tightly to 10a at the same time,
The LSI chip 4 and the measurement circuit on the support plate 10 are connected to each other. According to this usage,
The wiring length for connecting the LSI chip 4 to be measured and the measurement circuit can be shortened, and higher frequency measurement is possible compared to the case where a conventional probe card is used.
なお、金バンプ２・・・・２および支持板１０のバンプ
１０ａ・・・・１０ａの高さのばらつきは、絶縁性基板
１の弾性、ないしは押圧密着時の金バンプ２・・・・２
やバンプ１０ａ・・・・１０ａの変形によって吸収され
、問題とはならない。Incidentally, the variation in height of the gold bumps 2...2 and the bumps 10a...10a of the support plate 10 is due to the elasticity of the insulating substrate 1 or the gold bumps 2...2 when pressed into close contact.
This is absorbed by the deformation of the bumps 10a, . . . 10a, and does not pose a problem.
〈発明の効果〉
以上説明したように、本発明によれば、絶縁性基板の一
面に、被計測ＩＣチップの電極パッドと同等の配列パタ
ーンを持つ複数の導電体バンブと、その各バンプに個別
に導通する信号取り出し線を形成した構造であるので、
例えばフォトリソグラフィ技術を用いることによって製
造することができ、容易に位置精度を高精度化すること
ができると同時に、多ピンのＬＳＩ等を初めとする、例
えば第５図に示すような複雑なパッドＥ、、、、Ｈの配
列にも簡単に対応でき、しかも、ピン数が多くても製造
コストが殆ど変わらずに低コストのプローブが得られる
。<Effects of the Invention> As explained above, according to the present invention, a plurality of conductive bumps having an arrangement pattern equivalent to the electrode pads of an IC chip to be measured are provided on one surface of an insulating substrate, and each of the bumps is individually arranged. The structure has a signal extraction line that conducts to the
For example, it can be manufactured using photolithography technology, and the positional accuracy can be easily improved. E, ..., H arrangements can be easily accommodated, and even with a large number of pins, a low-cost probe can be obtained with almost no change in manufacturing cost.
また、計測用回路を適当な基板に実装して、本発明のプ
ローブと組み合わせて使用することにより、信号取り出
し線を短くすることもでき、従来のプローブカードに比
してより高周波の計測が可能となる。Furthermore, by mounting the measurement circuit on a suitable board and using it in combination with the probe of the present invention, the signal extraction line can be shortened, making it possible to measure higher frequencies than with conventional probe cards. becomes.
第１図は本発明実施例の外観図で、被計測ＬＳＩを併記
して示す図、第２図はその製造工程の説明図、第３図は
本発明実施例の使用方法の例の説明図、第４図はその要
部拡大図、第５図は本発明が対応可能なＩＣの電極パッ
ドの配列パターンの例を示す図である。
１・・・・絶縁性基板
２・・２・・・・金バンプ
３・・３・・・・信号取り出し線
３ａ・・３ａ・・・・パッド部
４・・・・被計測ＬＳＩチップ
５・・５・・・・電極パッド
１０・・・・支持板
１０ａ・・・・パッドFig. 1 is an external view of an embodiment of the present invention, together with an LSI to be measured, Fig. 2 is an explanatory diagram of its manufacturing process, and Fig. 3 is an explanatory diagram of an example of how to use the embodiment of the present invention. , FIG. 4 is an enlarged view of the main part thereof, and FIG. 5 is a diagram showing an example of an arrangement pattern of electrode pads of an IC to which the present invention can be applied. 1... Insulating substrate 2... 2... Gold bump 3... 3... Signal extraction line 3a... 3a... Pad portion 4... LSI chip to be measured 5.・5... Electrode pad 10... Support plate 10a... Pad
Claims (1)
配設パターンと同じパターンで複数の導電体の突起が形
成され、かつ、その各突起に個別に導通する信号取り出
し線が形成されてなるＩＣ計測用プローブ。A plurality of conductor protrusions are formed on the surface of an insulating substrate in the same pattern as the arrangement pattern of the signal extraction electrodes of the IC to be measured, and a signal extraction line that is individually conductive to each of the protrusions is formed. IC measurement probe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1282401A JPH03142368A (en) | 1989-10-30 | 1989-10-30 | Ic measuring probe |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1282401A JPH03142368A (en) | 1989-10-30 | 1989-10-30 | Ic measuring probe |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03142368A true JPH03142368A (en) | 1991-06-18 |
Family
ID=17651932
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1282401A Pending JPH03142368A (en) | 1989-10-30 | 1989-10-30 | Ic measuring probe |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03142368A (en) |
-
1989
- 1989-10-30 JP JP1282401A patent/JPH03142368A/en active Pending
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