JPH0314218A - Charged beam lithography - Google Patents

Abstract

PURPOSE:To make the acceleration of the data conversion time as well as the reduction of transfer data feasible while bringing together well compressed lithographic pattern data by a method wherein the positional data on common regions and local regions contained in frame regions as well as the figure data contained in the local regions are collected to bring together into the frame data. CONSTITUTION:In the title drawing method, an LSI chip region 1 is divided into three assumptive frame regions 51-53; a multitude of block regions defined by block data exist in the LSI chip region 1; and the block regions 3, 4, 7, 8 existing in the frame regions 51-53 are assumed to be common regions while the block regions 5, 6, 9 outside the common regions are assumed to be local regions. On the other hand, the positional data on the common regions and the local regions contained in the frame regions 51-53 as well as the frame data contained in the local regions are collected to bring together the frame data as the lithographic pattern data pertaining to one frame region so that the lithographic pattern data on the whole LSI chips may be composed of the set of frame data and the common data as the figure data on the common regions.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention provides a charged beam for drawing the bumps of a semiconductor integrated circuit such as an LSI on a sample such as a mask or a wafer at high speed and with high precision. The present invention relates to a lithography method, and particularly to a charged beam lithography method that enables highly accurate lithography using compressed lithography pattern data.

(Prior Art) In recent years, LSI patterns have become increasingly finer and more complex, and electron beam lithography devices have been used to form such patterns. When drawing a desired LSI pattern using this device, LS such as CAD
Design pattern data created using an I-pattern design pattern data creation tool cannot be supplied as drawing pattern data to the above-mentioned drawing apparatus in its original format.

Firstly, the data system defined in the old pattern data is generally created as a pig system with a very high degree of freedom, so in order to make the data system acceptable to the electron beam lithography system, the following should be done. The restrictions shown must be met.

- Defined by a graphic system consisting only of basic figures (such as trapezoids and rectangles) that can be accepted by electron beam lithography equipment.

■It must be defined in a data system that does not overlap each other, which would result in multiple exposures and reduce pattern formation accuracy.

- Defined in a data system divided into predetermined unit drawing areas according to the drawing method of the electron beam drawing device.

Therefore, multiple exposure areas are removed using a method such as contouring processing from the above design pattern data, and then rectangles, trapezoids, triangles, etc. are formed for each unit drawing area (frame area, subfield area) determined by the beam deflection area. By dividing the figure into basic figure groups, a figure data system acceptable to the electron beam lithography system is created. Then, the desired LS is created based on the data of such a graphical system.
Drawing pattern data related to the I-chip is generated, and the drawing pattern data is stored in a storage medium such as a magnetic disk for drawing.

Then, in the drawing processing process, the above drawing pattern data]
Each drawing stripe area (area in which frame areas are collected according to a predetermined rule) is read out for each unit area that can be drawn by continuous movement of the table, and is temporarily stored in the pattern memory section. The data stored in this pattern memory is decoded and a desired pattern is constructed from a collection of drawing unit figures (rectangles with limits on figure size and triangles with limits on shape and size) that can be formed by beam shaping means. The figure is divided as much as possible. Based on the resulting graphical data, the beam position and beam are controlled, and the table on which the sample is placed is moved continuously in the X or Y direction to draw the desired pattern within the drawing stripe area. do.

Next, the table is moved in steps by the width of the drawing stripe area in a direction perpendicular to the continuous movement direction, and the above process is repeated to perform the drawing process on the entire desired area. In addition, in a two-stage deflection method in which the main deflection means controls the sub-deflection position and the sub-deflection means draws a desired pattern in the sub-deflection area, the frame area is composed of a collection of unit drawing areas (sub-fields). A collection of these frame areas constitutes a drawing stripe area, and the width of the drawing stripe area is defined by the beam deflection widths of the main deflection means and the sub-deflection means.

As mentioned above, when generating the drawing pattern data to be used in the drawing process, as a countermeasure for the miniaturization and high integration of LSI patterns, for pattern areas with repeating structures such as memory cells, repeat seeds are removed. Compression of the drawing pattern data was attempted by configuring the drawing pattern data with a group of graphic patterns and their repetition information. The reason for this is that in data conversion processing for memory devices, where pattern density is becoming finer and integration density is increasing rapidly, computer resources will be severely strained unless data compression is performed using the above-mentioned repeating structure, and data conversion This is because data conversion is no longer possible from the viewpoint of prolonging the processing time and making it impractical.

Against this background, in actual data conversion processing,
In the data conversion process for a non-repetitive pattern area, the area is divided into areas in a matrix based on a predetermined subfield size, and each subfield area has its drawing position and the drawing included in the subfield area. Generate drawing pattern data that defines a group of graphic patterns. And for pattern areas with repeats,
It is determined whether or not the area that becomes the repetition seed is larger than the above-mentioned subfield size, and if it is smaller or equal to the size, drawing in which repetition information is added to the figure data indicating the drawn figure pattern included in the above-mentioned repetition seed pattern area. Use it as pattern data. On the other hand, if the area is larger than the subfield area, the repeated seed slam area is divided into areas with a predetermined subfield size, and a system drawing pattern is generated in which repetition information is added to each subfield area.

Then, by combining the drawing pattern data generated through the above processing steps, the data is rearranged so that the drawing pattern data for each subfield appears in accordance with the drawing order when drawing each subfield area,
Drawing pattern data (frame data) related to a frame area, which is one unit constituting the area of the LSI chip.
Build. Furthermore, chip data is expressed as a collection of frame data, and when drawing, the drawing process is repeated for each drawing stripe area, which is a unit area that collects frame areas that can be drawn by one continuous movement of the table. The entire desired area was drawn.

However, this type of method has the following problems. That is, in the process of data conversion from design pattern data created in CAD to drawing pattern data, it was defined as design pattern data by sorting processing (data sorting process according to the drawing order) in subfield area units. Part of the repeating structure of the pattern (especially the repeating definition in the direction of continuous movement of the table) is obstructed, and as a result, the subfield areas of the pattern area with the repeating structure are expanded and each subfield area is This has led to a situation where it is necessary to define index data that indicates the drawing position and drawing pattern.

Furthermore, since the block area defined by the design pattern data cannot necessarily be included in the frame area, which is a unit area within the LSI chip, the block area that straddles the frame area may be included as necessary. teeth,
The drawing pattern data for each different frame area is divided into subfield areas constituting the area, and is composed of the drawing position and its drawing figure data. As a result, the regularity of the pattern defined in the design pattern data is destroyed, leading to problems such as an increase in the amount of data and a prolongation of data conversion time, which places a significant burden on computer resources. . In addition, in the actual writing processing process, the time required to transfer the drawing pattern data obtained by data conversion from a storage medium such as a magnetic disk to the pattern memory section for each drawing stripe area becomes long. It can be estimated that time is the main factor that reduces the drawing throughput of the drawing device itself.

On the other hand, in a writing method that does not use a continuous table movement method, but repeats writing processing for each unit area where the beam can be deflected while moving a table on which a sample such as a mask or wafer is placed in a step-and-V repeat method, Data of frequently appearing pattern areas such as memory cells is registered in advance in a storage medium, and the conversion operator inputs information on the drawing position of the pattern area at the time of data conversion. The drawing pattern data is generated by setting only the drawing position and the index pointer to the drawing pattern group without generating the drawing figure data of the area.

Then, during the drawing process, necessary drawing pattern data is read out from the storage medium for each unit area (area to be drawn when the table is stopped 1°) and used for drawing.

However, even in this type of processing, pattern areas that do not generate drawing figure data (data compression) can only be applied to system-specific pattern areas that have been registered in advance. In addition, the operator at the time of pig conversion must define placement information for data compression using the pattern area, resulting in extremely low work efficiency. In addition, in order to prevent incorrect data from being created due to human error, it is essential to thoroughly verify the generated drawing pattern data. In addition, the drawing figure data included in the system-specific pattern area mentioned above is always stored in the pattern memory section in order to speed up the transfer time to the pattern memory section, and the limited resources of the pattern memory section are used for drawing. Depending on the LSI chip used, this may be wasted.

Under these circumstances, current data conversion processing and drawing processing steps have limitations on the compression of drawing pattern data, and have contradictory problems from speeding up data compression and drawing processing. The above-mentioned problems will reduce the operation rate of electron beam lithography equipment and cause a decline in LSI productivity.In the future, with the rapid progress of LSI, pattern miniaturization and integration will increase, resulting in electron beam lithography This poses a major problem in increasing the reliability of LSI patterns drawn by the device and the operating rate of the device.

(Problem to be Solved by the Invention) As described above, in a two-stage deflection type electron beam writing apparatus that controls the beam position using a combination of main deflection means and sub-deflection means 4, conventionally a pattern having a repeating structure is used. Divide a pattern area that does not have an area or repeating structure into subfield areas according to the size of each area, and define drawing pattern data for each subfield in an order that follows the drawing order (continuous movement direction of the table). As a result, the repeating structure of the pattern that the design pattern data created with CAD has is not fully utilized, which limits the compression of the amount of data and the speeding up of data conversion time.

In addition to the above issues, in order to create writing pattern data in a system in which the design pattern data is divided into frame areas, which are unit areas specific to electron beam lithography equipment, we have changed the repeating structure of the pattern defined as the design pattern data. This results in an increase in the amount of data and a prolongation of the conversion time as described above, as well as an increase in the amount of data transferred during drawing processing, resulting in a decrease in drawing throughput.

Furthermore, even when drawing pattern data related to a pattern area that is repeatedly subjected to drawing processing is made to reside in the pattern memory section as a measure to reduce the amount of data transferred during drawing processing, the data is stored only in unique patterns set in advance. The effect is limited, it cannot be set flexibly depending on the type of chip, and the definition method is not a system that automatically identifies it from design pattern data, but the operator who converts the data uses the above registered repeating pattern. There were many practical problems in that area information had to be input.

Note that the above-mentioned problem is not limited to the electron beam drawing method, but also applies to charged beam drawing methods using an ion beam or a laser beam.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to fully utilize the repeating structure of patterns 6 defined in design pattern data created with CAD to improve the effectiveness of data compression. An object of the present invention is to provide a charged beam lithography method that can generate lithographic pattern data, speed up data conversion time, reduce the amount of transferred data during lithography processing, and improve lithography throughput. .

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to provide drawing pattern data that can be compressed by effectively utilizing the repeating structure of patterns defined in design pattern data created by CAD. The objective is to convert data at high speed and improve the drawing throughput based on this drawing pattern data.

That is, the present invention controls the shape and position of a beam from LSI chip design pattern data expressed as a set of block data consisting of figure pattern data to be drawn or reference information of other blocks to create a mask, wafer, etc. [Drawing pattern data for drawing a desired pattern]
In a charged beam drawing method in which data is converted into 7 and drawn based on the data, the area of the LSI chip is divided into virtual areas (hereinafter referred to as frame areas) determined by the beam deflection width, and defined by the block data. A block area in which a plurality of block areas exist in the area of the LSI chip and this block area exists in a plurality of frame areas is defined as a common area, and block areas other than the common area are defined as local areas, and The position data of the included common area and local area and the figure data included in the local area are collected to generate drawing pattern data (hereinafter referred to as frame data) related to one frame area, and this set of frame data and the common area mentioned above are generated. The drawing pattern data for the entire LSI chip is constructed using the graphic data (hereinafter referred to as common data), and the process of drawing the frame area as a drawing stripe area is repeated based on the common pig and each frame data. This method performs drawing processing for all eight desired areas (Claim 1).
.

Further, in the present invention, when drawing the drawing stripe area, common data and frame data of the LSI chip related to the drawing stripe area are defined in a pattern memory section that temporarily stores the drawing pattern data related to the area. The common data is always stored while drawing a unit area that is a collection of LSI chips, and only the frame data of the LSI chip related to the area is re-stored for each drawing stripe area. The method performs drawing processing (claim 3), and furthermore, in the drawing processing of the drawing stripe area, drawing is performed while decoding drawing pattern data for each drawing stripe area stored in a pattern memory section. Yes, it is determined whether the reference position of the block area or the minute area is included in the virtually defined frame area, and if this reference position is included in the frame area, the block area of 9. Alternatively, the drawing process is performed selectively on minute areas (Claim 5), and the reference positions of the block areas or the minute areas are read out in descending order or in ascending order (Claim 6).
.

(Operation) According to the method of the present invention, the repeating structure of a pattern defined in the design pattern data of an LSI chip created by CAD is automatically identified from the design pattern data, and based on the information, the LSI chip is A block area to be made resident in the pattern memory section is selected for each type of chip. Furthermore,
When data is converted from the above design pattern data to writing pattern data, the repeating structure of the pattern is drawn using a compact system that is extremely effective at data compression and is not affected by the frame area, which is the unit area of the electron beam lithography system. By generating pattern data, the amount of data for the entire LSI chip can be reduced. As a result, it is possible to speed up the data transfer time from the storage medium to the pattern memory unit for data in the drawing stripe area (an area that can be drawn by one continuous movement of the table), which is a collection of the frame 0 areas. The button memory section and computer resources can be used effectively.

Furthermore, the above-mentioned drawing method can speed up the data conversion processing time for converting design pattern data into drawing pattern data and reduce the device itself. In terms of both improving the drawing throughput and speeding up the drawing time of
It is possible to improve the productivity of SI.

(Example) The details of the present invention will be explained below with reference to the illustrated embodiments.

FIG. 1 is a schematic diagram showing the configuration of an electron beam lithography system used in a method according to an embodiment of the present invention.

In the figure, reference numeral 10 denotes a sample chamber, and a table 12 on which a sample 11 such as a semiconductor wafer or a glass mask is placed is accommodated in the sample chamber 10. The table 12 is driven by a table drive circuit 13 in the X direction (left and right directions on the page) and Y direction (back and front directions on the page).

The moving position of the table 12 is measured by a position circuit 14 using a laser interferometer or the like.

An electron beam optical system 20 is arranged above the sample chamber]0. This optical system 20 includes an electron gun 2], various lenses 22 to 26. Blanking deflector 31. Beam dimension variable deflector 32 Beam scanning main deflector 33. Sub deflector 34 for beam scanning and beam shaping aperture 35°3
It consists of 6 mag. Then, the main deflector 33 positions the predetermined sub-deflection area (subfield), the sub-deflector 34 positions the figure drawing position within the sub-field, and the beam size variable deflector 32 and the shaping aperture 35 The beam shape is controlled by .36, and while the table 12 is continuously moved in one direction, a drawing stripe area that is collected within the range that can be drawn in the frame area of two LSI chips by one continuous movement of the table is subjected to drawing processing. Further, the table 2 is moved stepwise in a direction perpendicular to the direction of continuous movement, and the above process is repeated to sequentially draw each drawing stripe area.

On the other hand, the control computer 40 has a magnetic disk (storage medium) 4.
1 is connected, and the drawing pattern data of the LSI chip is stored in this disk 41. The drawing pattern data of the LSI chip read from the magnetic disk 41 is temporarily stored in a pattern memory (data buffer section) 42 for each drawing stripe area.

The pattern memory for each drawing stripe area (consisting of drawing position and basic figure data) stored in the data buffer section 42 is decoded by a pattern data decoder 43 and a drawing data decoder 44, which are data decoding sections, and then transferred to a blanking circuit 45. Former driver 46. It is sent to the main deflector driver 47 and the sub deflector driver 48.

That is, the pattern data decoder 43 inputs the drawing pattern data for each drawing stripe area, expands the compressed drawing figure data based on the repetition information of the pattern defined as the drawing stripe data, and processes the drawing pattern data for each drawing stripe area. In the area drawing process, the drawing figure data defined in the drawing pattern data is applied to the combination of the forming apertures 35 and 36 while determining and decoding for each subfield whether or not the area should be drawn and the area to be drawn next. The figure is divided into drawing unit figure groups that can be formed by. Then, blanking data is created based on this data and sent to the blanking circuit 45. Further, desired beam size data is created, and this beam shaping control button is sent to the beam shaper driver 46.

Next, a predetermined deflection signal is applied from the beam shaper driver 46 to the beam dimension variable deflector 32 of the optical system 20, thereby controlling the four dimensions of the electron beam.

Furthermore, the drawing data decoder 44 decodes and creates subfield positioning data based on the drawing stripe data, and sends this data to the main deflector driver 47. Then, a predetermined deflection signal is applied from the main deflector driver 47 to the main deflector 33 of the optical system, whereby the electron beam is deflected and scanned to a designated subfield position. Furthermore, the drawing data decoder 44 generates a control signal for sub-deflection scanning, and this signal applies a predetermined sub-deflection signal to the sub-deflector 34 via the sub-deflector driver 48, thereby controlling the drawing process for each sub-field. is to be carried out.

Next, an electron beam lithography method using the apparatus configured as described above will be explained. FIG. 2 shows the process of generating data for performing the drawing process. The LSI pattern is
A CAD system is used to design and create a pattern, and the design pattern data is converted into lithography pattern data specific to the electron beam lithography apparatus depending on the lithography method of the electron beam lithography apparatus by a host computer with a high processing capacity, such as a large computer. Based on this drawing pattern data, the positioning and beam shape of the electron beam are controlled to perform a series of drawing processes.

Here, the design pattern data created by the CAD system is such that the entire area 1 of the LSI chip is divided into several block areas (2, 3, 5) as shown in FIG. 3(a).
, 6, 9) and several graphic patterns IA to ID, and its reference block area 2 is composed of repeating block areas 4 as shown in FIG.
Furthermore, the reference block 3 is composed of block areas 7 and 8 and a graphic pattern 3A as shown in FIG. It is a system. Here, the block areas 5, 6, and 9 are not particularly shown in the drawings, or will be described below as block areas that are constituted only by graphic patterns without reference to the block areas.

As shown in FIG. 4, the design pattern data representing each block area is composed of a block reference information group and a graphic data group defining a graphic pattern. The design pattern data shown in FIG. 4 is related to block area 1 of the entire LSI chip shown in FIG. 3(a), and the graphic patterns included in each block area are polygonal patterns. The data is defined as follows, and the system allows the patterns of these figures to overlap with each other. Furthermore, there are no particular restrictions on the overlap between block areas.

In order to convert LSI pattern data in this format into writing pattern data that can be accepted by an electron beam writing system, the host computer performs preprocessing to remove pattern overlap between the block areas (for example, a special Gansho 8
No. 2-327197). Furthermore, the block references of LSI chip 1 are concentrated in block 1 that represents the entire chip area, and the design pattern data is created so that there is no block reference other than block area 1 and the data system consists only of graphic patterns. A reorganization process is performed (that is, an expansion process is performed to limit the block reference relationship to the level), and a data system is created such that the block reference relationship is as shown in FIG. Then, mutual overlap removal processing is performed on the graphic pattern group included in each block area using methods such as the slit method and the touch puffer method to eliminate multiple exposure areas of the drawn shapes. Perform graphic processing for Next, as shown in FIG. 6, the entire area 1 of the LSI chip is divided into temporary frame areas (51 to 53) determined by the main deflection width of the beam. In FIG. 6, the table continuous movement direction is in the left-right direction on the paper, and the table step movement direction is in the vertical direction on the paper.

The top block 1 or reference 8 shown in FIG. 5 is referenced twice or more in the entire LSI chip area among the referenced block areas 3 to 9, and the frame areas 51 to 53 shown in FIG. A block area (3°4.7.8) that is referenced from two or more frames is determined to be a common block. Furthermore, the graphic patterns included in the block are divided into regions and basic shapes (rectangles,
The figure is divided into trapezoids and triangles. Then, as a graphic button system as shown in FIG. 7, common block graphic data as shown in FIG. 8 is generated, which is expressed as a set of graphic data defining the position and shape of the graphic pattern.

On the other hand, for local blocks (top blocks 1 and 5.6.9) that are blocks other than the common blocks, it is determined whether or not they straddle the frame areas 51 to 53, and block 1 and As shown in FIG. 9, subblocks 91 to 93° 9 101 to 103 are divided into regions at frame boundaries. Similarly to the above-mentioned common blocks, for local blocks which are a collection of such blocks and sub-blocks, the figure pattern included in each local block and sub-block is divided into predetermined sub-fields, and furthermore, the area obtained there is divided into predetermined sub-fields. Local block graphic data is generated which is expressed as a set of graphic data obtained by dividing the graphic pattern into basic graphic groups.

Next, in the process of generating drawing pattern data for each frame area, the frame areas 51 to 5 are
positional data that defines the drawing positions of the common block area, local block area, and sub-block area included in 3 in terms of relative positions from the frame reference position; and the common block figure data that defines the drawing figures within the block area. Then, a cell arrangement data group is generated in which one unit is index data for the local block graphic pig and repetition information of the block area. Here, the storage order of the cell arrangement data to be generated is stored in the order along the FWD movement direction of the table (from left to right on the page), and corresponds to the drawing order of each block. Also, the BW of the table
In response to the D movement (leftward from the cloth on the paper), chain data is added to each of the above cell arrangement data in accordance with the block drawing order on the BWD screen, and the data generated from this processing process is The cell arrangement data has a cell arrangement system as shown in FIG. 10(a), and the cell arrangement data has a data system for the frame area 52 as shown in FIG. 10(b).

A set of cell arrangement data and local block graphic data thus obtained constitutes one frame data. Further, a set of frame data of such a system and the common block graphic data are collected to form drawing pattern data representing the entire LSI chip as shown in FIG. 11, and are stored on the magnetic disk 41.

Next, a description will be given of processing steps when performing a drawing process based on the drawing pattern data obtained through the data conversion process as described above. As shown in FIG. 12(a),
From the LSI chip groups A to E arranged on the sample, only LSI chip groups having the same position in the step movement direction of the table are extracted and used as drawing column areas 60a to 60e. When performing drawing processing for each drawing column area, 1
All common block graphic data of the LSI chip included in one drawing column area is stored in the button memory 42, and is kept resident during the drawing process of the drawing column area. Further, from the frame areas constituting the LSI chip included in the drawing column area, only frame areas having the same table step movement direction are selectively extracted.
A drawing stripe area 60c which is a unit area to be drawn by one continuous movement of the table as shown in FIG. 12(b)
Set. Then, the frame data (composed of cell arrangement data, local block graphic data, and sub-block graphic data) 2 included in the drawing stripe area is additionally stored in the pattern memory section 42.

Therefore, the pattern memory 42 stores drawing pattern data having a system as shown in FIG. a)
Sorting the block areas that make up the block areas defined in each frame area of the drawing stripe area as shown in the above drawing stripe area along the continuous movement direction of the table (in the case of FWD, the cell arrangement data is stored in the same order as before) In the case of BWD, the data is rearranged based on the chain data given to the cell arrangement data) and held. Furthermore, a subfield to be drawn is selected from the sorted block area according to the table movement direction for each subfield area (Fig. 14(a) shows the drawing order during FWD drawing in subfield units, (b) shows the drawing order during BWD drawing) by decoding the drawing data,
It is determined whether the reference position of the subfield area is included in the frame area, and only if it is included, the main deflector 33 uses the subfield arrangement data to direct the electron beam to a predetermined subfield position. A control signal is sent to perform deflection scanning. At the same time, a group of figure data to be drawn in the subfield area is input to the pattern data decoder 43, and the figure data is divided into unit drawing figure groups that can be formed by a combination of two forming apertures 35 and 36. , the beam position and beam shape in the subfield region are controlled by the beam control signal outputted from the subfield region, and a desired pattern is written in the region.

(FIG. 14(C) shows the subfield area that is actually drawn and the subfield area that is not drawn in the drawing process of the drawing stripe area.) The drawing position of the above subfield area is set in the frame as described above. As mentioned above, the reference position is indicated as a relative position from the frame reference position, and whether or not to draw in that frame is determined by table step movement of the subfield reference position (here, the lower left coordinate point of the subfield 4 field area). If the coordinate value in the direction (vertical direction on the page) is 0 or more and smaller than the frame width, it is determined that the area is a sub-yield area to be drawn. Further, in the case where the size of the block area is smaller than a predetermined subfield size and the pattern data decoder 43 has a repetitive structure, the pattern data decoder 43 decodes the number of block areas that can be positioned and drawn using the main deflection means at one time. controlled to process.

By repeating the drawing process for such a drawing stripe area, the drawing process for the drawing column area is performed,
Furthermore, when drawing the next drawing column area, the common block figure data stored in the pattern memory section is replaced, and by repeating the above series of drawing processes, it is possible to draw a desired pattern on the entire sample. Through the above-described process, it is possible to quickly create data-compressed drawing pattern data from design pattern data, and also to realize high-speed and highly accurate drawing processing using this drawing pattern data. .

Thus, according to the method of this embodiment, a data system (
By generating drawing pattern data with a data system that is effective at data compression for patterns with repeated structures, it is possible to significantly reduce the amount of data and speed up data conversion time. In the drawing process, it is possible to reduce the amount of data transferred from the magnetic disk (storage medium) to the pattern memory section, and it is possible to significantly improve the drawing speed. Therefore, it is possible to improve the throughput in a series of drawing steps, thereby maximizing the performance of the electron beam drawing apparatus.

Note that the present invention is not limited to the embodiments described above. For example, the means for storing the drawing pattern data is not limited to a magnetic disk, but other storage media such as a magnetic tape or a semiconductor memory can be used. Furthermore, the configuration of the electron beam lithography apparatus is not limited to the same as shown in FIG. 1, but can be changed as appropriate according to specifications. In addition, although the embodiments have been explained using an electron beam as an example, the application is not limited to electron beams, but can be applied to charged beams including ion beams and laser beams, and other methods such as the Schott I method using a variable shaping beam, etc. It is also applicable to vector or rask type devices using elliptical beams.

In addition, the graphic system of the drawing pattern data stored in the storage medium may be not only basic figures such as rectangles and trapezoids but also drawing unit figures and polygonal figures, and the pattern data decoder section removes overlaps between figures. This can be done by adding a graphic calculation means that performs black and white reversal.
It is also applicable to data of such a system. Furthermore, the drawing graphic data resident in the pattern memory section is the graphic data of the entire block area, and when drawing the drawing stripe area, only the cell arrangement data of 7 in the area is transferred, further increasing the drawing throughput. It is also possible to aim for In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, the present invention has a data system that is highly consistent with design pattern data created by a CAD system (a data system that is effective at data compression for patterns with repeated structures). By generating drawing pattern data, it is possible to significantly reduce the amount of data and speed up the data conversion time. It is possible to reduce the amount of data to be transferred, and it is possible to significantly improve the drawing speed.

As a result, it is possible to improve the throughput in a series of drawing steps, and also to increase the operating rate of the electron beam drawing apparatus, contributing to improvement in LSI productivity.

8

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the configuration of an electron beam lithography system used in a method according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing the process of generating writing pattern data, and FIG. Figure 4 is a schematic diagram showing the block data system, Figure 5 is a schematic diagram showing the block structure within the chip, Figure 6 is a schematic diagram showing division into frame areas, and Figure 7 is the basic diagram. FIG. 8 is a schematic diagram showing the data structure of common block graphic data; FIG. 9 is a schematic diagram showing the local block division system;
Figure 10 is a schematic diagram showing the block arrangement of the frame.
Fig. 1 is a schematic diagram showing the data structure of the entire LSI chip, Fig. 12 is a schematic diagram showing the drawing column area and drawing stripe area during drawing, Fig. 13 is a schematic diagram showing the data structure in the pattern memory, Figure 14 shows schematics 1 to 9... blocks, 1A to 1D... for explaining the drawing processing process.
3 graphic patterns, 10...sample chamber, 11...sample, 12...table, 13...table drive circuit, 14...position circuit,
20... Electron optical system, 21... Electron gun, 22-26.
・Lens, 31 to 34... Deflector, 35. 36... Beam shaping aperture, 40... Control computer, 41...
- Magnetic disk (storage medium), 42... Button memory, 43... Pattern data decoder, 44... Drawing data decoder, 45... Blanking circuit, 46.
...Beam shaper driver, 47...Main deflector driver, 48...Sub deflector driver, 51-53...Frame area, 60a-60e...Drawing column area, 61
...Drawing stripe area, 61a-61c...Drawing frame area, 91-93.101-103...Sub-block area, A-E...LSI chip.

Claims (6)

[Claims] (1) Create drawing pattern data that can be accepted by a charged beam lithography system from LSI chip design pattern data expressed as a set of block data consisting of figure pattern data to be drawn and reference information of other blocks. In the charged beam drawing method for drawing a desired pattern on a sample based on the drawing pattern data, the area of the LSI chip is divided into virtual frame areas determined by the beam deflection width, and the areas defined by the block data are divided into virtual frame areas defined by the block data. A block area in which a plurality of block areas exist in the area of the LSI chip and the block area exists in a plurality of frame areas is defined as a common area, and block areas other than the common area are defined as local areas, and the block area is defined as a local area. The position data of the included common area and local area and the figure data included in the local area are collected to generate frame data as drawing pattern data related to one frame area, and this set of frame data and the figure of the common area are generated. The drawing pattern data for the entire LSI chip is configured with the common data as data, and based on the common data and each frame data, the process of drawing a drawing stripe area in which the frame areas are collected is repeated, and a desired area is drawn. A charged beam drawing method characterized by performing overall drawing processing. (2) In the drawing process of the drawing stripe area,
A collection of drawing unit figures that can be formed by beam shaping means by controlling the main and sub-stage beam deflection means to position the beam while continuously moving the table on which the sample is placed in the X or Y direction. 2. The charged beam drawing method according to claim 1, wherein a desired pattern is drawn as a desired pattern. (3) In the drawing process of the drawing stripe area,
The common data and frame data of the LSI chips related to the drawing stripe area are defined in a pattern memory section that temporarily stores the drawing pattern data related to the area, and drawing processing is performed on the LSI chips, and the common data is applied to the set of LSI chips. 3. The charge according to claim 1 or 2, wherein the charge is always stored while drawing a unit area, and for each drawing stripe area, only the frame data of the LSI chip related to the area is re-stored and the drawing process is performed. Beam drawing method. (4) The block area is classified depending on whether or not it is larger than a minute area determined by the beam deflection width of the sub-deflection means, and if the block area is larger than the minute area, this block area is divided into the minute areas. 3. The charged beam drawing method according to claim 2, wherein the drawing pattern data is configured as a set of graphic data for each area. (5) The drawing process for the drawing stripe area is performed while decoding the drawing pattern data for each drawing stripe area stored in the pattern memory section, and the reference position of the block area or the minute area is set in the frame. Claim 1 characterized in that it is determined whether or not the reference position is included in the frame area, and selectively draws the block area or minute area when the reference position is included in the frame area. Or the charged beam drawing method according to 2. (6) The drawing process of the drawing stripe area is performed while decoding the drawing pattern data for each drawing stripe area stored in the pattern memory unit, and the drawing is performed in descending order of the reference position of the block area or the minute area. 3. The charged beam drawing method according to claim 1, wherein the charged beam drawing process is performed by reading out the drawings in descending order.