JPH0314021A - Printer - Google Patents

Abstract

PURPOSE:To prevent the processing load from distributing to one side in a printer controller to perform the stable operation by outputting a signal indicating the receivable state to a host computer after a prescribed time at the time when the printer controller enters into the receivable state. CONSTITUTION:A delay means 10 and a switching means 12 which switches the delay means 10 to the available state or the unavailable state are provided, and the signal indicating the receivable state is outputted to the host computer after a prescribed time by the delay means when the printer controller enters into the receivable state, and the switching means 12 switches the means 10 to the available state while the image expansion processing from character code information to character pattern information is performed for the purpose of printing information. If the means 12 switches the means 10 to the unavailable state, the signal indicating the receivable state is outputted immediately when the printer controller enters into the receivable state; but otherwise, the signal indicating the receivable state is outputted after the prescribed time and another required processing is performed, during this time. Thus, the load not distributed to one side is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a printer used by being connected to a host computer.

Prior Art and Problems with the Invention This type of printer has a signal indicating a reception ready state in the interface part of the print control device in order to communicate with the host computer, and conventional printers receive data as quickly as possible. In order to receive data from the host computer, the above signal is output as soon as the printer control device becomes ready to receive data.

Incidentally, in recent years, the processing power of host computers has improved, and the speed of data transmission to printers has become extremely fast.

For this reason, in conventional printers that receive data by issuing the above signal as soon as the state within the printer control device becomes ready to receive data, the CPU (central processing This increases the load on the device, making it impossible to perform other necessary processing at a sufficient speed.

In order to reduce the load on the CPU of the printer control device, it has been proposed to provide a separate CPU dedicated to data reception.

However, this increases the number of parts and increases the cost of the entire device.

An object of the present invention is to solve the above problems, and even when connected to a high-speed host computer, it does not take too much processing time to receive data, and provides sufficient processing time for other processes other than data reception. To provide a printer that realizes even load distribution for execution and is inexpensive.

Means for Solving the Problems A printer according to the present invention has a signal indicating a receivable state in an interface part of the printer control device to communicate with a host computer, and the state within the printer control device can be received. However, it is equipped with a delay means for outputting the signal indicating the receivable state to the host computer after a predetermined delay, and a switching means for switching the delay means between enabled and disabled.

Preferably, the switching means enables the delaying means while performing image development processing from character code information to character pattern information for printing.

When the operation switching means is disabled, as soon as the state within the printer control device becomes ready for reception, a signal indicating the ready state is output, and data reception is performed.

When the switching means is effectively switched, even if the state within the printer control device becomes ready to receive, a signal indicating the ready state is output after a predetermined delay, and other necessary processing can be performed during this time. I can do it.

Example Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of a printer control device (1).

The printer control device (1) is a C controller that controls the entire printer.
It is equipped with P U (2), and CPU (2) has the following:
Through the bus (3), ROM (4), RAM (5),
A mechanism interface (8), a host computer interface (7), etc. are connected.

The ROM (4) stores in advance a printer control procedure, a host computer interface (7) control procedure, and the like.

RAM (5) is used for temporary storage of various tasks.

The mechanism interface (8) is for controlling each part of the printer mechanism.

The host computer interface (7) is for communicating with the host computer (8),
The details are shown in FIG.

In FIG. 2, Sl is an internal BUSY signal indicating that the printer control device (1) is currently processing something and cannot process the next data, and s2 is the host computer (8
) External BU indicating that data cannot be received for
This is the SY signal. These (7) BUSY signals Sl, S
2 is at the H (Hlgh) level in the USY state where reception is not possible, and is canceled and becomes the L (Low) level when the state is in the READY state where the reception is possible. And external BUSY
Interpreting the signal S2 in the opposite way, the host computer (8)
The READY signal indicates a receivable state.

s3 confirms that it can receive data from the host computer (
8). External BUSY signal S
2 and the ACK signal S3 are well known, and the host computer (8) may check whether the printer is capable of receiving signals using either one of the signals, or may use both signals. (9) is a one-shot multi-by-break for generating the ACK signal S3 from the external BUSY signal S3. The signal S3 is normally at the H level, and becomes the L level for a certain period of time when the external BUSY signal S2 is released.

S4 is a switching signal with/without delay.

The switching signal S4 is switched by the software of the CPU (2) between an H level indicating that there is a delay (valid) and an L level indicating that there is no delay (invalid). For example, when processing an image from character code information to character pattern information for printing, the processing capacity inside the printer is large and a large amount of time cannot be used to receive data from the host computer (8). At certain times, the switching signal S4 is switched to H level, and at other times, it is switched to L level.
Can be switched to level. In this way, a part of the software of the CPU (2) constitutes the switching means.

(10) is a one-shot multi-by-break to release the external BtlSY signal S2 later than the internal BUSY signal S1, and the delay time is the capacitor (C
1) and the resistance (R1). The output signal (delayed signal) S5 of the multi-bye break (10) is normally L.
When the internal BUSY signal s1 is released while the switching signal S4 is at the H level, it goes to the H level for the above delay time.

(11) is an inverter circuit for delaying the transmission of the release of the internal BUSY signal S1 to the first input terminal (12a) of the OR circuit (12) by a time slightly longer than the operation delay of the multivibrator (lO). , and four inverters. That is, in the inverter circuit (11), after the internal BUSY signal S1 is released, the multivibrator (lO) operates to generate the delayed signal S5.
This is a delay circuit with a very short delay time so as not to cause the first input terminal (12a) of the OR circuit (12) to go to the L level until it changes to the H level. And multivibrator (10), inverter circuit (11) and OR
The circuit (12) constitutes a delay means (13).

The operation of each part when the switching signal 9S4 is at L level without delay will be explained with reference to the time chart of FIG.

If the switching signal S4 is at L level, the multivibrator (10) does not operate at all, and the delay signal S5, that is, OR
The second input terminal (12b) of the circuit (12) is always at L level. While the internal BUSY signal is at H level, the output signal S6 of the inverter circuit (iF), that is, the OR circuit (12
) is also at H level, and external B
The USY signal S2 is also at H level. Internal BUSY
When the signal S1 is released, the output signal S6 of the inverter circuit (11), that is, the first input terminal (12a) of the OR circuit (12) becomes L level with a slight delay, and at this time the O
Since the second input terminal (12b) of the R circuit (12) is at L level, the output signal of the OR circuit (12) becomes L level, and the external BUSY signal S2 is released. Since the time from when the internal BUSY signal Sl becomes L level until the output signal S6 of the inverter circuit (11) becomes L level is very short, when the internal nusy signal Sl is released, the external BUSY signal S2 also becomes almost be canceled at the same time. Therefore, the internal printer READY state is immediately transmitted to the host computer (8), and the internal printer READY state is immediately transmitted to the host computer (8).
) can send the next data, resulting in the fastest data transfer.

The operation of each part when the switching signal S4 is delayed (H level) will be explained with reference to the time chart of FIG.

When the switching signal S4 goes to H level, the multivibrator (10) becomes operational, but while the internal BUSY signal S1 goes to H level, the multivibrator (10)
The delayed signal S5 is at L level. Mata, internal BUSY
While the signal S1 is at the H level, the external BUSY signal S2 is also at the H level, as described above. Here, when the inside of the printer enters the READY state and the internal BUSY signal S1 is released, the multi-bye break ('10) operates immediately after that, and only for a certain delay time determined by the capacitor (CI) and resistor (R1). The delay signal S5 becomes H level.

When the internal BUSY signal Sl is released, the output signal S8 of the inverter circuit (11), that is, the first input terminal (12a) of the OR circuit (12) becomes L level with a slight delay, but at this time, as described above, Delayed signal S5 or O
Since the second input terminal (12b) of the R circuit (12) is at H level, the external BUSY signal S2 is not released immediately, but is released only when the delayed signal S5 becomes L level again. . As a result, the host computer (8
) To cancel the external BUSY signal S2 output to
This is delayed by the delay time when the delay signal S5 is at the H level after the BUSY state inside the printer is released. Since the host computer (8) checks the external BUSY signal S2 and starts transmitting the next data, the CPU (2) on the printer side can sufficiently proceed with the internal processing of the printer during that time.

In the above embodiment, a multivibrator (10) or the like is used to configure the delay means, but a similar means may be realized by software of the CPU (2).

Effects of the Invention According to the printer of the present invention, as described above, even if the state within the printer control device becomes receivable, it is possible to output the signal representing the receivable state to the host computer with a predetermined delay. During this time, necessary processing other than reception can be performed. For this reason, even when connected to a high-speed host computer, it is possible to limit the transfer speed of print data sent to the printer to prevent uneven processing load within the printer control device and ensure stable operation. can. Furthermore, since it is only necessary to add delay means and switching means to the printer control device, it is inexpensive.

[Brief explanation of the drawing]

Fig. 1 is an electrical block diagram of a printer control device showing one embodiment of the present invention, Fig. 2 is an electrical circuit diagram of its host computer interface portion, and Fig. 3 is a time diagram showing signals of various parts when there is a delay. FIG. 4 is a time chart showing the signals of each part in the case of no delay. (1)...Printer control device, (2)...CPU,
(7)...Host computer interface, (8
)...Host computer, (10)...One-shot multivibrator, (11)...Inverter circuit, (12)...OR circuit, (13)...Delay means.

Claims (2)

[Claims] (1) In order to communicate with the host computer, in a printer that has a signal indicating a receivable state in the interface part of the printer control device, even if the state in the printer control device becomes receivable, the host computer does not receive the above signal. A printer comprising a delay means for delaying and outputting a signal indicating a receivable state by a predetermined period of time, and a switching means for switching the delay means between enabled and disabled. (2) Claim (2) wherein the switching means enables the delaying means while image development processing from character code information to character pattern information is being performed for printing.
1) Printer.