JPH0314015A - Reset signal generator - Google Patents

Abstract

PURPOSE:To realize appending and saving functions by taking a reset request signal as one input of a bus arbitrating circuit, and issuing a hold request to a central processing unit CPU when a reset request is issued and the CPU occupies a bus, and permitting reset at the time of approving the request. CONSTITUTION:When a reset request signal 6 is inputted and a CPU 4 occupies the bus, a bus arbitrating circuit 8 outputs a hold request 9 to the CPU 4; and when the current bus operation is terminated, a hold approving signal 10 for the hold request 9 is returned to the bus arbitrating circuit 8 to execute reset. Thus, a device is reset without destruction of contents of a memory because the device does not act when the CPU 4 or another device 5 is in the middle of access a memory to the memory, and appending and saving functions are realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to electronic devices such as computers that perform information processing.

[Prior Art] Fig. 2 is a schematic diagram showing conventional reset signal generation, in which 1 is a reset switch, 2 is a circuit for shaping the waveform of the reset request signal obtained by the reset switch, and 3 is a circuit for shaping the waveform of the reset request signal obtained by the reset switch. A driver for driving the reset request signal obtained by the waveform shaping circuit 2, 4 a central processing unit (hereinafter referred to as CPU), 5 a peripheral circuit to be reset, 6 a reset request signal, and 7 a driver for driving a reset request signal obtained by the waveform shaping circuit 2; This is a reset signal.

Next, the operation will be explained. The reset request signal 6 obtained by closing the reset switch 1 is processed by the waveform shaping circuit 2 to remove noise such as chattering and ensure the necessary reset signal width, and then sent to the CPU 4 and peripheral circuits 5 by the driver 3. Given.

(Problems to be Solved by the Invention) In the conventional reset signal generation circuit, the CPU and its peripheral circuits are immediately reset by the reset request signal obtained by closing the reset switch 1. Since the conventional reset generation method is configured as described above, the memory contents at the time of reset are not guaranteed, and if the system goes out of control for some reason, the memory contents at the time of the failure can be restored after the system is reset. There was a problem in that it was not possible to save and investigate the cause (hereinafter referred to as an abend save).

Furthermore, as an interesting prior art for preventing the destruction of the memory contents of dynamic RAM, Japanese Patent Application Laid-Open No. 62-256298 discloses that a hold acknowledgment is given on behalf of the microprocessor in response to a hold request signal of a refresh circuit at the time of reset of the microprocessor. Although a technique for providing a system reset synchronization circuit that outputs a signal has been disclosed, the control wiring tends to be complicated.

The present invention has been made to realize one function of a means for solving the above-mentioned problems, and is to provide a reset signal that has a simple configuration and that operates reliably, making it possible to realize the abend save function. The purpose is to obtain a generator.

[Means to solve the problem]

A reset signal generation device according to the present invention includes a bus arbitration circuit that receives a reset request signal and generates a reset signal;
a central processing unit that generates a hold approval signal based on a hold request signal for reset from the bus arbitration circuit, and the bus arbitration circuit receives the reset request signal and the central processing unit occupies the bus. In response to this hold request, the central processing unit returns a hold approval signal to the bus arbitration circuit at the end of the current bus operation, and reset is performed. The purpose of the present invention is to achieve the above-mentioned objective by making the system executed.

[Effect]

The reset signal generating device according to the present invention uses the reset request signal as one of the inputs of the bus arbitration circuit, issues a hold request to the CPU when there is a reset request and the CPU occupies the bus, and issues the hold request to the CPU. Reset will be permitted once approved.

〔Example〕

The present invention will be explained below based on examples.

FIG. 1 shows a schematic diagram of a reset signal generation device according to an embodiment of the present invention. Note that it is the same as the conventional example shown in Fig. 2 (
(equivalent) Components are given the same reference numerals.

A reset signal generation device according to an embodiment of the present invention includes a bus arbitration circuit 8 that generates a reset signal 7 from a reset request signal 6, and a hold approval signal 10 based on a hold request signal 9 from the bus arbitration circuit 8. It is equipped with CPU4. In the figure, 11 is a bus use request signal other than a reset request, and 12 is a bus use permission signal for the bus use request signal 11 other than a reset request.

Next, the operation will be explained. A reset request signal 6 obtained by closing the reset switch 1 is subjected to noise removal such as chattering by a waveform shaping circuit 2, and then input to a bus arbitration circuit 8. In the bus arbitration circuit 8, when all the bus use permission signals 12 based on the bus use request signal 11 other than the reset request are invalid, that is, when the bus use right is granted to the CPU 4,
Hold request signal 9 for reset to CPU 4
is generated. After completing the current bus operation in response to the hold request signal 9, the CPU 4 returns a hold approval signal 10 to the bus arbitration circuit 8. Bus arbitration circuit 8 generates reset signal 7 when this hold approval signal 10 is input. Therefore, the reset signal generation device of the present invention does not destroy the contents of the memory.

(Effects of the Invention) According to the present invention, the reset signal is generated only when the reset request signal and the hold approval signal from the CPU are valid in the bus arbitration circuit, so the CPU and other devices access the memory. Since there is no chance of drowning during the process, the memory contents will be reset without destroying them.

This provides a feature that allows for abend saves.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a reset signal generation device according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of a conventional reset signal generation device. In addition, in the drawings, the same reference numerals represent the same or equivalent parts. 6-------Reset request signal 7---Reset signal 9---Hold request signal 10---Hold approval signal

Claims (1)

[Claims] The bus arbitration circuit includes a bus arbitration circuit that receives a reset request signal and generates a reset signal, and a central processing unit that generates a hold approval signal based on a hold request signal for reset from the bus arbitration circuit, and the bus arbitration circuit generates a reset request. When a signal is input and the central processing unit occupies the bus, it outputs a hold request to the central processing unit, and in response to this hold request, the central processing unit determines the end point of the current bus operation. A reset signal generating device characterized in that a hold approval signal is returned to the bus arbitration circuit in order to execute a reset.