JPH03138980A - Thin film transistor - Google Patents

Abstract

PURPOSE:To improve conductivity by specifying the length of a thick part of a gate insulating film in a direction from the end of a source electrode toward the center of a channel. CONSTITUTION:The thickness of a gate insulating film of an amorphous silicon thin film transistor is varied along a channel direction, and so formed as to be thick at and near parts of source and drain electrodes and thin at the part in contact with the channel. The thick part LS of the film is set to 7mum or less in a direction from the end of the source electrode to the center of the channel. The length of overlapping of a gate electrode and the source electrode at the thin part of the film is 3mum or less at the drain side. Thus, conductivity can be enhanced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a thin film transistor using hydrogenated amorphous silicon (a-8i:H), which has particularly high conductivity and therefore has a large driving capacity, and has excellent switching performance. Concerning high speed thin film transistors.

[Conventional technology]

As a conventional thin film transistor (TPT), there is one described, for example, in Japanese Patent Laid-Open No. 62-26862.

FIG. 2 is a cross-sectional view of an example of the above thin film transistor.

In FIG. 2, 1 is a glass substrate, 2 is a Cr gate electrode, 3 is a SiN gate insulating film, 6 is an a-3i:H semiconductor layer, 7 is an n''a-8i:H ohmic contact layer, 10 is a source electrode, 11 is a train electrode, and 12 is a passivation electrode.The source electrode 10 and the drain electrode 11 have a laminated double structure of a Cr layer 8 and an AQ layer 9.

The characteristics of the conventional thin film transistor as described above are threshold voltage vt ~ 1v, mobility p = Q, 5cm''/
V-8EC was typical.

[Problem to be solved by the invention]

The conventional a-3i TFT as described above is an insulated gate field effect transistor, and its conductivity is usually 1.
(W/-L) ・Proportional to μ・Ci.

Here, W is the TPT channel width, L is the channel length, μ
is the electron mobility, and Ci is the gate insulating film capacitance per unit area.

The value of μ above is at most 1 depending on the a-8i material.
cm" / V-sec, and the W/L ratio can be suppressed to about 100 μm / 10 pm from the viewpoint of yield. Therefore, it is usually necessary to increase Ci, that is, to reduce the thickness of the gate insulating film. A method of effectively improving conductivity has been used.

However, if the gate insulating film is made significantly thinner while maintaining the conventional structure, insulation defects will occur due to breakage of the gate insulating film at the end face of the gate electrode, and ■ The increase in the thin insulating film area causes short-circuit defects between the gate electrode and the source and drain electrodes.

■Reducing the overall thickness of the gate insulating film has the disadvantage of increasing off-state current.

It was difficult to realize this.

The object of the invention is to increase the conductivity compared to the prior art;
An object of the present invention is to provide an amorphous silicon thin film transistor with suppressed off-state current and sufficient stability.

[Means to solve the problem]

In order to achieve the above object, the present invention varies the thickness of the gate insulating film of an amorphous silicon thin film transistor along the channel direction, making it thicker in the vicinity of the source and drain electrodes, and increasing the thickness in the region adjacent to the channel. By forming it thinly, it is possible to increase the value of Ci and to obtain stable long-term, low parasitic capacitance, and high on-current.On the source electrode side, from the end of the source electrode to the center of the channel in the direction of
The thick portion of the gate insulating film was set to 7 μm or less. On the drain electrode side, the thick part of the gate insulating film was set to be -3 μm or more in the direction from the end of the drain electrode to the center of the channel. That is, on the drain side, the amount of overlap between the gate electrode and the source electrode in the thin portion of the gate insulating film was set to 3 μm or less.

(Function) As mentioned above, the gate insulating film of the TPT has the role of indirectly transmitting the voltage applied to the gate to the carriers flowing through the channel.In the TPT according to the present invention, as shown in FIG. Since the film thickness is reduced in most of the part of the film that is in contact with the channel, it is possible to transmit more carriers.In addition, ΔLS in the same figure
and ΔL.

The gate insulating film at this portion is thicker than at most of the central portion of the channel. The results of investigating the relationship between the size of the thick portion of the gate insulating film near the source and drain electrodes and the transistor characteristics of on-current and off-current are shown in FIGS. 3 and 4. Figure 3 shows that the on-current is the thicker part of the gate insulating film on the source electrode side (hereinafter ΔL
The figure shows how it changes depending on S. The on-current here is expressed as the amount of increase in the on-current when the on-current when the gate insulating film is thick over the entire channel is set to 1. From the figure, it can be seen that as ΔLS increases, the amount of increase in on-current decreases. From the results in the same figure, the region where the increase amount is more effective is ΔLS of 7 μm at maximum,
It can be seen that it is desirable that it be less than that. Also, Δ
It can be seen that a larger on-current can be obtained in the region where LS is (-), that is, where the second gate electrode and the source electrode overlap.

On the other hand, FIG. 4 shows how the off-state current depends on the thicker part of the gate insulating film on the drain electrode side (hereinafter referred to as ΔLD). The figure shows that the larger ΔLD is, the smaller the off-state current is, and the better the transistor is. However, even if ΔLD is (-), that is, the gate electrode and drain electrode overlap in a thin part of the gate insulating film (overlap), by suppressing the amount of overlap, an extreme increase in off-state current can be suppressed. It has been shown that this is possible.

That is, it has been shown that when the amount of overlap is 3 μm or less (ΔLS is 13 μm or more), the off-state current can be particularly lower than when the overlap is larger than that.

To summarize the above explanation, in a thin film transistor in which the gate insulating film in the channel region is thinned at the center of the channel, (
1) In order to further increase the on-current, ΔLS is preferably 7 μm or less. (2) ΔLD from above to suppress the increase in off-state current
It is preferable that the thickness is -3 μm or more.

〔Example〕

FIG. 1 is a sectional view of a first embodiment of the present invention, showing a hydrogenated amorphous silicon thin film transistor (a-8i: HTFT) fabricated on a glass substrate 1. FIG.

In FIG. 1, 1 is a glass substrate, 2 is a first gate electrode, 3 is a first gate insulating film, 4 is a second gate electrode, 5 is a second gate insulating film, and 6 is a -Si:H semiconductor layer (active M), 7 is an n''a-8i:H ohmic contact layer, 10 is a source electrode, and 11 is a drain electrode.The source electrode 10 and the drain electrode 11 are
It has a laminated double structure of Cr ffl 8 and 10 layers 9.

This transistor has gate electrodes 2, 4 . Source electrode 1
This is an insulated gate field effect transistor having three electrodes, 0 and 11.

Next, the manufacturing method will be explained.

First, Cr is deposited to a thickness of 1000 nm on a glass substrate 1 by a sputtering method, and a first gate electrode pattern 2 is formed using an ordinary photolithography technique.

Next, the first gate insulating film 3 is formed by plasma CVD method.
Then, a SiN film is deposited to a thickness of 3,000 layers (tslN in FIG. 3), and Cr is deposited thereon to a thickness of 400 layers to form the second gate electrode 4.

Subsequently, by CVD, a SiN film was deposited to a thickness of 400 mm (tstsa in FIG. 3) as the second gate insulating film 5, and then an intrinsic a-8i:H film was deposited to a thickness of 2000 mm as the semiconductor layer 6. Further, as an ohmic contact layer 7, an n''a-8i:H film is deposited to a thickness of 400 mm.

In each of the above steps, the formation of the second gate insulating film 5 and subsequent films was performed in the same chamber while changing the gas type. When switching, first evacuate the chamber (
The purity of the film was maintained by using a back pressure of 10”@Torr or less.The gas species during the SiN film formation were SiH,
,N.

The a-8i:H film is formed using a mixture of three types of NH and Si.
A mixed gas of H4 and hydrogen was used. Furthermore, PH3 gas diluted with hydrogen was used for n+ doping.

After the film was deposited as described above, the a-Si:H film was processed into an island shape, and then Cr layers 8 and 10 layers 9, which were to become source and drain electrodes, were formed by sputtering. In addition,
The thickness of the Cr layer 8 is 500, and the thickness of the 10 layer 9 is 4000.
It's a person.

After forming the above Cr layer 8 and 10 layer 9, the Cr layer 8 and AQf@9 above the channel are offset by about 1μ so that the source electrode 10 and drain electrode 11 do not overlap with the second gate electrode 4. The n''a-8i:H layer 7 was etched off using a process step and removed in a shape that overlapped with the first gate electrode 2 by 2 μm or more, and using this as a mask.

Through the above steps, the TPT process is completed and the transistor operation can be confirmed, but a protective film 12 (not shown) of SiN film is further formed thereon to stabilize the characteristics.

Next, the operation and characteristics of the transistor according to the present invention will be explained.

FIG. 5 is a diagram schematically showing the current path of the transistor according to this embodiment.

In the illustrated current path IP, the effective insulating film thickness is tSiN+t5LNz in the portion where the source electrode 10 and the first gate electrode 2 overlap, and is tstNz on the second gate electrode 4.

If there is no first gate electrode 2, this TPT is just an offset transistor with a gate insulating film thickness of tStNz, and charge injection from the source electrode 10 is limited. However, in the present invention, the first gate electrode 2 acts to promote this charge injection.

In addition, in this example, since ΔLS = ΔLD = 1 μm, the film thickness profile is such that the electric field applied to the gate insulating film is reduced in the region where the electric field is most concentrated in the TPT. The TPT structure can be made smaller compared to simply making the gate insulating film thinner.

FIG. 6 shows the W/
FIG. 4 is a diagram showing the relationship between gate voltage Vg and drain current Id when L (channel width/channel length)=50/11 and the source is grounded and the drain voltage (Vo) is 10V. Note that the potentials of the first gate electrode 2 and the second gate electrode 4 were the same.

As shown, the obtained characteristics are the threshold voltage v t
= i, avt', and the on-current at Vg = 10V was 3.3 x 10-''A.

In addition, in FIG. 6, the characteristics of the conventional structure TPT (gate insulating film thickness 3000 mm) are shown by broken lines, and the on-current in this case is 1.3 It can be seen that TPT has a current driving capacity two to three times that of the conventional one.

Also, looking at the comparison of off-state current in Figure 6, Vg=-1
At 0V and Vo=10V, the off-state current Id in the conventional TPT is 7 x 10-13A, and in this embodiment it is 2 x 10-11A.

In this way, in the transistor of this example, as the on-current increases, the off-current also increases. However, the off-state current is suppressed to a value lower than the order of 10-1aA, and can be said to be a value that does not pose any problem at the level of this embodiment. Such an effect,
That is, the increase in on-current is due to the thinning of the gate insulating film at the center of the channel portion, and the reason that the off-current does not increase to an extreme level is due to setting ΔLD to 1 μm. As described above, in order to further increase the on-current, it is possible to achieve this by making ΔLS=1 μm smaller in this embodiment and by making the gate insulating film on the second gate electrode thinner.

Also, if you want to further reduce the off-state current, use ΔL.

What can be achieved by increasing the value from 1 μm in this embodiment as described above is as described above.6 Note that the present invention is not limited to the above-mentioned embodiment. In particular, the material of the second gate electrode 4 is not limited to Cr; for example, CVD
n”a-8iH formed by the method.
The gate insulating film 3 and the second gate insulating film 5 are made of SiN
It is not limited to , and it is not necessary that the two are the same. Furthermore, in this embodiment, considering the bidirectionality of the device, the second gate electrode 4, the source electrode 10, and the drain electrode 11 are connected to each other.
Although an offset is provided for both electrodes, the effects of the present invention will not be lost even if the electrodes are configured to overlap with one of the electrodes.

Moreover, the first gate electrode 2 and the second gate electrode 4 are
Usually, they are commonly connected on a pattern or by external connection and used at the same potential, but they can also be made independent and used at different potentials.

Example 2 FIG. 7 is a sectional view of a second embodiment of the present invention.

In this embodiment, there is one gate electrode, but the gate insulating film has a two-layer structure.

In FIG. 7, first, a gate voltage tf is placed on the glass substrate 1.
After forming the gate electrode 12, a first gate insulating film 3 is deposited thereon, and a desired pattern portion on the gate electrode 2 is removed. Next, SiN, which will become the second gate insulating film 5, is deposited to a thickness of 40 mm.
Deposited on 0 people. The subsequent steps are the same as those in the embodiment shown in FIG. 1, except that ΔLS=-
1 μm.

The source and drain electrodes were processed so that ΔLD-2 μm, and the transistor shown in FIG. 7 was obtained.

Conotransistor (7) The on-current at Vg=10V and Vo=10V is 5.5 times that of a transistor with a conventional structure, and the off-state current at Vg=-10V and Vo=10V is I x 10-" I was able to get it below A.

Example 3 The next example will be described with reference to FIG. The transistor according to this embodiment is intended to be bidirectional, that is, a transistor in which the source and drain can be switched depending on the driving conditions, as seen in switching transistors for liquid crystal displays. FIG. 8 shows a cross section of the transistor of this example. The method for manufacturing this transistor is the second
Example 1 is manufactured in the same manner up to the formation of the gate electrode.

Next, SiN is deposited to a thickness of 400 mm as the second gate insulating film 5 by, for example, CVD method, and then CVD
By the D method, the a-8i layer was formed into a film thickness of 8 as the semiconductor layer 6.
After that, SiN was deposited as a protective film 21 to a thickness of 0.2 μm using the CVD method. after that,
The protective film 21 was processed by photoetching so as to have the channel length. On top of this, 300 layers of conductive amorphous silicon (a-8i (n")) were deposited by the CVD method to form an ohmic contact layer 7. Next, the semiconductor layer 6 was processed into an island shape. At this time, the ohmic contact layer 7 at the center of the protective film 21 was also removed.Next, the method of depositing and processing Cr and AQ was as described in Example 1.
The same is true. The transistor thus obtained is the 8th transistor.
The result will be as shown in the figure.

ΔLS in this transistor is the protective film 2 on the source side.
is the distance from the end of 1 to the end of the second gate electrode,
Similarly, ΔLD is the distance from the end of the protective film 21 on the drain side to the end of the second gate electrode. In this example,
Processing was performed so that both ΔLS and ΔLD were 2 μm. Further, the channel length was 6 μm and the channel width was 307 Am. That is, the W/L of the channel is 5. To use this transistor in a liquid crystal display, a pixel electrode must be formed.

Formation of passivation It is necessary to form the necessary components as a pond display. However, the operation of this transistor will be described here, and the method for manufacturing the display panel will be omitted.

Transistors used in liquid crystal displays and the like operate bidirectionally. That is, the source and drain are interchanged depending on operating conditions. This is because the liquid crystal needs to be driven with alternating current. For example, while driving the gate electrode in pulses at Vg±17.5V, a video signal is input to electrode 11 (used as a drain electrode) in FIG. 8. Then, a video signal is transmitted to the 12th electrode side when Vg is +17.5V.

Here, the voltage of the video signal varies depending on the brightness, and the voltage of the video signal varies depending on the brightness.
It varies from v to ±13V. When the video signal is (+), the 11th electrode correctly works as a drain, while for a (-) signal, the 11th electrode works as a source because the direction of current flow is reversed. Thus, a change in the signal voltage means that even if Vg is constant, the potential between the gate and the drain is changing. In other words, this is equivalent to a change in the substantial gate voltage. FIG. 9 shows the results of examining the dependence of the drain current (more) on the drain voltage (VD) of the transistor according to this example at various Vg values. Display driving conditions (7) Vg=+17.5V, signal voltage Vo=+13V. The driving operation range of the transistor is the hatched area surrounded by the solid line in the figure. On the other hand, in the diagram, a transistor with a conventional structure (W
/L=5) is shown by a hatching surrounded by a dotted line. From the figure, it can be seen that even though the transistors are the same size, the operating range of the transistor according to this example is very wide and the signal current that can be handled is large.
were both 2 μm, and the characteristics shown in FIG. 9 were obtained no matter which one served as the drain. In addition, the drive current is more than three times that of a transistor with a conventional structure.Although the present invention has been described above with reference to examples, the gist of the present invention is not limited thereto. For example, the type of insulating film is not limited to SiN, but also Sin, 5iON, Ta, ○
, or Aff20. etc. may be used. In addition, the semiconductor layer is not limited to a-8i:H, but also a-Ge:H, a-C:H.
Alternatively, it may be an alloy of these. Furthermore, the first and second gate insulating films are made of SiN, SiO, or Si.
Of course, a combination of N and 5iON or the like may also be used.

〔Effect of the invention〕

As described above, according to the present invention, the conductivity of an a-8i:H thin film transistor can be increased compared to conventional transistors. Therefore, it is necessary to reduce the size of the transistor to flow the same current, so this T
If PT is used as a switching transistor for a liquid crystal display, great effects can be obtained from both the manufacturing and characteristic aspects.

In addition, since the current drive capability is large, a-Si:HTFT
It also has a huge effect on the production of integrated circuits. Therefore, circuit configurations that were difficult to realize in the past are now possible, and the economical effects are significant.

In addition, in the transistor of the present invention, ΔLS and ΔLD are
By selecting an appropriate transistor according to the method of use, it is possible to create a transistor with a larger on-current, or a transistor that does not deteriorate its off-characteristics while increasing the on-current.
Furthermore, it is possible to obtain a bidirectional transistor that takes advantage of numerous characteristics, such as a transistor with a large on-current.

[Brief explanation of the drawing]

Fig. 1 is a sectional view of the first embodiment of the present invention, Fig. 2 is a sectional view of an example of conventional TPT, Fig. 3 is an experimental result showing the effects of the present invention, and Fig. 4 is the effect of the present invention. Experimental results showing 5th
The figure is a cross-sectional view showing the current path of the transistor of the present invention, Figure 6 is a characteristic diagram comparing the transistor characteristics of the first embodiment with the conventional transistor characteristics, and Figure 7 is the second embodiment of the present invention.
FIG. 8 is a cross-sectional view of the third embodiment of the present invention, and FIG. 9 shows the operating characteristics showing the driving operation range when the transistor of the third embodiment is used in a liquid crystal display.
FIG. 3 is a diagram showing operating characteristics compared with those of a conventional transistor. 1... Glass substrate 2... First gate electrode 3... First gate insulating film 4... Second gate electrode 5... Second gate insulating film 6... a- 8i:H semiconductor layer 7...n''a-5i ohmic contact layer 8...
・Cr layer 9...Afi layer 10...Source electrode 11...Drain electrode 12...Base base 21...Protective film response / Z $L wind 11--Drain f pole 31! l ΔLCD (μm hard disk left diagram

Claims (1)

[Claims] 1. An active layer consisting of a semiconductor layer formed on a semiconductor substrate or an insulating substrate, a gate insulating film, a gate electrode, a source electrode, and a drain electrode, the film thickness of the gate insulating film being , in a thin film transistor that is thick in the vicinity of both or one of the source and drain electrodes and thin in the part that contacts the channel between the source and drain electrodes, the gate The length of the thick part of the insulating film (ΔL_
A thin film transistor characterized in that S) is 7 μm or less. 2. It has an active layer consisting of a semiconductor layer formed on a semiconductor substrate or an insulating substrate, a gate insulating film, a gate electrode, a source electrode, and a drain electrode, and the film thickness of the gate insulating film is equal to that of the source electrode and the drain electrode. In a thin film transistor, the thickness of the gate insulating film is increased in the direction from the edge of the drain electrode to the center of the channel in a thin film transistor that is thick in the vicinity of both or one of the electrodes and thin in the part adjacent to the channel between the source and drain electrodes. The length of the thick part (ΔL
A thin film transistor characterized in that _D) is -3 μm or more.