JPH0313675B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a mask using MOS transistors.
Read-only semiconductor storage devices such as ROM and PROM,
In particular, the present invention relates to a read circuit of a read-only semiconductor memory device.

[Conventional technology]

Conventionally, as a technology in this field,
Some of these are described in Japanese Patent Publication No. 59-75495, Japanese Patent Application Laid-Open No. 59-77700, Japanese Patent Publication No. 13117-1980, etc.
The general configuration will be explained below using the drawings.

FIG. 2 is a block diagram showing an example of the configuration of a conventional read-only semiconductor memory device (ROM).
In FIG. 2, 1 is a memory cell matrix,
This memory cell matrix 1 is, for example, an N channel.
A large number of memory cells 2 consisting of MOS transistors
-11 to 2-1n, . . . , 2-m1 to 2-mn are arranged in a matrix. A plurality of word lines 3-1 to 3-m made of polysilicon, polycide, etc. are arranged in the row direction of the memory cell matrix 1, and a plurality of data lines 4 made of aluminum, etc. are arranged in the column direction. -1 to 4-n are arranged.
Each word line 3-1 to 3-m corresponds to a memory cell 2-11 to 2-1n, . . . , 2- in the row direction, respectively.
The data lines 4-1 to 4-n are connected to the gates of the memory cells 2-11 to 2-m1,..., 2-1n to 2-n in the column direction, respectively.
Connected to the drain of mn. Memory cells 2-11 to 2-m1, ..., 2-1n to 2- in the column direction
The sources of mn are each connected to a common line 5-1-m, and the source of the power supply voltage _Vss (for example, OV
or a voltage close to it) is given.

On the other hand, each word line 3-1 to 3-m is connected to a word line decoder 7, and each data line 4-1
4-n are connected to a sense amplifier (read amplifier) 10 via a multiplexer 8. Multiplexer 8 is controlled by data line decoder 9. Here, the word line decoder 7 and the data line decoder decode encoded input signals 11 and 12, respectively, and output one selection signal. One of the word line decoders 7 decodes the input signal 11 and outputs a selection signal to one of the word lines 3-1 to 3-m. The other data line decoder 9 has a plurality of output lines 13-1 to 13-n.
The decoded selection signal is connected to the multiplexer 8 via the output line 13-1 to 13-n.
is applied to multiplexer 8 via. The multiplexer 8 selects one input signal from a plurality of input signals, and has a plurality of switch elements 14-1 to 14-n made of, for example, MOS transistors, and each of the switch elements 14-1 to 14-n gates are connected to each output line 13-n to 13-1, respectively, and each switch element 14-1 to 14
The source of -n is connected to each data 4-n to 4-1, and the drain is connected to the sense amplifier 10 via a common line 15 and a terminal 16, respectively. Therefore, when the selection signal of the data line decoder 9 is applied to any of the output lines 13-1 to 13-n, any of the switch elements 14-n in the multiplexer 8
1 to 14-n are turned on, and as a result, any data line 4 connected to this turned-on switch element
-n~4-1 and sense amplifier 10 are common line 15
and will be connected via the terminal 16.

The sense amplifier 10 is connected to the memory cell matrix 1
This circuit detects the storage state of a selected memory cell (for example, conduction or non-conduction of a memory cell), and transfers data to the selected memory cell by the data line decoder 9, multiplexer 8, and word line decoder 7. Lines 4-1 to 4-n and common line 5-1
~5-n, and detect the storage state of the selected memory cell from this outflow current;
It is output from the data output terminal 17 as read data. Note that conduction or non-conduction of a memory cell depends on the presence or absence of wiring in each memory cell, the shape of the MOS transistor, or the electrical properties of the MOS transistor (for example, if it has a floating gate and electrons are injected into the floating gate). Data is written into the memory cells in advance using this distinction. In addition, 1 in Figure 2
8 is a stray capacitance of the data line 4-n, which occurs in each of the data lines 4-1 to 4-n, respectively.

FIGS. 3 1 and 2 explain the structure of a memory cell consisting of a MOS transistor in FIG. 2. For example, FIG.
A plan view of a MOS transistor corresponding to 2-12,
3 is a sectional view taken along line A--A in FIG. 3.

As shown in FIG. 3, MOS transistors 2-11 and 2 formed on a P-type semiconductor substrate 20
-12 is a word line 3-1 made of polysilicon.
and data lines 4-1 and 4-2 each made of aluminum. Each data line 4-1, 4-2 is connected to an N ⁺ region 2 formed in a P-type semiconductor substrate 20 through an opening 21-1, 21-2.
2-1 and 22-2, respectively. Further, other N ⁺ regions 23-1, 23-2 are formed on the P-type ^{semiconductor} substrate 20, facing these N ⁺ regions 21-1, 21-2.
The power supply voltage V _SS is applied to. Further, as shown in FIG.
A word line 3-1 made of polysilicon is placed between the N ⁺ regions 22-1 and 23-1 with a gate oxide film 24 interposed therebetween, and a word line 3-1 made of polysilicon is placed above the word line 3-1 with an intermediate insulating film 25 interposed therebetween. Data 4-1 consisting of amyl is arranged.

MOS transistor 2-
11, 2-12, a high voltage that forms a channel under the gate oxide film 24 (or increases the conductance of the channel) is applied to the word line 3-1, and the data lines 4-1,
4-2 to one N ⁺ region 22-1 and the other
When a voltage higher than the voltage V _SS of the N ⁺ region 23-1 is applied, the MOS transistors 2-11, 2-12
becomes conductive, and the data lines 4-1 and 4-1 on the high potential side become conductive.
4-2 → N ⁺ region 22-1 → N ⁺ region 2 on the low potential side
Current flows to 3-1.

Note that the MOS transistors 2-11, 2-
12 etc., the presence or absence of contact openings 21-1, 21-2 and the gate oxide film 24 are required.
This is done by using changes in the concentration of P-type impurities underneath, or by inserting a floating gate between the gate oxide film 24 and the word line 3-1 and using the presence or absence of charge in the floating gate. .

Next, a read operation of the ROM configured as above will be explained.

For example, memory cell 2-1n shown in FIG.
To read the memory contents of memory cell 2-1,
Signals 11 and 12 containing n address information are applied to the word line decoder 7 and data line decoder 9. Then, the selection signal output from the data line decoder 9 is applied to the output line 13-1, and this selection signal causes the switch element 1 in the multiplexer 8 to be
4-1 is turned on, and the data line 4-n and the sense amplifier 10 are electrically connected via the common line 15 and the terminal 16. At the same time, the potential of the word line 3-1 selected by the word line decoder 7 rises, and at the same time, a high voltage is applied from the sense amplifier 10 to the data line 4-n and a current is supplied. As a result, the stray capacitance 18 of the selected data line 4-n is charged, and the potential of the data line rises. After the potential of the data line 4-n rises, the sense amplifier 10
Now, the impedance of the memory cell 2-1n is determined by measuring the potential when a constant current flows into the data line 4-n or the current flowing into the data line 4-n when a constant voltage is applied. 2-1n is detected to be conductive or non-conductive (i.e., the stored contents) and output from the output terminal 17 as read data.

[Problem that the invention seeks to solve]

However, in the ROM having the above configuration, the capacitive load that the word line decoder 7 must drive is large, and as a result of this increasing as the ROM becomes highly integrated, signal propagation to the ends of the word lines 3-1 to 3-m is cause a delay. For example, in a ROM of about 256 kbit, when polysilicon is used as the wiring material for word lines 3-1 to 3-m, the data output delay due to delay in the word line circuit system accounts for more than 1/3 of the entire ROM. . There is a problem in that such a delay in signal propagation reduces the read speed. This problem will be further explained below with reference to FIG.

FIG. 4 is a circuit diagram in which memory cells 2-11 to 2-1n related to word line 3-1 in FIG. 2 are extracted. In FIG. 4, if memory cell 2-1n is selected, unselected memory cells 2-11 to 2
Because of the capacitance component (MOS capacitance) between the gate of -1(n-1) and the ground, a load capacitance is connected between the gate of the memory cell 2-1n and the ground.
The number of unselected memory cells 2-11 to 2-1 (n-1) serving as load capacitance of the word line 3-1 increases dramatically as the degree of integration increases. For example, in the case of a 256 kbit ROM, even if the word line decoder 7 is placed in the center of the memory cell matrix 1 in order to prevent delays in signal transmission speed and reduce the power consumption of the word line decoder, the number of memory cells and matrix When there are 512 x 512 pieces, one word line
256 memory cells are arranged. Considering the resistance R of the word line made of polysilicon as the word line length increases due to high integration, one word line has a ladder-shaped RC with MOS capacitor C and resistor R.
form a delay line. This causes a signal propagation delay, which slows down the read speed of the MOS.
At this time, the source of each memory cell 2-11 to 2-1n is at _Vss potential, which is a major reason why the load capacitance mentioned above cannot be ignored.

More specifically, unselected memory cell 2-11
When the source and drain of each MOS transistor forming 2-1 (n-1) are at _Vss potential, as the potential of the word line 3-1 rises, unnecessary MOS transistors form under the gate oxide film. This will form an inversion layer, or channel. In this case, although the electrons in the inversion layer are originally unnecessary, they increase as the word line potential rises, so the same amount of charge must be supplied to the gate of the MOS transistor through the word line 3-1. , the word line potential cannot be increased. Therefore, the word line decoder 7 supplies a large amount of charge to the selected load line 3-1 via the driver within the word line decoder, even though most of the charges are unnecessary when the word potential increases. Is required.

In reality, the data lines 4-1 to 4-(n-1), which continue to be in the non-selected state, are connected to the memory cells 2-11 to 2-2 at the intersection with the selected word line 3-1.
-1(n-1) (note that this memory cell is selectively turned on by writing data), the charge accumulated in the stray capacitance during past selection is released and the potential becomes _Vss . Most of them are in the same condition. With the improvement in ROM integration, the data lines 4-1 to 4-4 assume this _Vss potential state.
The number of -(n-1) also increases. Naturally, when the power is turned on, all data lines 4-1 to 4-n are _{at Vss.}
Located at electric potential. These data lines 4-1 to 4-(n
-1) is the word line 3- selected as described above.
1 is applied to each memory cell 2-11 to 2-1 (n-
At the same time as the threshold voltage of the MOS transistor forming 1) is exceeded, an inversion layer of the MOS transistor existing at the intersection point is formed. Therefore, the gate oxide film of this MOS transistor becomes an insulating film, resulting in a MOS capacitor with an extremely narrow electrode spacing, creating a condition in which a non-negligible capacitive load is formed. This has caused a problem in that a word line propagation delay occurs due to an increase in word line load capacitance, resulting in a slow reading speed.

The present invention provides a high-speed read device that solves the problems of the prior art, such as an increase in word line load capacitance due to unselected memory cells and a word line propagation delay caused by this. .

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a read-only semiconductor memory device in which a current can flow into a sense amplifier from at least one selected data line among a plurality of data lines during reading. The sense amplifier is configured to detect the storage state of the selected memory cell based on this current inflow amount.

[Effect]

According to the present invention, in a read-only semiconductor memory device configured as described above, both the data line on the sense amplifier side centering on the memory cell and the common line on the opposite side are maintained at a high potential, and the selected data line is selected at the time of reading. When the memory cell that has been switched on is turned on, only the data line on the sense amplifier side of that memory cell becomes a low potential, and a current flows to the sense amplifier via the data line. Thereby, the sense amplifier works to detect the storage state of the selected memory cell from the amount of current flowing in. Moreover, since the sources and drains of non-selected memory cells in an off state are at a high potential during reading, channel formation is prevented and the selected word line does not become a load capacitor. This allows the load capacitance of the selected word line to be reduced.
Therefore, the above-mentioned problem can be eliminated.

〔Example〕

FIG. 1 is a block diagram of a read-only semiconductor memory device (ROM) showing an embodiment of the present invention.
In FIG. 1, the same elements as those in FIGS. 2 to 4 are given the same reference numerals.

The difference between this ROM and the one in FIG. 2 is that each memory cell 2-11 to 2-1n, ..., 2-
A potential line 100, a pressure reducing circuit 101 and a power supply 1 are connected to the terminal 6 commonly connected to the drains of m1 to 2-mn.
02 in series, and each data line 4-1
~4-n multiplexer 8 and the opposite end thereof are resistors 103-1 to 103 for preventing potential drop, respectively.
-n, and the resistors 103-1 to 103-n
is connected to the terminal 6 via the common line 104. Furthermore, the common line 1 is connected via the terminal 105.
The sense amplifier 106 connected to the terminal 1
The memory state of one of the selected memory cells 2-11 to 2-mn is detected based on the amount of current flowing from 05 to 2-mn, and is output from the output terminal 107.

Here, the pressure reducing circuit 101 has a configuration in which two enhancement type MOS transistors 120 and 121 are connected in series as a load MOS. Therefore, the power supply voltage V _cc (for example, +5V) is applied to the power supply terminal 102.
When V cc is applied, the pressure reducing circuit 101 reduces the power supply voltage V _cc
and a low potential _Vss (for example, 0V or a voltage close to it) in the sense amplifier 106, which will be described later, are lowered and applied to the terminal 6. This suppresses the potential amplitude of the data lines 4-1 to 4-n due to switching of the memory cells 2-11 to 2-mn from becoming unnecessarily large, thereby preventing an increase in power consumption and a decrease in signal propagation speed. ing.

The resistors 103-1 to 103-n connected to each data line 4-1 to 4-n are connected to the unselected data line 4-n.
Memory cell 2-1 to which 1 to 4-n are connected
This is to prevent the potential from decreasing due to current leakage due to a PN junction or the like within 1 to 2 mn. Therefore, the resistors 103-1 to 103-
n has a resistance value sufficiently large compared to the current drive capability of memory cells 2-11 to 2-mn.

FIG. 5 shows an example of the circuit configuration of the sense amplifier 106 shown in FIG. 1. This sense amplifier 106
A conversion circuit 130 that converts the amount of current input from the input terminal 105 into an amount of voltage, and a conversion circuit 13
Reference voltage circuit 140 that creates a reference voltage of 0
, a differential amplifier circuit 150 that amplifies the output voltage difference between the conversion circuit 130 and the reference voltage circuit 140, and an inverter 160 that amplifies the potential amplitude of the output of the differential amplifier circuit 150 and outputs it from the data output terminal 107.
It consists of

Here, in the conversion circuit 130, enhancement type MOS transistors 131 and 132 and a depletion type MOS transistor 133 are connected in series, and an input terminal 105 is connected to the drain side of the MOS transistor 131.
The source and gate of the MOS transistor 133 are connected. Such a conversion circuit 13
Reference voltage circuit 1 provided in parallel opposite to 0
4 is an enhancement type MOS transistor 1
41, 142 and a depletion type MOS transistor 143 are connected in series, and the drain side of the MOS transistor 142 is connected to the MOS transistor 1.
41, 142, and 143 and the gate of the MOS transistor 132, respectively.

and a conversion circuit 130 and a reference voltage circuit 140
In this case, the MOS transistor 131 is selected to have a suitably higher current driving ability than the MOS transistor 141, and the MOS transistors 132, 142, and 1
Transistors 33 and 143 each have the same characteristics. In addition, the MOS transistor 131,
The source of MOS transistor 141 is held at power supply voltage V _ss , and the drain of MOS transistors 133 and 143 is applied with power supply voltage V _cc . In addition, MOS
Terminal section 133a on the gate side of transistor 133
is a part whose potential changes depending on the storage state of memory cells 2-11 to 2-mn, MOS transistor 1
42 source side terminal portion 142a, data line 4-
1 to 4-n and the part whose potential is compared, and MOS
Terminal section 143a on the gate side of the transistor 143
is a constant voltage portion that is compared with the corresponding terminal portion 133a.

The differential amplifier circuit 150 also includes a common MOS
A transistor 151 and a MOS transistor 15 connected in parallel to this MOS transistor 151
2,153 and MOS transistors 154,15
It consists of 5 and more. Here, the power supply voltage V _cc is applied to the gate of the common MOS transistor 151, and the power supply voltage V _ss is applied to the source, and
The terminal portions 133a and 143a are connected to the gates of the MOS transistors 152 and 154, respectively. If there is a difference between the input voltages applied from the terminal sections 133a and 143a, this voltage difference is amplified by the MOS transistors 152 and 154, and
It is output from the gates of MOS transistors 153 and 155 and applied to inverter 160. This inverter 160 includes an enhancement type MOS transistor 161 and a depletion type MOS transistor for the load.
It is composed of a series circuit with a MOS transistor 162. When the output voltage of the differential amplifier circuit 150 is applied to the gate of the MOS transistor 161, this is amplified by the MOS transistor 161.
The data is output from the drain of the MOS transistor 161 to the data output terminal 107.

Note that the MOS transistor 13 connected to the terminal 6 etc. in FIG. 1 and the power supply voltage V _ss in FIG.
1, 132, etc., the circuit structure is such that a current can flow from a selected data line (for example, one of 4-1 to 4-n) to the sense amplifier 106 during reading.

Next, the operation of the ROM configured as described above will be explained with reference to FIGS. 1, 5, and 6. Note that FIG. 6 shows the word line 3- in FIG.
2 is a circuit diagram in which memory cells 2-11 to 2-1n according to FIG. 1 are extracted. FIG.

First, in FIG. 1, the word line decoder 7 and the data line decoder 9 respectively
-1 to 3-m and one each of data lines 4-1 to 4-n, for example 3-1 and 4-n, are selected. Here, regarding the data lines 4-1 to 4-n, the data line that had been selected just before was in a conductive state with the sense amplifier 106 and therefore has a potential close to the power supply voltage _Vss . and the newly selected data line 4-n
quickly reaches a potential close to _Vss after selection, but the other unselected data lines 4-1 to 4-(n-1) are all connected to terminal 6 due to non-conduction with the sense amplifier 106.
becomes the same as the potential of The potential of terminal 6 is the voltage V _cc
Since it is the intermediate potential of V _ss , V _cc = +5V, V _ss = 0
So, it is about +3V. For example, if the ROM
In the case of 256 kbit, 8 data output, the number of data lines 4-1 to 4-n corresponding to one data output is 64.
Since the number of sense amplifiers is about 1, two of them are 1 sense amplifier.
05, the remaining 62 unselected data lines 4-1 to 4-(n-1) have a potential of about 3V.

In this state, the selected word line 3-1 increases its potential, but each memory cell 2-11 to
When 2-mn is composed of enhancement-type MOS transistors and the threshold voltage of each MOS transistor is V _T , a channel does not begin to form unless the potential rises to (V _T +3V). Therefore, the amount of charge required to raise the potential to that point is
It is extremely small because it is only needed to form a depletion layer under the gate oxide film of the MOS transistor and to charge the source/drain capacitance when current is cut off.

In reality, the enhancement type MOS transistors that constitute memory cells 2-11 to 2-mn are:
Due to the narrow channel effect, the substrate effect is greatly affected by the high concentration impurity under the transistor isolation oxide film. Therefore, the above potential (V _T +3V)
In the state of , the semiconductor substrate 20 of the MOS transistor
is subjected to a substrate bias of 3V, so the threshold voltage V _T is 1 to 2V, especially 2 to 3V in an electrically writable EPROM. Therefore, in reality, unselected memory cells 2-11 to 2-1
(n-1) MOS transistor, word line 3
-1 rises to the power supply voltage _Vcc , almost no channel is formed. Therefore, as shown in FIG. 6, unselected memory cells 2-11 to 2-1 (n-
1) does not become the load capacitance of the word line 3-1, so the load capacitance of the word line 3-1 becomes extremely small, and its propagation delay is significantly improved.

Also configures the selected memory cell 2-1n.
As for the MOS transistor, it turns on and conducts with the sense amplifier input terminal 105.
Since the source potential is approximately _Vss potential, this MOS
Current flows from the drain of the transistor to the sense amplifier 106 via the source, and the sense amplifier 1
Memory cell 2- selected from the current inflow amount in 06
1(n-1) memory contents are detected. As described above, since the source potential of the memory cell 2-1n is approximately the _Vss potential, the current driving capability is equivalent to that of the conventional current drain type sensing method as shown in FIG. Therefore, the amount of current that the sense amplifier 106 should detect is the same as in the conventional method.

Further, when detecting this current inflow, unless the potential to be detected is kept sufficiently low, it will not be possible to secure the same amount of current from the memory cell 2-1n as in the conventional method. However, sense amplifier 10
By configuring 6 as shown in FIG. 5, for example,
It becomes possible to lower the detection potential to about (V _ss +0.1V).

That is, in the circuit shown in FIG. 5, the input terminal 105 is connected to one data line selected by the data line decoder 9, for example, 4-n. If no current flows in from the input terminal 105, the potential of the terminal portion 133a becomes slightly lower than that of the terminal portion 143a. On the other hand, if a current flows in from the terminal 105, the drain potential of the MOS transistor 131 increases slightly and becomes higher than the potential of the terminal portion 142a, so that the potential of the terminal portion 133a becomes higher than the potential of the terminal portion 143a. Therefore, by amplifying such a state with the differential amplifier circuit 150 and the inverter 160, a desired data output can be obtained from the output terminal 107.

In addition, the data line 41 by the data line decoder 9
During the switching from 4-n to 4-n, there is a possibility that a large amount of charge that had been charged in the floating capacitance of the selected data line before switching flows into the input terminal, resulting in a large potential rise. Since such a rise in potential causes malfunction of the sense amplifier 106, it is necessary to quickly release the charge to quickly lower the increased potential. In the sense amplifier 106 in FIG. 5, the input terminal 105 has a normal detection level (for example,
0.1V) or more, the terminal section 13
The potential of 3a rises to the same width, and this causes the MOS
Transistor 131 rapidly increases its current driving capability. Then, the potential of the terminal 105 drops to the normal detection level in a short time, so that malfunction of the sense amplifier 106 can be prevented.

Therefore, in this embodiment, at the time of selection,
Non-selected data lines, e.g. 4-1 to 4-1 (n-
Set the potential of 1) to the intermediate potential between V _cc and V _ss , and
Since the potential of the selected word line, for example 3-1, is set to a high potential, the unselected memory cells 2-11 to 2-1
The gate and source of (n) are both at a high potential to prevent channel formation. Therefore, the unselected memory cells 2-11 to 2-1 (n-1) do not become a load capacitance of the selected word line 3-1. Since the load capacitance of the selected word line 3-1 is reduced in this way, the word line 3-1 signal propagation becomes faster, and therefore the ROM
It is possible to increase the read speed of the data. Furthermore, since the load capacitance of the selected word line 3-1 is small, the capacitance of the driver in the word line decoder 7 for supplying charge to the selected word line 3-1 can be reduced, and the design of the driver is therefore easy. At the same time, current consumption can be reduced.

In the above embodiment, if the voltage reducing circuit 101 is omitted, the potential of the unselected data line becomes _Vcc , which is higher than the intermediate potential between _Vcc and _Vss . Then, the potential amplitude of the data line increases as the potential increases, and although the read speed becomes slightly slower, there is an advantage that the circuit configuration becomes simpler.

〔Effect of the invention〕

As explained in detail above, according to the present invention,
The circuit structure is such that a current can flow into the sense amplifier from at least one selected data line among the plurality of data lines during reading, and the storage state of the selected memory cell is detected based on the amount of current flow. Since the sense amplifier is configured, unselected memory cells do not become a word line load capacitance, and the word line load capacitance at the time of word line switching is reduced. Therefore, the signal propagation speed becomes faster, and the data read speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a ROM showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a conventional ROM, and FIG.
2 is a diagram explaining the structure of the memory cell in Figure 2, Figure 4 is a diagram explaining the operation of Figure 2, Figure 5 is a circuit diagram of the sense amplifier in Figure 1, and Figure 6 is the operation of Figure 1. It is an explanatory diagram. 1...Memory cell matrix, 2-11 to 2-
mn...Memory cell, 3-1 to 3-n...Word line, 4-1 to 4-n...Data line, 5-1 to 5-
n, 15, 104... common line, 7... word line decoder, 8... multiplexer, 9... data line decoder, 101... pressure reducing circuit, 103-1 to 1
03-n...Resistor, 106...Sense amplifier.

Claims (1)

[Claims] 1 Arranged in a matrix and at least one
A plurality of memory cells having a MOS structure, a plurality of word lines arranged in a row direction and connected to gates of the memory cells having the MOS structure, and sources or drains of the memory cells having the MOS structure arranged in a column direction. A read-only semiconductor comprising: a plurality of data lines connected to the plurality of data lines; and a sense amplifier selectively connected to the plurality of data lines and detecting the storage state of a memory cell selected via the data lines and word lines. In the memory device, the source and drain sides of the memory cell are held at a higher potential than the input side of the sense amplifier, and the sense amplifier is connected from at least one selected data line among the plurality of data lines during reading. A read-only semiconductor memory device, characterized in that the circuit is configured to allow current to flow into the memory cell, and the sense amplifier is configured to detect the storage state of the selected memory cell based on the amount of current flowing into the memory cell.