JPH03136336A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the formation of a damage layer or defects on a substrate surface and prevent the deterioration in element characteristics, by a method wherein, at the time of forming a polycide gate, only the upper layer is patterned in a gate shape by utilizing the difference of etching rate, and impurities for forming a source and drain region are ion-implanted through a lower polysilicon layer. CONSTITUTION:After a thick conducting polysilicon layer turning to the material of a polycide gate and, e.g. a WSi2 layer 6 are laminated and formed, only the WSi2 layer is selectively etched with a means capable of setting the selection ratio of WSi2 and polysilicon higher than or equal to 1:1 and by using an etching end point detector of emission spectrum system, and patterns 6GA, 6G2 are formed. By using the WSi patterns 6G1, 6G2 as masks, phosphorus for forming a low concentration source and drain region is ion-implanted. An SiO2 film is formed, and etched and eliminated until the layer 5 surface is exposed, thereby forming side walls 9, 59. A low concentration N<-> type source region and drain regions 60S, 60D, and a high concentration N<+> type source region and drain regions 60S, 60D are formed and etched, thereby selectively eliminating the layer 5.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Actions Embodiment 1 Process sectional view of the embodiment (Fig. 1) Invention Effects [Summary] Regarding the manufacturing method of semiconductor devices, especially the manufacturing method of MOS type semiconductor devices with LDD structure, and the manufacturing method of MOS type semiconductor devices in which LDD structure and normal structure are mixed, the substrate used when forming the LDD structure This prevents deterioration of device characteristics by avoiding etching damage caused to the LD.
The purpose is to enable the creation of D-structure elements and elements that do not require an LDD structure, and to prevent β reduction in elements that do not require an LDD structure. When manufacturing a MOS type semiconductor device having an LDD structure, which has a gate electrode in which a conductor layer having a conductivity is laminated, and a low concentration source and drain region, a gate insulating film is formed on a semiconductor substrate of one conductivity type. After that, a step of forming a polysilicon layer and the conductor layer on the substrate, a step of patterning the conductor layer in the shape of a gate electrode, and a step of forming the polysilicon layer to be exposed using the conductor layer pattern as a mask. and a step of ion-implanting impurities of opposite conductivity type to become low concentration source and drain regions into the semiconductor substrate through the gate insulating film thereunder, a step of forming an insulating film sidewall on the side surface of the conductive layer pattern, and a step of forming an insulating film sidewall on the side surface of the conductive layer pattern. using the film sidewall and the conductive pattern as a mask, ion-implanting impurities of opposite conductivity type to become highly concentrated source and drain regions into the semiconductor substrate through the exposed polysilicon layer and the gate insulating film therebelow; After removing the insulating film sidewall, the exposed polysilicon layer is removed using the conductor layer pattern as a mask to form a gate electrode in which the polysilicon layer and the conductor layer are laminated. After forming a plurality of MOS type semiconductor elements with an LDD structure on one semiconductor substrate according to the configuration and the above configuration, a resist film having openings exposing some of the LDD elements is formed on the substrate, and the resist film is formed on the substrate. Through the opening in the film, impurities of the opposite conductivity type are ion-implanted at a high dose using the gate electrode in which the polysilicon layer and the conductive layer are laminated as a mask, so that the highly concentrated source and drain regions are placed in the lower region of the gate. The structure includes a step of selectively forming directly adjacent MOS transistors.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, particularly an MO of an LDD structure.
The present invention relates to a method of manufacturing an S-type semiconductor device and a method of manufacturing a MOS-type semiconductor device in which an LDD structure and a normal structure are mixed.

Semiconductor integrated circuits have become increasingly finer in recent years, and individual MO
S) Transistors with gate lengths of 1 am or less are now being manufactured. Therefore, in order to prevent deterioration of transistor characteristics and reliability due to hot carriers and short channel effects, a MOS transistor with an LDD structure in which lightly doped source and drain regions are interposed between the gate portion and the highly doped source and drain regions, respectively. In addition, in order to prevent the resistance of the ligate electrode from increasing due to the reduction in wiring width due to miniaturization and resulting in a decrease in operating speed, polysilicon with high electrical conductivity is being used. Polycide gates, in which resistance is reduced by stacking high-melting point metal silicide, are increasingly being used.

On the other hand, as integrated circuits become more multifunctional, LDD structure MOS
) transistor, and a MOS transistor with a normal structure that does not have a low concentration source or drain region and has high driving ability.
- There is also a growing demand for mixed mounting on semiconductor substrates.

[Conventional technology]

Conventionally, MO of LDD structure using polycide gate
S) When manufacturing MOSICs equipped with transistors, the method described below with reference to the drawings has been used.

Referring to FIG. 2(a), for example, a first element formation region A where a short channel converter is formed on a surface of a p-type silicon substrate by a field oxide film 2 and a p-type channel stopper 3 under the field oxide film 2.
, and the second one in which an element that is not short-channeled is formed.
Using a substrate formed separately from the element formation region aX,
First, a gate oxide film 4 is formed on the element forming region Al5lh, and then a polysilicon layer 5, which is a constituent material of a polycide gate, and a metal silicide layer, such as a tungsten silicide (WSiz) layer 6, are laminated on this substrate.

Refer to FIG. 2(b) Next, the WSi layer 6 and the polysilicon layer 5 are patterned to form polycide gate electrodes 7 and 57 in which the 15iz layer 6 is laminated on the polysilicon N5. .57 as a mask, each element forming area A1, A
At t, an n-type impurity such as phosphorus (Po) for forming low concentration source and drain regions is ion-implanted at a low dose.

108s, 1080.158S, 1580 indicate low concentration P implanted regions.

Refer to FIG. 2(C). A silicon dioxide (SiO□) film 109 for forming sidewalls is formed on the substrate by vapor phase growth.

Refer to FIG. 2(d), the entire surface of the 5i01 film 109 is etched by reactive ion etching means, and the gate electrodes 7 and 57 are etched.
Si0g sidewalls 9 and 59 are formed on the side surfaces of the substrate, respectively.

Referring to FIG. 2(e), using the gate electrodes 7 and 57 and side walls 9 and 59 as masks, an n-type impurity such as arsenic (As ) is deeply ion-implanted at a high dose, followed by heat treatment (often combined with flow treatment between PSG layers).
The previously implanted phosphorus and the currently implanted arsenic are activated to form n-type low concentration source and drain regions B.
S, 8D, 58S, 58D and n0 type high concentration source and drain regions 10S.

This is a method of forming 100.60S and 600.

[Problem to be solved by the invention]

However, according to the above conventional method, in the active ion etching process when forming the sidewalls 9 and 59, the gate oxide film 4 is also etched away at the same time, as shown in FIG. Since the substrate 1 is exposed to an etching atmosphere and is bombarded by ions, defects and damaged layers are formed in the substrate 1, and junction leakage occurs in the high concentration source and drain regions formed in these areas, resulting in deterioration of device characteristics. There is a problem with deterioration.

In addition, in the conventional method, the LDD structure is uniformly formed even in peripheral circuit elements where it is desired to increase the current amplification factor (β) rather than being short-channeled. There is also a drawback that an increase in drain resistance causes a decrease in β of such peripheral elements.

Therefore, the present invention avoids the etching damage caused to the substrate when forming the LDD structure, prevents deterioration of device characteristics, and makes it possible to differentiate between LDD structure devices and devices that do not require the LDD structure. , the purpose is to prevent β reduction in elements that do not require an LDD structure.

[Means to solve the problem]

The above problem is solved by an L having a gate electrode in which a conductor layer having etching selectivity with respect to the polysilicon is laminated on a polysilicon layer, and a low concentration source/drain region.
When manufacturing a DD structure MOS type semiconductor device, -
After forming a gate insulating film on a conductive semiconductor substrate, a step of laminating and forming a polysilicon layer and the conductor layer on the semiconductor substrate, a step of patterning the conductor layer in the shape of a gate electrode, a step of ion-implanting impurities of opposite conductivity type to become low concentration source and drain regions into the semiconductor substrate through the exposed polysilicon layer and the gate insulating film thereunder using the conductor layer pattern as a mask; A step of forming an insulating film sidewall on the side surface of the layer pattern, using the insulating film sidewall and the conductor pattern as a mask, and depositing high concentration into the semiconductor substrate through the exposed polysilicon layer and the gate insulating film below it. A process of ion-implanting impurities of opposite conductivity type to become the source and drain regions, a process of removing the insulating film sidewalls, and a process of selectively removing the exposed polysilicon layer using the conductor layer pattern as a mask. A method for manufacturing a semiconductor device according to the present invention, which includes a step of forming a gate electrode formed by laminating a silicon layer and the conductor layer, and a method for manufacturing a plurality of LDD structures on one semiconductor substrate by the above method.
After forming the OS type semiconductor element, a resist film having an opening that exposes a part of the MOS type semiconductor element of the LDD structure is formed on the semiconductor substrate, and through the opening of the resist film,
Using the gate electrode in which the polysilicon layer and the conductive layer are laminated as a mask, impurities of opposite conductivity type are ion-implanted at a high dose to form a MOS (MOS) transistor in which the high concentration source and drain regions are in direct contact with the lower region of the gate. The problem is solved by a method of manufacturing a semiconductor device according to the present invention, which includes a selective forming step.

[Function] That is, in the method of the present invention, when forming a polycide gate, only the two WSi layers are patterned using the difference in etching rate, without patterning the upper layer, for example, the WSix layer and the lower polysilicon layer. Patterned into a gate shape,
Leave the polysilicon layer covering the entire surface of the substrate.
Low concentration and high concentration impurities for forming source and drain regions are ion-implanted through this polysilicon layer.

A SiOg sidewall serving as a mask for defining the lengths of the lightly doped source and drain regions in the LDD structure is also formed on the side surface of the WSi2 pattern having the shape of the gate electrode on the polysilicon.

Therefore, when forming the Si0g sidewall, the silicon substrate surface is not exposed to the etching atmosphere or etching gas ion irradiation due to the presence of the polysilicon layer, so that damage layers and defects are prevented from being formed on the substrate surface. This is avoided and deterioration of device characteristics is prevented.

In addition, when the polycide gate is completed, Sin,
Since the polysilicon layer covering areas other than the sidewalls and gate areas is removed, impurities are again introduced at a high concentration using the gate electrode as a mask. It can be very easily converted into a MOS transistor of normal structure directly in contact with the lower gate region.

〔Example〕

The present invention will be described below with reference to process cross-sectional views shown in FIGS. 1(a) to (h), and an embodiment in which an LDD structure MOS) transistor and a normal structure MOS) transistor are both formed on one substrate. This will be explained in detail.

Refer to FIG. 1(a) By the method of the present invention, the above LDD structure and the MO of the normal structure are
S) When forming a semiconductor device equipped with a transistor, for example, a field oxide film 2 and a p-type channel stopper 3 below the field oxide film 2 are formed on one surface of a P-type silicon substrate, as in the conventional case.
As a result, a first element formation region A in which a short channel MOS transistor having an LDD structure is formed and a second element formation region A2 in which a MOS transistor having a normal structure that is not short channeled are formed are formed separately. After forming a gate oxide film 4 with a thickness of, for example, about 300 nm on the element formation region A1, by thermal oxidation using a substrate of Then, a polysilicon layer 5 having a conductivity of about 1,000 layers and a thickness of about 2,000 layers, for example, a WSi2 layer 6, which is a material for a polycide gate, are laminated.

Refer to FIG. 1(b) Next, using a resist pattern (not shown) as a mask, WS
Etching means that can maintain a selectivity ratio of iz and polysilicon of 1:1 or more, such as [carbon tetrachloride (CC14), ten oxygen (
Using an etching end point detector using an emission spectrum method, only the WSi2 layer is etched by RIB processing using an etching gas composed of A second 5i2 pattern 6Gt having a gate electrode shape is formed. Note that the polysilicon layer 5 is also etched here and becomes slightly thinner.

Next, using the -5i2 patterns 6G+ and 6cz as masks, phosphorus (P゛) for forming low concentration source and drain regions is applied to the respective element formation regions ^ and A2 through the polysilicon layer 5 and gate oxide film using accelerated energy. :
Ion implantation is performed under implantation conditions of 100 KeV and dose: 10" to 10" cm. 108s, 108
0.158S, 1580 indicates a low concentration P'' implantation region.

Refer to FIG. 1(C). Next, a film with a thickness of 1500 to 25 mm is coated on the above substrate by CVD method.
SiO□ film 109 for sidewall formation for about 00 people
form.

Refer to FIG. 1(d). Next, the SiO□ film 109 is etched away until the surface of the polysilicon layer 5 is exposed by etching the entire surface by RIB processing using, for example, methane trifluoride as an etching gas, and the WSizSi-N film is removed. Sin and sidewalls 9 and 59 are formed on the side surfaces of 6G+ and 6G2. In this etching, a polysilicon layer 5 with a thickness of approximately 1000 mm is interposed between the 5i02 film 109 and the silicon substrate 1, and the etching rate of this polysilicon is S.
Extremely small compared to iO□.

Therefore, one side of the silicon substrate is not exposed until the sidewalls 9 and 59 are completely formed.
Therefore, the surface of the silicon substrate is not directly exposed to etching gas or gas ions, so that damage layers and defects are prevented from being formed on the surface of the silicon substrate.

Referring to FIG. 1(e), the first WSi having the sidewall 9,
Second WSi with pattern 6G+ and sidewall 59, pattern 6G! As a mask, As+ is applied from 101% to 10% through the polysilicon layer 5 onto one surface of the silicon substrate.
Ion implantation is performed at a high dose of about "cm-", and predetermined heat treatment is performed to combine the implanted arsenic and the P implanted region 108S,
The phosphorus in 108D, 158S, and 158D is activated and redistributed to form low concentration source and drain regions 8S and 8D, high concentration source and drain regions 10S 5100 in the first element forming region A1, and Element formation area A
! There are n-type low concentration source and drain regions 58S inside.
, 58D, and n+ type doped source and drain regions 60S and 600 are formed, respectively.

Refer to FIG. 1(f). Next, wet etching is performed using a hydrofluoric acid solution to remove Si.
After removing 0g sidewalls 9 and 59, WSiz
The entire surface of this substrate is etched by RIB processing using a bromine (Brz) gas species that provides sufficiently high etching selectivity with respect to the gate oxide film (Si01) and the exposed polysilicon layer 5. selectively remove. Here, the LDD structure MOS transistor Tr having the polycide gate electrode 7 on the element formation region AI is changed to the LDD structure MOS transistor Tr having the polycide gate electrode 57 on the element formation region A2.
A D-structure MOS) transistor Trsz is formed.

Refer to FIG. 1 ((to)) Next, for example, some transistors used in the peripheral circuit, such as the LDD structure M on the element formation region A2 and the OS transistor TrB, are constructed in a conventional manner in which the highly doped source and drain regions are directly in contact with the lower gate region. This transistor Trs is placed on the above substrate to convert it into a transistor (MOS structure).
Resist pattern 11 having openings 12 exposing the top of z
is formed by a normal photo process, and using this resist pattern 11 and the polycide gate electrode 57 exposed in the opening 12 as a mask, a high dose of about 101th is applied through the gate oxide film 4 into the element formation region A8. A
s″″ is ion-implanted. 113S and 113D indicate high concentration As'' implanted regions.

Refer to FIG. 1 Q'1) Next, a predetermined heat treatment is performed to activate and redistribute the implanted As, thereby converting the source and drain regions of the LDD structure of this MOS transistor TrB into a normal structure in direct contact with the lower gate region. The n-type source region 13S and drain region 130 are converted into n-type source regions 13S and drain regions 130.

As described above, an LD is formed on one semiconductor substrate 1 having P-type.
An n-channel MOS transistor Tr having a D structure and an n-channel MOS transistor Tr having a normal structure.
A semiconductor device having z is formed.

As explained in the examples above, according to the method of the present invention,
When forming sidewalls on the sides of the gate electrode to form an LDD structure, the semiconductor substrate surface is not exposed to etching gas or etching gas ions, so no damage layer or defects are formed on the silicon substrate surface. This prevents deterioration of device characteristics due to junction leakage, etc., and improves the reliability of a semiconductor device configured using an LDD structure MOS transistor.

Further, as shown in the same embodiment, according to the method of the present invention, it is extremely easy to convert a plurality of LDD structure MOS transistors formed on one semiconductor substrate into a normal structure MOSI transistor.

Note that in the method of the present invention, the metal silicide forming the polycide gate is not limited to the above-mentioned WSiz. Further, the conductor layer laminated on the polysilicon layer is not limited to metal silicide, but may be a conductor having etching selectivity with respect to polysilicon, such as a high melting point metal.

〔Effect of the invention〕

As explained above, according to the present invention, the MO of the LD'D structure
S) The reliability of semiconductor ICs configured using transistors is improved.

Further, since MOSI transistors having an LDD structure and a normal structure can be easily mounted together on one substrate, the performance of a multi-functional semiconductor IC can be improved.

[Brief explanation of the drawing]

FIGS. 1(a) to 1) are cross-sectional views of an embodiment of the method of the present invention, and FIGS. 2(a) to 2(e) are cross-sectional views of a conventional method. In the figure, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is a p-type channel stopper, 4 is a gate oxide film, 5 is a polysilicon layer, 6 is a -5iz layer, 5G+ and 6Gz are -5i2 patterns, 7.57 is a polycide gate electrode, 8S, 58S are n-type low concentration source regions, 8D, 58
D is an n-type low concentration drain region, 9.59 is a 5ift sidewall, 10S, 60S is an n0 type high concentration source region, 100
, 600 is an n1 type high concentration drain region, 11 is a resist pattern, 12 is an opening, 13S is an n + type source region, 130 is an n0 type drain region, 108S, 1080.158s, 1580 is a low concentration P
``Implanted regions, 113S and 1130 are high-concentration As'' implanted regions, A is an element formation region, Trl and Tr are LDD structure MOSI-transistors,
Tr indicates a transistor (usually structured as a MOS transistor). An embodiment of the square block of the present invention] Eave plan (Part 1)! 1!1 Figure (2)

Claims (2)

[Claims] (1) LDD having a gate electrode in which a conductor layer having etching selectivity with the polysilicon layer is laminated on a polysilicon layer, and a low concentration source and drain region.
When manufacturing a MOS type semiconductor device having a structure, a step of forming a gate insulating film on a semiconductor substrate of one conductivity type and then laminating a polysilicon layer and the conductor layer on the semiconductor substrate; a step of patterning the conductor layer in the shape of a gate electrode, using the conductor layer pattern as a mask, forming a low concentration source and drain region in the semiconductor substrate through the exposed polysilicon layer and the gate insulating film therebelow; a step of ion-implanting conductive impurities; a step of forming an insulating film sidewall on the side surface of the conductive layer pattern; using the insulating film sidewall and the conductive pattern as a mask, the exposed polysilicon layer and its lower part; a step of ion-implanting impurities of opposite conductivity type to become highly concentrated source and drain regions into the semiconductor substrate through the gate insulating film of the semiconductor substrate; a step of removing sidewalls of the insulating film; and a step of removing the sidewalls of the insulating film; 1. A method of manufacturing a semiconductor device, comprising the step of selectively removing a polysilicon layer to form a gate electrode formed by stacking the polysilicon layer and the conductor layer. (2) After forming a plurality of MOS semiconductor elements with an LDD structure on one semiconductor substrate by the method according to claim 1, openings on the semiconductor substrate expose some of the MOS semiconductor elements with an LDD structure. A resist film having a conductivity type is formed, and impurities of the opposite conductivity type are ion-implanted at a high dose through the openings in the resist film, using the gate electrode in which the polysilicon layer and the conductive layer are laminated as a mask. 1. A method of manufacturing a semiconductor device, comprising the step of selectively forming a MOS transistor whose doped source and drain regions are in direct contact with a lower gate region.