JPH03134579A - Multivalue calculation model and formation of test pattern of logical circuit using same - Google Patents

Abstract

PURPOSE:To efficiently form a test pattern generating no back track by constituting a multivalue calculation model wherein specific functions are allowed to respectively correspond to the AND element, OR element and NOT element constituting a logical circuit. CONSTITUTION:When at least one input value increases, the output values of both of an AND element and an OR element are increased and a function making the difference between the output values to two input series different only in one input smaller (larger in the OR element) than the difference between the output values to two input series increased in the input value of the input equal in the input value among said two input series is allowed to correspond and, with respect to an NOT element, a multivalue calculation model wherein a function reducing the output value thereof when the input value increases is allowed to correspond is constituted. Then, a system composed of the real number slightly larger than 0 and a system composed of the real number slightly smaller than 1 and inputted to the respective models of logic having trouble constituted with respect to a logic circuit and trouble desired to be detected and an input system is altered so as to make the difference between the output values large to form a test pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for automatically generating test patterns for detecting manufacturing failures in logic circuits.

[Conventional technology]

In the past, many methods have been proposed for generating test patterns for logic circuits, but in particular, a method for generating test patterns without backtracking is described in the Proceedings of the International Conference on Computer Design '87. Discussed on pages 48-51.

This method will be explained using FIGS. 2, 3, and 4. FIG. 2 is a flowchart of the conventional method for generating a test pattern for detecting a fault given a logic circuit and a fault to be detected. First, in step 201, an arbitrary test vector is selected. In step 202, an operation called threshold simulation is performed on all adjacent vectors of the selected test vector. Threshold simulation means that if each element included in a logic circuit is an AND element, the value obtained by applying a function called the threshold function shown in Figure 3 to the average of the input values, and if each element included in the logic circuit is an OR element, the value of the input value is calculated. This is a simulation in which the output value is the value obtained by applying the threshold numerical value shown in FIG. 4 to the average. The above simulation is performed on two circuits, a normal circuit and a failed circuit, and the reciprocal of the difference in output values is calculated as the cost. 203,20
In step 4, it is determined whether the vector with the minimum cost is a test pattern that detects the given fault, and if the test pattern is the test pattern, the process ends; if it is not the test pattern, the vector with the minimum cost is used as the next trial vector and the above operation is repeated. This is a method for finding test patterns.

An application example of the conventional method will be explained using FIG. 7.

FIG. 7 shows a circuit consisting of two AND elements.

Now, a test pattern for detecting a failure in which the signal at the first input terminal of the AND element 71 of this circuit is always fixed at 1 will be determined using a conventional method. First, as the initial vector (
0, O, O), the adjacent vector is (1, O, O
), (0,1,0) (0,0,1). When calculating the cost for these four vectors, each
324° 324, ω, 19, and since none of the vectors is a test pattern, the next trial vector is set to the minimum cost (0, 0, 1) and the adjacent vector (1, 0, 1
), (0, 1, 1), and (0, O, O).

Among these, the vector (1, 0, 1) with the minimum cost is a test pattern, so the process ends.

[Problem to be solved by the invention]

The above conventional method is strongly influenced by changes in test vectors in terms of controlling signal values different from those at the time of failure at the failure point, but is not so strongly influenced by test vectors in terms of propagating failure information to the output. , Therefore, test pattern generation may fail. For example, a test pattern for detecting a fault in which the signal at the first input terminal of the AND element 72 of the circuit shown in FIG. .

Initial vector (0, O, O) and its adjacent vector/L
/ (0,1,O), (0,0,1)# (0,
The cost of 0°1) is 17.0%, respectively, as shown in Figure 8.
86. Co, 17.89, 17.89.

From this, the cost of the initial vector is the minimum (actually (0,
1, O), (0, 0, 1)), the next trial vector does not change and the desired test pattern (0, 1, 1)
) is not reached.

[Means to solve the problem]

To solve the above issues.

For a logic circuit consisting of an AND element, an OR element, a NOT element, and a logic element that can be configured by combining these elements, the AND element increases its output value when at least one input value increases, And, the difference in output values for two input series that differ in only one input is made smaller than the difference in output values for two input series in which the input values of the inputs with the same input value are increased, and OR is performed. For an element, when at least one input value increases, its output value increases, and the difference between the output values for two input series that differ only in one input is the input value of the input with the same input value among the two input series. A function is associated with the NOT element that makes the output value larger than the difference between the output values for the increased two input series, and a function that decreases the output value when the input value increases is associated with the NOT element. For the combined logic elements, a multi-value calculation model is created that corresponds to a function that is a combination of functions corresponding to the logic elements that constitute the logic elements, and for the above logic circuit and the fault to be detected, a fault-free logic and Configure each for logic with a fault, input a series of real numbers slightly larger than 0 and real numbers slightly smaller than 1 to the above two calculation models, and the difference between the output values of the two calculation models becomes large. A test pattern can be generated by changing the input series, or a series consisting of 0 and 1 can be input into the two calculation models mentioned above, and the difference between the output values of the two calculation models can be increased. A test pattern can be generated by changing the input sequence, or in the multivalue calculation model described above, a function corresponding to the AND element can be given as a product of input values, and O
A multi-value calculation model in which the function corresponding to the R element is given as the value obtained by subtracting the multiplied value of 1-input value for each input from 1, and the function corresponding to the NOT element is given as 1-input value. are constructed for the above logic circuit and the fault to be detected, respectively for the logic without a fault and the logic with a fault, and the series consisting of real numbers slightly larger than O and real numbers slightly smaller than 1 is calculated using the above two calculations. A test pattern may be generated by inputting data into a model and changing the input series so that the difference between the output values of the two calculation models increases.

In the above multi-value calculation model, the function corresponding to the AND element is a downwardly convex function passing through (0, 0) and (1, 1) whose domain is the average value of the input values, and the function corresponding to the OR element is A multivalued calculation in which the function corresponding to the NOT element is given as a 1-input value, where the function is an upwardly convex function passing through (0, 0) and (1, 1) whose domain is the average value of the input values. model,
For the above logic circuit and the fault to be detected, construct logic without a fault and logic with a fault, input a series of 0 and 1 to the above two calculation models, and
A test pattern is generated by changing the input series so that the difference between the output values of two calculation models becomes large.

[Effect]

As mentioned above, for an AND element, when at least one input value increases, its output value increases, and the difference between the output values for one input series that differs only in one input is the difference between the input values of the two input series. Increased input value for equal inputs by 2
Correspond to a function that makes the difference between the output value and the input series smaller than the difference.

For an OR element, when at least one input value increases, its output value increases, and only one input differs.
By associating a function such that the difference in the output value for the input series is larger than the difference in the output value for the two input series in which the input value of the input with the same input value is increased among the two input series, the input The value increases and OR
In the element, if the observability of the failure signal is improved by reducing the input value, this will immediately be reflected in an improvement in cost, so the above problem is solved. Also, as shown above, the function corresponding to the AND element is given by the product of the input values, and the function corresponding to the OR element is given for each input by 1 - the value obtained by multiplying the input value by 1. give,
The function corresponding to the NOT element can be given as 1-input value, and the function corresponding to the AND element can be given as a domain that passes through (0.0) and (1, 1). The function corresponding to the OR element is an upwardly convex relationship passing through (0.0) and (1, 1) whose domain is the average value of the input values, and the function corresponding to the NOT element is 1. - Even if the input value is given as an input value, the input value increases in the AND element, and the input value decreases in the OR element, and if the WA metric of the fault signal improves, this will immediately reflect in an improvement in cost. Therefore, the above problem is solved.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a schematic flowchart of the present invention, and when compared with the flowchart of the conventional method, 102 simulation methods are different. This simulation, named approximate value simulation, uses approximate values (here 0.0) for O and 1 as test vectors input to the circuit model.
1 and 0.99) is input. Since a logic element can only handle two values, O and 1, operations for each logic element are defined as follows in order to handle real values. For an AND element, the output value is the product of input values. For the OR element, the product of the difference between 1 and each input value is 1
The difference between the two is the output value.

For a NOT element, the difference between 1 and the input value is set as the output value. Regarding fault signal lines, set the value of the signal line that always degenerates to 0 to 0.0, and the value of the signal line that always degenerates to 1 to 1.0.
Make it. A circuit model with the above calculation rules is constructed for a normal circuit and a faulty circuit, and the output values of the normal circuit and faulty circuit are calculated with respect to the trial vector and its adjacent vectors.

Note that the cost is the reciprocal of the difference between the output values of the normal circuit and the faulty circuit, and the test pattern is derived by changing the trial vector in a direction that reduces the cost.

Using the second method, a test pattern for detecting a failure in which the signal at the first input terminal of the AND element of the circuit shown in FIG. 7 always degenerates to 1 is determined. As the initial vector, (0, O, O) is used as in the previous example.

The initial vector (0, O, O) and its adjacent vector (
1,O,O), (0,1,O), (0,0゜1
), each cost is 1 as shown in Figure 9.
0101, 1000000, 102, 102. As a result, the vector (0, 1, O) or (0, 0° 1) with the minimum cost is selected as the next trial vector, and the cost is calculated together with its adjacent vectors. As a result, the adjacent vector (0, 1, 1) can be derived as a test pattern.

Further, other embodiments of the present invention are shown in FIGS. 2, 5 and 6.
This will be explained using figures. FIG. 2 is a schematic flowchart of the conventional method, and the threshold functions used in the threshold simulation in 202 are shown in FIGS. 3 and 4, those related to AND elements are shown in FIG. 5, and those related to OR elements are shown in FIG. is changed to that shown in FIG. This threshold simulation reduces the cost immediately when failure information propagates more easily, so the cost of (0,1,O) or (0,0,1) is lower than the cost of (0,O,O). is smaller, and the desired test pattern (0, 1, l
) can be derived.

〔Effect of the invention〕

According to the present invention, increases and decreases in cost due to failure information propagation become noticeable, and test patterns can be efficiently generated without backtracking. In particular, not only is the effort required to generate test patterns reduced as in the example shown in Figure 7, but it has also become possible to obtain test patterns for failures for which test patterns could not be generated. For example, when comparing the performance of the method shown in Example 1 and the conventional method, it was found that the method shown in Example 1 was able to reduce the number of undetected failures by half in the conventional method. If test patterns for undetected faults are created manually, this method can reduce the number of manual steps by half.

[Brief explanation of the drawing]

Fig. 1 is a schematic flow diagram of an embodiment of the present invention, Fig. 2 is a schematic flow diagram of the conventional method, Fig. 3 is the threshold function of the AND element used in the threshold simulation of the conventional method, and Fig. 4 is the threshold function of the OR element used in the threshold simulation of the conventional method. FIG. 5 shows the threshold numerical value of the AND element used in the threshold simulation of another embodiment of the present invention, and FIG. 6 shows the O used in the threshold simulation of another embodiment of the present invention.
Threshold function of R element, FIG. 7 is a circuit diagram explaining the problems of the conventional method, FIG. 8 is a simulation result of the conventional method for FIG. 7, and FIG. 9 is an example of the present invention for FIG. 7. It is a figure showing the simulation result in . 701. 702, 703 - External input terminal, 704 Fig. 1 Fig. 2 Fig. 2 Average of input values

Claims (1)

[Claims] 1. In a multi-value calculation model configured for a logic circuit consisting of an AND element, an OR element, a NOT element, or a logic element that can be configured by combining these elements, for the AND element: The output value of the element is increased when at least one input value increases, and the difference between the output values for two input series that differ in only one input increases the input value of only the inputs with the same input value among the two input series. Correlate a function that makes the difference between the output value and the input series smaller than the difference, and perform OR
For an element, when at least one input value increases, the output value of the element increases, and only one input differs.
Correspond to a function such that the difference in output value for the input series is larger than the difference in output value for the two input series in which the input value of the input with the same input value is increased among the two input series, and NO
A function that decreases the output value of the element when the input value increases is associated with the T element, and a function that decreases the output value of the element when the input value increases, and a function that is a combination of the above elements is associated with the logic elements that constitute the logic element. A multivalue calculation model characterized by a combination of functions that correspond to each other. 2. In the multi-value calculation model according to claim 1, the function corresponding to the AND element is given as a product of input values, and the function corresponding to the OR element is multiplied by calculating (1-input value) for each input. A multi-value calculation model characterized in that a value subtracted from 1 is given as a value, and a function corresponding to a NOT element is given as (1-input value). 3. In the multi-value calculation model according to claim 1, the function corresponding to the AND element has an average value of input values as a domain (0
, 0) and (1, 1), and OR
The function corresponding to the element is defined by the average value of the input values as the domain (
0, 0) and (1, 1), and N
A multi-value calculation model characterized in that a function corresponding to an OT element is given as (1-input value). 4. In a method of generating a test pattern for detecting a fault in a logic circuit, for a given logic circuit and a detected fault, the calculation model according to claim 2 is applied to logic without a fault and logic with a fault, respectively. , input a series of real numbers slightly larger than 0 and real numbers slightly smaller than 1 to the two calculation models, and change the input series so that the difference between the output values of the two calculation models becomes large. 1. A method for generating a test pattern for a logic circuit, characterized in that a test pattern is generated by: 5. In a method of generating a test pattern for detecting a fault in a logic circuit, for a given logic circuit and a fault to be detected, the calculation model according to claim 3 is applied to logic without a fault and logic with a fault, respectively. and 0 and 1
Input the series consisting of into the two calculation models, and
A method for generating a test pattern for a logic circuit, characterized in that a test pattern is generated by changing an input series so that the difference between output values of two calculation models increases. In this method, in addition to 6, 0, and 1, logical values are provided to interpolate between them, and a test pattern for a logic circuit is obtained based on multi-value simulation. The device and the NOR element are characterized in that if any of the input terminals approaches 0, the fact that fault information appearing at other input terminals becomes easier to propagate is reflected in the output value of the element. A method for generating test patterns for logic circuits. 7. A test in which the given input sequence detects a failure by giving an input sequence consisting of 0s and 1s to a logic circuit, and finding a pattern that detects a failure by comparing the output sequence during normal and failure times. The index of how close the input sequence is to the pattern is determined by corresponding to real numbers greater than 0 and less than 0.5 and real numbers greater than 0.5 and less than 1, respectively, and logical product, logical sum, and negation operations. The test pattern is obtained by making the evaluation values of the output series during normal and failure times performed as the product of input values, 1-{product of (1-input value)}, and 1-input value, respectively. A method for generating test patterns for logic circuits. 8. Generation of a test pattern for a logic circuit in which the evaluation value of the output series during normal operation and at the time of failure according to claim 7 is the maximum value of the difference between corresponding elements of the output series during normal operation and the output series at the time of failure. Method. 9. Generation of a test pattern for a logic circuit in which the evaluation value of the output series at normal times and at the time of failure according to claim 7 is the sum of squares of the differences between corresponding elements of the output series at normal times and the output series at the time of failure. Method. 10. A method for generating a test pattern for a logic circuit according to claim 7, wherein the evaluation value of the output series during normal operation and during failure is the sum of the differences between corresponding elements of the output sequence during normal operation and the output sequence during failure. .