JPH0784817A - Method for generating test pattern of combination circuit - Google Patents

Abstract

PURPOSE:To enable fast test pattern generation by utilizing logical value information on an input which is less in the probability of back tracking from test pattern information that is already generated at the time of logical value assignment. CONSTITUTION:Circuit data 1 on a combination circuit to be processed and fault data 2 on the combination circuit are inputted and a test pattern generating process is performed based the fault data 2, and test pattern data 3 are outputted and edited, and the test pattern edited data 4 are outputted. The test pattern edited data 4 are inputted, a test generating process which utilizes a test pattern that is already generated is performed based on the circuit data 1 on the combination circuit, fault data 2 on the combination circuit, and test pattern edited data 4, and test pattern data 5 are outputted. Namely, the test pattern information is utilized, the input pin of the combination circuit to which a logical value 0 or 1 is assigned with high probability is recognized, and a logical value which is assigned to the recognized input pin with high probability is assigned.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault diagnosis of a combinational circuit, and more particularly to a test pattern generation method suitable for fault diagnosis of a combinational circuit.

[0002]

2. Description of the Related Art In recent years, as the scale of logic circuits has increased, the mainstream method of generating fault diagnostic data for logic circuits is from the method of directly generating fault diagnostic data for the entire logic circuit to the scan design method. By adopting this method, the logic circuit is divided into a plurality of combinational circuits, partial failure diagnosis data is generated for each combinational circuit, and these partial failure diagnosis data are edited to generate failure diagnosis data of the entire logic circuit. The process is moving. With the shift of the method of generating the failure diagnosis data, the logic circuit to be the object of the failure diagnosis is also changed from the sequential circuit to the combinational circuit. Therefore, a method of generating fault diagnosis data for a combinational circuit, particularly a test pattern generation method and a fault simulation method, which are the core of the method, has become an important issue. As test pattern generation methods for combinational circuits, Boolean differentiation method, D
Algorithm, PODEM (Path Oriented DEcision M
aking), FAN (FANout oriented test generation)
Etc. have been proposed.

[0003]

However, as the circuit scale increases, the number of failures that make it difficult to generate a test pattern increases. As a result, in the test pattern generating method as described above, the processing time increases. It can't be ignored.

To generate a test pattern for a combinational circuit, a logical value is assigned to a signal line in the combinational circuit, and if the assigned logical value does not satisfy the test pattern condition,
The logical value allocation is redone (called backtracking). An increase in the number of backtracks causes an increase in the test pattern generation time. Therefore, in order to shorten the test pattern generation time, it is necessary to generate the test pattern without backtracking as much as possible.

Therefore, an object of the present invention is to provide a test pattern generation method which can reduce the number of backtracks and generate a test pattern at a higher speed.

[0006]

In order to achieve the above object, in the test pattern generation method of the present invention, when a test pattern of an undetected fault in a combinational circuit is generated,
Using the test pattern information that has already been generated for the combinational circuit, the input pin of the combinational circuit with a high probability of being assigned a logical value 0 or 1 is recognized, and the probability of being assigned to the recognized input pin is high. The recognized logical value is assigned.

[0007]

Among the input pins of the combinational circuit for which the test pattern is to be generated, it is recognized that the probability of being assigned is high to the input pin having a high probability of being assigned the logical value 0 or 1 from the already generated test pattern information. By assigning such a logical value, the probability that the logical value assigned to the input pin satisfies the condition of the test pattern is increased, and the test pattern can be generated stochastically with a smaller number of backtracks.

[0008]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a flow chart of a test pattern generation process according to an embodiment of the present invention. Step 1
At 00, the circuit data 1 of the combinational circuit to be processed and the failure data 2 of the combinational circuit are input. Next, in step 200, a test pattern generation process is performed based on the circuit data 1 of the combinational circuit and the failure data 2 of the combinational circuit, and the test pattern data 3 is output. The test pattern generation method used here may be any method such as a random method or an algorithmic method. Further, when the number of generated test patterns reaches a predetermined number of abort test patterns, the test pattern generation process is aborted. In step 300, the test pattern data 3 generated in step 200 is input and edited, and the test pattern edit data 4 is output.
Step 400 is the core step of the present invention,
The test pattern edit data 4 is input, and based on the circuit data 1 of the combination circuit, the failure data 2 of the combination circuit, and the test pattern edit data 4, the test pattern generation process using the already generated test pattern is performed, and the test is performed. The pattern data 5 is output. The test pattern generation method used in step 400 may be any method as long as it uses backtracking and backtracking.

FIG. 2 shows the method of editing the test pattern data in step 300 of FIG. Reference numeral 201 denotes a combinational circuit to be processed, which is I1, I2, ...
., In represent input pins, O1, O2, ..., Om
Represents an output pin. The test pattern data 202 is stored in the step 200 of FIG.
Represents the logical value of the input pin in the test pattern generated by the test pattern generation process (the number of cutoff test patterns t = 100).

The method of editing the test pattern data is as follows. First, from the test pattern 202, for each input pin, the number K0 of test patterns whose logical value assigned to the input pin is 0 and the logical value assigned to the input pin among the generated test patterns. Is 1
Then, the number K1 of test patterns is calculated. Next, the deviation degree H representing the degree of deviation of the logical value of each input pin is calculated by the calculation formula 204. In calculation formula 204, logical value 0
The deviation value H is defined as the absolute value of the difference between the number K0 of test patterns assigned to and the number t of cut-off test patterns divided by two. The deviation degree H is 0 when K0 and K1 of the input pin are equal, and increases as there is a difference between them. The test pattern edit data 203 includes K0, K1, and H for each input pin from the test pattern data 202.
Is obtained by seeking.

FIG. 3 is a flow chart of backward tracking and backtracking in the test pattern generation process using the generated test pattern in step 400 of FIG. In step 301, a contradiction flag indicating whether or not a contradiction has occurred due to an implication operation is initialized. The contradiction flag is
And 1 if the fault signal is not propagated to the output pin but the fault signal disappears, 0 otherwise. In step 302, based on the test pattern edit data 4, for input pins having a bias degree H larger than a preset value, a logical value having a larger number of times assigned in order from the bias degree H is assigned. Then, in step 303, an implication operation is performed. In step 304, if the contradiction flag is 0, the process branches to step 305, and if the contradiction flag is 1, the process branches to step 308. In step 305, if an unjustified signal line exists or a failure signal has not propagated to the output pin, the process branches to step 306. If not, it is determined that a test pattern has been generated, and processing is performed. To finish. If there is an unjustified signal line, or if a fault signal has not propagated to the output pin, then in step 306 backtracking is performed to assign a logical value to the input pin. Then, an implication operation is performed in step 307, and the process returns to step 304.

On the other hand, if the contradiction flag is not 0 in step 304, backtracking of logical value assignment of input pins is performed in step 308. Then, in step 309, it is determined whether or not the test pattern exists in the backtrack in step 308. If it is determined that the test pattern does not exist, the process ends.
If it is determined in step 309 that the test pattern is present, the process branches to step 310, the implication operation is performed, and the process returns to step 304.

FIG. 4 shows an example of logical value assignment in a test pattern generation process using a generated test pattern. In FIG. 4, 1a, 2a, 3a, 5a, 6a are OR gates, 4a are AND gates, and 7a, 8a, 9
a, 10a are input pins, 11a are output pins, 12a
Indicates a fault signal line (0 stuck-at fault (s-a-0)).

FIG. 4A shows a state in which the definite logical value is assigned (the logical value 1 is assigned to the input pin 9a) and the implication operation is performed. Here, D is the logical value of the normal circuit is 1
Indicates a fault signal in which the logic value of the fault circuit is 0. Next, FIG. 4B shows the input pin 7 having a large deviation H.
A state is shown in which a logical value 0 is assigned to a, an implication operation is performed, and the input pin 7a is stacked on the backtrack stack. FIG. 4 (c) shows a state in which backward tracking is performed to propagate the fault signal D to the output of the OR gate 1a, a logical value 0 is assigned to the input pin 8a, an implication operation is performed, and the input pin 8a is stacked on the stack. Is shown. FIG. 4D shows a state in which a backward trace is performed to propagate the fault signal D to the output of the OR gate 3a, a logical value 0 is assigned to the input pin 10a, an implication operation is performed, and the input pin 10a is stacked on the stack. Is shown. In this state, the failure signal D has propagated to the output pin 11a, and the test pattern generation ends without backtracking.

FIG. 5 shows an example of logical value allocation in the case where the test pattern generation processing is performed for the same circuit and the same fault as in FIG. 4 without using the generated test pattern. In FIG. 5, 1b, 2b, 3b, 5b,
6b is an OR gate, 4b is an AND gate, and 7b, 8
b, 9b, 10b are input pins, 11b are output pins,
Reference numerals 12b denote failure signal lines (0 stuck-at failure (s-a-0)).

FIG. 5A shows a state in which the definite logical value is assigned (the logical value 1 is assigned to the input pin 9b) and the implication operation is performed. FIG. 5 (b) shows that the back trace is performed to propagate the fault signal D to the output of the OR gate 1b, a logical value 0 is assigned to the input pin 8b, the implication operation is performed, and then the stack is input to the backtrack stack. The state where the pins 8b are stacked is shown. FIG. 5C shows a state in which the backward trace is performed to propagate the fault signal D to the output of the OR gate 3b, the logical value 0 is assigned to the input pin 10b, the implication operation is performed, and the input pin 10b is stacked on the stack. Is shown. Figure 5
(D) traces back to propagate the fault signal D to the output of the AND gate 4b and outputs a logical value of 1 to the input pin 7b.
Is assigned, the implication operation is performed, and the input pin 7b is stacked on the stack. In this state, the failure signal D has disappeared even though the failure signal D has not propagated to the output pin 11b. Therefore, backtracking is required.
Therefore, the input pin 7b stacked at the top of the stack
Inverts the logical value of. FIG. 5E shows a state in which the implication operation is performed after inverting the logical value of the input pin 7b. This time, the failure signal D is propagated to the output pin 11b,
The test pattern generation ends.

As described above, in the above-described example, according to the test pattern generation processing using the generated test pattern, the test pattern can be generated without backtracking, and the backtracking is required once. It is possible to speed up the generation of the test pattern as compared with the test pattern generation processing that does not use the test pattern.

[0019]

According to the present invention, in the fault diagnosis of the combinational circuit, the logic value information of the input pin which is unlikely to cause the backtrack is acquired from the generated test pattern information, and the information is assigned to the logic value. It is possible to generate a test pattern at high speed by using

[Brief description of drawings]

FIG. 1 is a flowchart of a test pattern generation process according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a method of editing test pattern data in step 300 of FIG.

FIG. 3 is a flowchart of backtracking and backtracking in a test pattern generation process using the generated test pattern in step 400 of FIG.

FIG. 4 is an explanatory diagram showing an example of logical value allocation in a test pattern generation process using a generated test pattern.

FIG. 5 is an explanatory diagram showing an example of logical value assignment when a test pattern generation process is performed without using a generated test pattern.

[Explanation of symbols]

 1 to 5: input / output data of test pattern generation processing, 100 to 400: test pattern generation processing steps.

Claims (1)

[Claims] 1. When diagnosing a failure of a combinational circuit, when a test pattern of an undetected failure in the combinational circuit is generated, logical value 0 or 1 is assigned by using the generated test pattern information of the combinational circuit. A method for generating a test pattern for a combinational circuit, which recognizes an input pin of the combinational circuit with a high probability of being assigned and allocates the logical value to the input pin.