JPH03132853A - Crt control circuit - Google Patents

Abstract

PURPOSE:To minimize the wait of a bus master and to ensure the highly efficient application of a bus by setting the generation timing of a bus evacuation request signal at the processing speed of each bus master of a CPU, a graphic display controller, etc., and sending individually the request signal to each bus master. CONSTITUTION:A counter means 11 counts the output timings of a bus request signal. The bus request generation timing setting means 12 - 14 set the generation timings of request signals set in accordance with the bus masters 41, 51 and 61 respectively. Then the comparison means 15 - 17 compares the output signals of the means 11 with the corresponding output signals of the means 12 - 14 respectively. The bus request means 18 - 20 apply the bus request signals to the bus masters and a data transfer means based on the coincidence result obtained via the corresponding comparison means. Thus the wait of the bus mater is minimized and the bus availability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a CRT control circuit of a computer device. In particular, 2-port DRAM (dual port D
This invention relates to a CRT control circuit using RAM.

〔overview〕

In the CRT control circuit of the present invention, the timing of generation of the bus surrender request signal is adjusted to the processing speed of each bus master such as the CPU and graphic display controller, and the request signal is sent to each bus master individually, thereby minimizing the wait of the bus master. This is to ensure efficient bus use by minimizing traffic congestion.

[Conventional technology]

Conventionally, a CRT control circuit uses a graphics display controller (hereinafter referred to as GD) prior to a data transfer cycle.
It's called C. ) and a bus surrender request signal to the CPU, etc. (
Hereinafter, this signal will be referred to as a bus request signal. ), and when the bus request signal becomes valid, the CPU, GDC, etc. receive the bus request signal and surrender the bus by the time the data transfer cycle starts.

[Problem that the invention seeks to solve]

However, in such a conventional CRT control circuit, the GDC
Since a common bus request signal was sent to each bus master such as the CPU and the CPU, it was necessary to send a bus request signal tailored to the bus master with the slowest processing speed. For this reason, bus masters with high processing speeds have the disadvantage of being burdened with extra wait, making it impossible to use the bus efficiently.

The present invention solves the above-mentioned drawbacks, and enables efficient bus use by minimizing the weight of the bus master.
The purpose of this invention is to provide an RT control circuit.

Means for Solving Problem C] The present invention provides a bus requesting means for giving a bus surrender request signal to a plurality of bus masters during a data transfer cycle, and a data transfer cycle to a 2-port DRAM based on the request signal of the bus requesting means. In the CRT control circuit, a CRT control circuit is provided with a data transfer means for supplying a time control signal; A bus request generation timing setting means is set according to the processing speed, and the output signal of the counting means connected to each bus request generation timing setting means is compared with the output signal of the corresponding bus request generation timing setting means. comparing means, and the bus requesting means includes means connected to each of the comparing means and outputting the request signal based on the matching result of the corresponding comparing means.

[Effect]

The counting means counts the output timing of the request signal. Each bus request generation timing setting means sets the generation timing of the request signal to the corresponding comparison means in accordance with the processing speed of the corresponding bus master. Each comparing means compares the set generation timing with the count value of the counting means. Each bus request means provides a request signal to the corresponding bus master and data transfer means based on the match result of the corresponding comparison means. By the above operation, the wait of the bus master can be minimized and the bus can be used efficiently.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a CRT control circuit according to an embodiment of the present invention. In FIG. 1, the CRT control circuit sends a bus surrender request signal to a CPU 40 during a data transfer cycle.
The bus request means 18 to 20 which are applied to the bus master 4L 51.61 of the GDC 50 and the refresh control device 60, and the bus request signal of the bus request means 2 port D
A CRT control circuit 10 comprising a data transfer means 21 that provides a control signal during a data transfer cycle to RAM M2O.
, a counting means 11 for counting the output timing of the bus request signal, and each bus master 41, 51 .
bus request generation timing setting means 12, which is provided corresponding to the bus master 41, 61, and sets the generation timing of the request signal in accordance with the processing speed of the bus master 41, 51, 61;
~14, and each bus request generation timing setting means 12~1
The bus requesting means 18 to 20 are connected to the respective comparing means 15 to 17 for comparing the output signal of the counting means 11 and the corresponding output signal of the bus request generation timing setting means 12 to 14. 15 to 17, respectively, and includes means for outputting the bus request signal based on the matching result of the corresponding comparison means.

The operation of the CRT control circuit having such a configuration will be explained. FIG. 2 is a block diagram of an electronic computer device including a CRT control circuit of the present invention. Figure 3 shows C and R of the present invention.
FIG. 3 is a diagram showing the operation of the T control circuit.

In FIGS. 1 to 3, bus request generation timing setting means 12 to 14 set the generation timing of the bus request signal to C.
PU40, GDC50 and refresh control device 60
The bus masters 41, 51, and 61 can be individually set, and the counting means 11 counts the timing of the bus request signal.

Comparing means 15-17 compare the outputs of bus request generation timing setting means 12-14 and counting means 11, and when they match, output the matching results to bus requesting means 18-20. The bus requesting means 18 to 20 that received this request the CP
A bus request signal is output to each bus master 4L 5L 61 of U40, GDC50, and refresh control device 60, and also to data transfer means 21.

Upon receiving this, the data transfer means 21 outputs a control signal for the 2-port DRAM 30 during the data transfer cycle.

FIG. 3 shows one cycle of operation, in which the counting means 11, bus request generation timing setting means 12-14, comparing means 15-17 and bus requesting means 18-20 operate as described above when the power is turned on. Repeat.

〔Effect of the invention〕

As explained above, the present invention has the excellent effect of minimizing the weight of the bus master and efficiently utilizing the bus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a CRT control circuit according to an embodiment of the present invention. FIG. 2 is a block diagram of an electronic computer device including a CRT control circuit of the present invention. FIG. 3 is a flowchart showing the operation of the CRT control circuit of the present invention. 10...CRT control circuit, 11...counting means,
12-14...Bus request generation timing setting means, 1
5-17... Comparison means, 18-20... Bus requesting means, 21... Data transfer means, 30... 2 port D
RAM, 40...CPU, 41.51.61...Bus master, 50...GDC, 60...Refresh control device.

Claims (1)

[Scope of Claims] 1. Bus request means for providing a bus surrender request signal during a data transfer cycle to a plurality of bus masters, and providing a control signal during a data transfer cycle to the 2-port DRAM based on the request signal of the bus request means. A CRT control circuit comprising a data transfer means, a count means for counting the output timing of the request signal, and a count means provided corresponding to each of the bus masters to adjust the generation timing of the request signal to the processing speed of the bus master. bus request generation timing setting means for setting, and comparison means connected to each of the bus request generation timing setting means for comparing the output signal of the counting means and the output signal of the corresponding bus request generation timing setting means, A CRT control circuit characterized in that the bus requesting means includes means connected to each of the comparing means and outputting the request signal based on a matching result of the corresponding comparing means.