JPH03131062A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the existence of a parasitic bipolar transistor, and to obviate a latch-up by covering all regions of the undersides and side faces of a bipolar transistor region, an N-type MOSFET re gion and a P-type MOSFET region with insulating films in a semiconductor device composed of Bi-CMOS. CONSTITUTION:A thermal oxide SiO2 film 12 and a single crystal Si thin-film 14, an underside of which has an N<+> diffusion layer 13, are formed onto an Si substrate 11. Si is removed selectively in the element isolation regions of the Si thin-film 14, trenches are shaped, and the trenches are buried with an insulating film 15. The trenches are formed up to SiO2 12, and all regions of undersides, side faces and top faces are also surrounded by thermal oxide film SiO2 in the Si thin-film layer 14 with the N<+> diffusion layer 13 through thermal oxidation. All sections of undersides and side faces and top faces except contact holes for connecting wirings are surrounded by the insulating film in a bipolar transistor region, an N-type MOSFET region and a P-type MOSFET region. There is no parasitic bipolar, and a latch-up is avoided. The element isolation region 15 can be brought to small width of 1mum or less, thus allowing the scale- down of a Bi-CMOS semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application 1 The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, high-speed large-scale integrated circuits (LS
I) is valid.

rPrior art] FIG. 5 shows a cross-sectional view of a conventional semiconductor device made of B1-CMOS.
A buried layer 33 is formed by epitaxial growth,
After forming the n-well 34 and the p-well 35, a field oxide film 39 and a gate 1f pole 37 are formed. Then collector n
0 diffusion layer 45, base P0 diffusion layer 40 formed, MOSF
After forming the source/drain P''' diffusion layer 43 and n''' diffusion layer 44 of the ET, a second layer of emitter layer 42 made of polycrystalline silicon is formed, and these bipolar and MOSFE
T is covered with a passivation film 38 and connected to the wiring layer through the contact hole.

[Problem to be solved by the invention] In the conventional B1-CMOS structure, between the bipolar and the substrate,
A parasitic bipolar transistor exists between the n-type MOS and the bipolar transistor and between the P-type MO3 and the n-type MO5. Therefore, when the noise current exceeds a certain level, the parasitic bipolar transistor becomes conductive and a steady large current flows from the current terminal to the ground terminal, causing a so-called latch-up problem. Conventionally, latch-up has been avoided by making the planar dimensions of the bipolar, P-type MO5, and n-type MOS sufficiently large and reducing the amplification factor of the parasitic bipolar. Therefore, the separation width between elements is large, making it difficult to downsize and highly integrate Bi-CMO5 semiconductor devices.

An object of the present invention is to avoid such conventional problems and provide a highly reliable and highly integrated Bi-CMO3 semiconductor device that does not cause latch-up.

[Means for Solving the Problems] According to the present invention, in a semiconductor device made of Bi-0MO5, a bipolar transistor region, an n-type MOSFE
The entire bottom and side surfaces of the T region and the P-type MOSFET region are each covered with an insulating film. Therefore, as shown in FIG. 4, in the present invention, there is no parasitic bipolar transistor and latch-up does not occur.
, nMOSFET, and bipolar transistor, except for the contact hole area for wiring connection on the top surface.
The entire surface (top, bottom, and sides) is covered with a thermal oxide film. Especially thermal oxide film Sin of silicon substrate of CZ, MCZ, FZ,
When surrounded by Si substrate and thermally oxidized SiO, lIi
Since the semiconductor device has a stable interface, interface or surface leakage can be minimized and a highly reliable semiconductor device can be obtained.

〔Example〕

The present invention will be explained below using examples. 1 to 4 are cross-sectional views of the manufacturing process of a semiconductor device according to the present invention, and FIG. 4 is a cross-sectional view of a Bi-CMO8 semiconductor device according to the present invention. A method for manufacturing a semiconductor device according to the present invention will be explained according to a flowchart of a cross-sectional view. In Figure 1, CZ, MCZ,
A thermal oxide film SiO
□2.3 is formed. In FIG. 2, the surfaces of the Si substrate 1 and the St substrate are brought into contact and bonded by heat treatment, and then
By grinding the Si substrate 5, a thermally oxidized 5iOa film 12 and a single crystal Sil film 14 having a 00 diffusion layer 13 on the lower surface are formed on the Si substrate 11. In FIG. 3, in the element isolation region of the Si thin film 14, Si is selectively removed to form a groove, and then the groove is filled with an insulating film 15.
If thermal oxidation is performed after forming up to iO*12, the Si thin film layer 14 having the n3 diffusion layer 13 will be surrounded by a thermal oxide film 5102 on the lower surface, side surfaces, and upper surface.

In FIG. 4, an n well 1t, a p well 16 are formed, a gate electrode 18, a collector n'' diffusion region 20, a base P4
A diffusion region 21 is formed, and a source/drain P0 diffusion layer 23 is formed.
, after forming the n4 diffusion layer 22, a second layer of polycrystalline 5i 25 and an emitter are formed, and passivation SiO□19.
It is covered with 24. After this, the semiconductor device according to the present invention, which is manufactured by the manufacturing method of the present invention, is connected to the wiring layer through the contact hole provided in the passivation film.
The ET region and the P-type MOSFET region are each surrounded by an insulating film on all portions of the lower surface and side surfaces, and on the upper surface except for contact holes for wiring connection. Therefore, there is no parasitic bipolar and latch-up is avoided. Therefore, the element isolation region 15 can have a small width of 1 μm or less, making it possible to downsize the Bi-CMO5 semiconductor device.6 According to the present invention, the collector n9 diffusion layer 20 is
It spreads over the entire bottom surface of the bipolar transistor. n°
Since it is connected to the diffusion layer 13, a large amplification factor can be obtained. Further, since the high concentration n' diffusion layer 13 exists on the lower surface of the n-well 17, the potential of the n-well is stabilized. Since an n″″ diffusion layer exists on the lower surface of the P well 16, the potential of the P well can be stabilized by forming an n0 layer for a power supply or ground terminal when forming the collector 20.

[Effects of the Invention] As explained above, the manufacturing method and semiconductor device of the present invention have no parasitic bipolar transistor, no latch-up problem occurs even when highly integrated, and an active region of the Si thin film 14. is the thermal oxide film S i of the Si substrate
Consisting of an Ox/Si interface, interfacial leakage can be suppressed. Furthermore, since there is an n0 diffusion layer on the bottom surface of each of the bipolar region, n-well, and p-well region, the bipolar transistor obtains a large amplification factor and the potential of both wells becomes stable. Therefore, the present invention provides a high-speed, highly reliable semiconductor device made of highly integrated Bi-CMO3 that does not cause latch-up, and a method for manufacturing the same.

[Brief explanation of the drawing]

1 to 4 are sectional views showing the manufacturing process of a semiconductor device according to the present invention, respectively. FIG. 5 is a sectional view of a conventional semiconductor device. 1.5... Semiconductor substrate 2.3... Insulating film 4... n Diffusion layer 11... Si substrate 12... Stow 13... n0 expansion layer 14...St thin film 15...5ift 16...P well 17...n well 18...gate electrode 19.24...Sing 20 ......n0 diffusion layer 21...P99 expansion 25...POLY-3i emitter 22...
n0 diffusion layer 23...P'' diffusion layer 31...Si substrate 32...n''' buried layer 33...P9 buried layer 34...n well 35 ...P well 37...Gate electrode 38.39...SiO□ 40...P° diffusion layer 41...N+ diffusion layer 42...Emitter POLY- Si43...
P00 diffusion 44...n''' diffusion layer 45...n0 diffusion layer and above

Claims (3)

[Claims] (1) In a semiconductor device consisting of bipolar and complementary MOSFETs (hereinafter referred to as Bi-CMOS), a bipolar region, an n-type MOSFET region, and a p-type MOSFET
1. A semiconductor device characterized in that the ET regions are separated from each other, and all of the upper surface, lower surface, and side surfaces except for contact hole regions for interconnection are surrounded by an insulating film. (2) In a semiconductor device made of Bi-CMOS, a bipolar region, a P-type MOSFET region, and an n-type MOS
2. The semiconductor device according to claim 1, wherein an n^+ diffusion layer is formed on the lower surface of all regions of the FET region. (3) In a semiconductor device made of Bi-CMOS, a bipolar region, an n-type MOSFET region, and a p-type MOSFET
The SFET regions include all parts of the bottom and side surfaces, respectively;
2. The semiconductor device according to claim 1, wherein the upper surface of the semiconductor substrate excluding a contact hole region for wiring connection is surrounded by a thermal oxide film of the semiconductor substrate.