JPH03131047A - Tab tape - Google Patents
Tab tapeInfo
- Publication number
- JPH03131047A JPH03131047A JP26931789A JP26931789A JPH03131047A JP H03131047 A JPH03131047 A JP H03131047A JP 26931789 A JP26931789 A JP 26931789A JP 26931789 A JP26931789 A JP 26931789A JP H03131047 A JPH03131047 A JP H03131047A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- electrodes
- dummy
- opening
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 238000010030 laminating Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 19
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 230000035882 stress Effects 0.000 description 7
- 230000008646 thermal stress Effects 0.000 description 7
- 238000007789 sealing Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明はTABテープ、更に詳しくは電気絶縁性薄板(
TABフィルム)の表面に積層した電極導出用リードの
配線間の間隔が不均一の場合に、この電極導出用リード
の寸法精度及び位置精度をより向上させたTABテープ
に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a TAB tape, more specifically an electrically insulating thin plate (
The present invention relates to a TAB tape that further improves the dimensional accuracy and positional accuracy of electrode leads laminated on the surface of a TAB film when the spacing between the wires of the electrode leads is uneven.
(従来の技術)
TA B (Tape AutorAated Bon
dlng)は、テープ状のフィルムキャリアによる自動
ボンディング技術であり、ここで使用されているTAB
テープは、従来、一般に第2図及び第3図に示すように
構成されていた。(Prior art) TA B (Tape AutoAated Bon)
dlng) is an automatic bonding technology using a tape-shaped film carrier, and the TAB
Tapes have conventionally been generally constructed as shown in FIGS. 2 and 3.
即ち、TABテープ1′は、例えばポリイミド等の合成
樹脂フィルム等の可撓性材料からなる電気絶縁性薄板2
の内部に半導体素子取付は用の開孔2aを設け、このT
ABフィルム1′の表面に、上記開孔2a内に端部3a
を延出させた複数の電極導出用リード3を積層して構成
されている。That is, the TAB tape 1' is an electrically insulating thin plate 2 made of a flexible material such as a synthetic resin film such as polyimide.
An opening 2a for mounting a semiconductor element is provided inside the T.
An end portion 3a is formed on the surface of the AB film 1' within the opening 2a.
It is constructed by stacking a plurality of electrode leads 3 extending from each other.
この電極導出用リード3は、一般に電気絶縁性薄板2の
全表面に銅箔等の金属層を接着等によって積層し、この
金属層にエツチング等の加工処理を施すことによってパ
ターン成形されたものである。The electrode lead 3 is generally formed by laminating a metal layer such as copper foil on the entire surface of the electrically insulating thin plate 2 by adhesion or the like, and then forming a pattern by subjecting this metal layer to processing such as etching. be.
そして、このようなTABテープ1′の開孔2aの内部
に半導体素子4を配置し、この半導体素子4の各電極4
aと上記電極導出用リード3の端部(延出端)2aとを
熱圧着等により電気的に接続(ボンディング)し、更に
エポキシ樹脂等の封止樹脂うで半導体素子4の周囲とT
ABテープ1′とを一体に樹脂封止して、半導体装置を
製造するようになされている。Then, a semiconductor element 4 is arranged inside the opening 2a of such TAB tape 1', and each electrode 4 of this semiconductor element 4 is
A and the end (extending end) 2a of the electrode lead 3 are electrically connected (bonded) by thermocompression bonding or the like, and then the periphery of the semiconductor element 4 and T are bonded with a sealing resin such as epoxy resin.
A semiconductor device is manufactured by integrally sealing the AB tape 1' with resin.
ここに、上記電極導出用リード3の配列は、半導体素子
4の電極4aの位置や、装着すべき半導体基板等の種々
の条件によって決まり、第2図に示すように、配線間の
間隔が不均一で、これが狭い区域と広い区域とが混在す
る場合がある。Here, the arrangement of the electrode leads 3 is determined by various conditions such as the position of the electrode 4a of the semiconductor element 4 and the semiconductor substrate to be mounted, and as shown in FIG. It is uniform, and may have a mixture of narrow and wide areas.
(発明が解′決しようとする課題)
このように、電極導出用リード3が複数本あり、かつ配
線間の間隔が不均一で狭い場合等に、工、。(Problem to be Solved by the Invention) As described above, when there are multiple electrode leads 3 and the spacing between the wires is uneven and narrow, the problem is difficult to solve.
チング等の加工を施す際、エツチング速度の相違により
電極導出用リードの幅が変化してしまったり、この時の
エツチング速度の差や接着剤の硬化の差等の影響によっ
て発生する加工応力や熱応力、更にはTABテープ自体
の収縮等により、電極導出用リードの位置が不均一にな
って、ボンディングの時の位置ずれが発生してしまうこ
とがあるといった問題点があった。When performing processing such as etching, the width of the electrode lead may change due to differences in etching speed, and processing stress and heat generated due to differences in etching speed or differences in adhesive hardening. There has been a problem in that the positions of the electrode leads may become uneven due to stress and further contraction of the TAB tape itself, resulting in misalignment during bonding.
本発明は上記に鑑み、電極導出用リードの寸法精度を向
上させるとともに、銅箔のエツチング等による加工応力
及び熱応力等によるリードの位置精度のバラツキを極力
防止するようにしたものを提供することを目的とする。In view of the above, it is an object of the present invention to provide an electrode lead that improves the dimensional accuracy of the lead and prevents as much as possible variations in the positional accuracy of the lead due to processing stress and thermal stress caused by etching of copper foil, etc. With the goal.
(課題を解決するための手段)
上記目的を達成するため、本発明に係るTABテープは
、内部に開孔を穿設した可撓性材料からなる電気絶縁性
薄板の表面に、この開孔内に端部を延出させた複数の電
極導出用リードを積層して構成され、上記開孔内に半導
体素子を位置させて該半導体素子の電極と上記電極導出
用リードの延出端とを電気的に接続して半導体装置を構
成するようにしたTABテープにおいて、上記電気絶縁
性薄板の表面の各電極導出用リード間の間隔が広い箇所
にダミーリードを設けて、上記電極導出用リードとこの
ダミーリードとが上記開孔の中央を中心として上下及び
左右にほぼ対称に分布するようにしたものである。(Means for Solving the Problems) In order to achieve the above object, the TAB tape according to the present invention has a surface of an electrically insulating thin plate made of a flexible material with an opening formed inside the opening. It is constructed by stacking a plurality of electrode lead-out leads each having an extended end portion, and a semiconductor element is positioned within the opening, and the electrode of the semiconductor element and the extended end of the electrode lead-out lead are electrically connected. In the TAB tape which is connected to each other to form a semiconductor device, a dummy lead is provided at a place on the surface of the electrically insulating thin plate where there is a wide interval between the electrode leads, and the electrode leads are connected to each other. The dummy leads are distributed approximately symmetrically vertically and horizontally with respect to the center of the opening.
(作 用)
上記のように構成した本発明によれば、電気絶縁性薄板
の表面に積層した銅箔等にエツチング加工を施してリー
ドを形成する際、ダミーリードを設けることによりこの
時のエツチング速度をより均一にして、エツチング寸法
のばらつきを少なくするとともに、エツチング後の加工
応力及び熱応力等による電極導出用リードの位置ずれ、
更には、樹脂封止後に生じる熱的ストレスによるTAB
テープ自体の反りや捩じれ等の変形を極力防止すること
ができる。(Function) According to the present invention configured as described above, when a lead is formed by etching a copper foil or the like laminated on the surface of an electrically insulating thin plate, a dummy lead is provided to prevent the etching at this time. In addition to making the etching speed more uniform and reducing variations in etching dimensions, it also prevents positional deviation of electrode leads due to processing stress and thermal stress after etching.
Furthermore, TAB due to thermal stress generated after resin sealing
Deformations such as warping and twisting of the tape itself can be prevented as much as possible.
(実施例) 以下、本発明の一実施例を第1図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.
本実施例において、TABテープ1は、例えばポリイミ
ド等の合成樹脂フィルム等の可撓性材料からなる電気絶
縁性薄板2の内部に半導体素子取付は用の開孔2aを設
け、このTABフィルム1の表面に、上記開孔2a内に
端部3aを延出させた複数の電極導出用リード3と、端
面を開孔2aの周面に一致させたダミーリード6とを積
層することによって構成されている。In this embodiment, the TAB tape 1 has an electrically insulating thin plate 2 made of a flexible material such as a synthetic resin film such as polyimide, and has an opening 2a for mounting a semiconductor element inside the TAB tape 1. It is constructed by laminating on the surface a plurality of electrode lead-out leads 3 whose ends 3a extend into the openings 2a, and dummy leads 6 whose end faces match the circumferential surface of the openings 2a. There is.
即ち、この電極導出用リード3の配列は、半導体素子4
の電極4aの位置や、半導体基板等の種々の条件によっ
て決まり、配線間の間隔が不均一で、これが狭い区域と
広い区域とが混在するのであるが、この間隔が広い区域
にダミーリード6を設けて、このダミーリード6と上記
電極導出用リード3が、上記開孔2aの中央を中心とし
て水平軸(X−X軸)に対して上下対称に、鉛直軸(Y
−Y軸)に対して左右対称に夫々分布するようなされて
いる。That is, the arrangement of the electrode leads 3 is similar to that of the semiconductor element 4.
The spacing between the wires is determined by various conditions such as the position of the electrode 4a and the semiconductor substrate, and this results in a mixture of narrow areas and wide areas. The dummy lead 6 and the electrode lead 3 are vertically symmetrical with respect to the horizontal axis (X-X axis) centered on the center of the opening 2a.
−Y axis), and are distributed symmetrically on the left and right sides.
この電極導出用リード3及びダミーリード6は、電気絶
縁性薄板2の全表面に銅箔等の金属層を積層し、この金
属層にエツチング等の加工処理を施すことによってパタ
ーン成形されたものである。The electrode lead 3 and the dummy lead 6 are pattern-formed by laminating a metal layer such as copper foil on the entire surface of the electrically insulating thin plate 2 and subjecting this metal layer to processing such as etching. be.
即ち、このように電極導出用リード3及びダミーリード
6とを同時にエツチングによるパターン成形することに
より、この時のエツチング速度をより均一にして、エツ
チング寸法のばらつきを少なくするとともに、エツチン
グ後の加工応力及び熱応力等による電極導出用リードの
位置ずれを極力防止し、更にTABテープ1自体の特に
弱い部分をダミーリード6で補強するとともに、樹脂封
止後に生じる熱的ストレスによるTABテープ1自体の
反りや捩じれ等の変形を極力防止することができるよう
なされている。That is, by etching the electrode leads 3 and the dummy leads 6 at the same time, the etching speed can be made more uniform, variations in etching dimensions can be reduced, and processing stress after etching can be reduced. In addition, the positional shift of the electrode lead lead due to thermal stress etc. is prevented as much as possible, and particularly weak parts of the TAB tape 1 itself are reinforced with dummy leads 6, and the TAB tape 1 itself is prevented from warping due to thermal stress generated after resin sealing. It is designed to prevent deformations such as twisting and twisting as much as possible.
そして、第3図に示すように、このTABテープlの開
孔2aの内部に半導体素子4を配置し、この半導体素子
4の各電極4aと上記電極導出用リード3の端部(延出
端)2aとを熱圧着等により電気的に接続(ボンディン
グ)シ、更にエポキシ樹脂等の封止材5で半導体素子4
の周囲をTABテープ1を一体に樹脂封止して、半導体
装置を製造するのである。Then, as shown in FIG. 3, a semiconductor element 4 is arranged inside the opening 2a of this TAB tape l, and each electrode 4a of this semiconductor element 4 and the end (extending end) of the electrode lead 3 are arranged. ) 2a by thermocompression bonding or the like, and further seal the semiconductor element 4 with a sealing material 5 such as epoxy resin.
The semiconductor device is manufactured by integrally sealing the periphery of the TAB tape 1 with resin.
なお、上記実施例においては、ダミーリード6は、半導
体素子部としての開孔2a内に延出しないよう構成され
ているが、ダミーリード6の端部を開孔2a内に延出さ
せ、このダミーリードの延出部を半導体素子に設けたこ
の内部との導通のないダミーの電極とを接続するように
しても良い′ことは勿論である。In the above embodiment, the dummy lead 6 is configured not to extend into the opening 2a as a semiconductor element portion, but the end of the dummy lead 6 is extended into the opening 2a, and this It goes without saying that the extended portion of the dummy lead may be connected to a dummy electrode provided on the semiconductor element that has no conduction with the interior.
本発明は上記のような構成であるので、エツチング加工
時のエツチング速度をより均一にしてエツチング寸法の
ばらつきを少なくして、電極導出用リードの寸法精度を
高めることができる。Since the present invention has the above-described structure, it is possible to make the etching speed more uniform during the etching process, reduce variations in etching dimensions, and improve the dimensional accuracy of the electrode leads.
しかも、ダミーリードによる補強と応力緩和を介して、
エツチング後の加工応力及び熱応力等による電極導出用
リードの位置ずれを極力防止するとともに、樹脂封止後
に生じる熱的ストレスによりTABテープ自体の反りや
捩じり等の変形も極力防止することができるといった効
果がある。Moreover, through reinforcement and stress relaxation by dummy leads,
It is possible to prevent as much as possible the displacement of the electrode leads due to processing stress and thermal stress after etching, and also to prevent deformation such as warping or twisting of the TAB tape itself due to thermal stress that occurs after resin sealing. It has the effect of being possible.
第1図は本発明の一実施例を示す半導体素子にボンディ
ングした状態を示す平面図、第2図は従来例を示す第1
図相当図、第3図は樹脂モールド後の断面図である。
1・・・TABテープ、2・・・電気絶縁性薄板、2a
・・・同開孔、3・・・電極導出用リード、3a・・・
同端部(延出部)、4・・・半導体素子、6・・・ダミ
ーリード。FIG. 1 is a plan view showing an embodiment of the present invention in a state where it is bonded to a semiconductor element, and FIG. 2 is a plan view showing a conventional example.
FIG. 3 is a sectional view after resin molding. 1...TAB tape, 2...Electrical insulating thin plate, 2a
...Same hole, 3...Lead for electrode extraction, 3a...
Same end portion (extending portion), 4... semiconductor element, 6... dummy lead.
Claims (1)
薄板の表面に、この開孔内に端部を延出させた複数の電
極導出用リードを積層して構成され、上記開孔内に半導
体素子を位置させて該半導体素子の電極と上記電極導出
用リードの延出端とを電気的に接続して半導体装置を構
成するようにしたTABテープにおいて、上記電気絶縁
性薄板の表面の各電極導出用リード間の間隔が広い箇所
にダミーリードを設けて、上記電極導出用リードとこの
ダミーリードとが上記開孔の中央を中心として上下及び
左右にほぼ対称に分布するようにしたことを特徴とする
TABテープ。It is constructed by laminating a plurality of electrode lead-out leads whose ends extend into the holes on the surface of an electrically insulating thin plate made of a flexible material with holes drilled inside. In a TAB tape in which a semiconductor element is positioned inside and the electrode of the semiconductor element and the extending end of the electrode lead are electrically connected to constitute a semiconductor device, the surface of the electrically insulating thin plate is A dummy lead was provided at a location where the distance between each electrode lead-out lead was wide, so that the electrode lead-out lead and this dummy lead were almost symmetrically distributed vertically and horizontally with the center of the opening as the center. TAB tape is characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1269317A JP2755731B2 (en) | 1989-10-17 | 1989-10-17 | TAB tape |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1269317A JP2755731B2 (en) | 1989-10-17 | 1989-10-17 | TAB tape |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03131047A true JPH03131047A (en) | 1991-06-04 |
JP2755731B2 JP2755731B2 (en) | 1998-05-25 |
Family
ID=17470664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1269317A Expired - Fee Related JP2755731B2 (en) | 1989-10-17 | 1989-10-17 | TAB tape |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2755731B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5289032A (en) * | 1991-08-16 | 1994-02-22 | Motorola, Inc. | Tape automated bonding(tab)semiconductor device and method for making the same |
US5471077A (en) * | 1991-10-10 | 1995-11-28 | Hughes Aircraft Company | High electron mobility transistor and methode of making |
JP2008091706A (en) * | 2006-10-03 | 2008-04-17 | Hitachi Cable Ltd | Method of manufacturing tab tape |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6344732A (en) * | 1986-08-11 | 1988-02-25 | Seiko Epson Corp | Manufacture of tape carrier |
JPS63107126A (en) * | 1986-10-24 | 1988-05-12 | Hitachi Ltd | Semiconductor device |
-
1989
- 1989-10-17 JP JP1269317A patent/JP2755731B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6344732A (en) * | 1986-08-11 | 1988-02-25 | Seiko Epson Corp | Manufacture of tape carrier |
JPS63107126A (en) * | 1986-10-24 | 1988-05-12 | Hitachi Ltd | Semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5289032A (en) * | 1991-08-16 | 1994-02-22 | Motorola, Inc. | Tape automated bonding(tab)semiconductor device and method for making the same |
US5361490A (en) * | 1991-08-16 | 1994-11-08 | Motorola, Inc. | Method for making tape automated bonding (TAB) semiconductor device |
US5471077A (en) * | 1991-10-10 | 1995-11-28 | Hughes Aircraft Company | High electron mobility transistor and methode of making |
JP2008091706A (en) * | 2006-10-03 | 2008-04-17 | Hitachi Cable Ltd | Method of manufacturing tab tape |
Also Published As
Publication number | Publication date |
---|---|
JP2755731B2 (en) | 1998-05-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |