CN116266539A - Method for forming package structure - Google Patents

Method for forming package structure Download PDF

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Publication number
CN116266539A
CN116266539A CN202111550129.6A CN202111550129A CN116266539A CN 116266539 A CN116266539 A CN 116266539A CN 202111550129 A CN202111550129 A CN 202111550129A CN 116266539 A CN116266539 A CN 116266539A
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China
Prior art keywords
lead
forming
dimension
substrate
chip
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CN202111550129.6A
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Chinese (zh)
Inventor
邢大为
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Advanced Semiconductor Materials Shenzhen Co ltd
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Advanced Semiconductor Materials Shenzhen Co ltd
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Priority to CN202111550129.6A priority Critical patent/CN116266539A/en
Priority to TW111147058A priority patent/TW202326876A/en
Publication of CN116266539A publication Critical patent/CN116266539A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A method for forming a package structure includes: forming a leadframe structure comprising opposing first and second faces, the leadframe structure comprising: a plurality of chip loading areas; the lead areas are positioned around the chip loading areas, a plurality of protruding lead parts are arranged in the lead areas, grooves extending from the first surface and the second surface are arranged between the adjacent lead parts and between the lead parts and the chip loading areas, the grooves are provided with narrowest parts and widest parts which are distributed along the direction vertical to the surface of the substrate, and the distance between the narrowest parts and the surface of the first surface of the substrate is smaller than the distance between the widest parts and the surface of the first surface of the substrate; providing a chip; fixing the chip on the first surface of the chip loading area; the chip and the lead part are electrically connected through a lead by adopting a wire bonding process; and forming a plastic sealing layer on the lead frame, the chip and the lead, wherein the plastic sealing layer covers the chip, the lead part and the lead, and the plastic sealing layer is also positioned in the groove. The reliability of the packaging structure is improved.

Description

Method for forming package structure
Technical Field
The present invention relates to the field of semiconductor packaging, and in particular, to a method for forming a packaging structure.
Background
In recent years, as the size and volume of semiconductor devices continue to be miniaturized, packaging requirements in the later stages of semiconductor fabrication are becoming more and more demanding. In order to meet such a demand, various Quad Flat No-leads Package (QFN) type semiconductor devices have been proposed, which are configured by sealing a semiconductor element mounted on a mounting surface thereof with a sealing resin using a lead frame and exposing a part of a lead to the back surface.
The existing packaging processes also need to be improved continuously to meet the higher requirements.
Disclosure of Invention
The invention provides a method for forming a packaging structure to improve the reliability of the packaging structure.
In order to solve the above technical problems, the present invention provides a method for forming a package structure, including: forming a leadframe structure, the leadframe structure including opposing first and second faces, the leadframe structure comprising: a plurality of chip loading areas; a lead region around each chip loading region, wherein a plurality of protruding lead parts are arranged in the lead region, grooves extending from a first surface and a second surface are arranged between adjacent lead parts and between the lead parts and the chip loading region, the grooves are provided with narrowest parts and widest parts which are distributed along a direction vertical to the surface of the substrate, and the distance between the narrowest parts and the surface of the first surface of the substrate is smaller than the distance between the widest parts and the surface of the first surface of the substrate; providing a chip; fixing the chip on the first surface of the chip loading area; the chip and the lead part are electrically connected through a lead by adopting a wire bonding process; and forming a plastic sealing layer on the lead frame, the chip and the lead, wherein the plastic sealing layer covers the chip, the lead part and the lead, and the plastic sealing layer is also positioned in the groove.
Optionally, the method for forming the lead frame structure includes: providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite, and the substrate comprises a plurality of chip loading areas and lead areas positioned around the chip loading areas; and etching the lead area by adopting at least two etching processes to form a plurality of raised lead parts and grooves positioned between adjacent lead parts and between the lead parts and the chip loading area.
Optionally, the groove comprises a first subsection and a second subsection positioned at the bottom of the first subsection, the top of the second subsection is communicated with the bottom of the first subsection, and the side wall surface of the second subsection is a concave surface; the narrowest portion is a bottom of the first portion and a top of the second portion, the first portion has a first dimension at a top in a first direction parallel to the leadframe surface, the narrowest portion has a second dimension in the first direction, a maximum dimension of the widest portion in the first direction is a third dimension, the first dimension is greater than the second dimension, and the second dimension is less than the third dimension.
Optionally, the cross section of the groove in the direction vertical to the surface of the substrate is an axisymmetric pattern, and the range of the third dimension single side larger than the second dimension is larger than 10 micrometers.
Optionally, the method for forming the groove includes: forming a first mask layer on a substrate, wherein the first mask layer exposes part of the surface of the substrate; etching the substrate by taking the first mask layer as a mask to form the first subsection; forming a second mask layer on the first subsection surface and the lead frame surface, wherein the second mask layer exposes part of the bottom surface of the first subsection; and etching the substrate at the bottom of the first subsection by taking the second mask layer as a mask, and forming a second subsection at the bottom of the first subsection.
Optionally, the process of etching the substrate with the first mask layer includes a wet etching process; the parameters of the wet etching process include: the etching liquid comprises a copper chloride solution or an iron chloride solution.
Optionally, the process of etching the substrate at the bottom of the first subsection by using the second mask layer as a mask includes a wet etching process or an isotropic dry etching process; the parameters of the wet etching process include: the etching liquid comprises a copper chloride solution or an iron chloride solution.
Optionally, the material of the first mask layer includes photoresist.
Optionally, the material of the second mask layer includes photoresist.
Optionally, the bottom surface of the second subsection is a concave surface, or the bottom surface of the second subsection is a plane.
Optionally, the groove further includes: the top of the third part is communicated with the bottom of the second part, and the side wall of the third part is recessed into the lead frame; the bottom of the second subsection in the first direction and the top of the third subsection in the first direction have a fourth dimension, the largest dimension of the third subsection in the first direction being a fifth dimension, the fourth dimension being smaller than the fifth dimension, the fourth dimension being greater than the second dimension.
Optionally, the grooves have an axisymmetric pattern in cross section in a direction perpendicular to the leadframe surface, and the fifth dimension is greater than the fourth dimension by a range of greater than 10 microns on one side.
Optionally, the forming method of the third subsection includes: forming a third mask layer on the first sub surface, the second sub surface and the lead frame surface, wherein the third mask layer exposes part of the bottom surface of the second sub; and etching the substrate at the bottom of the second part by taking the third mask layer as a mask, and forming a third part at the bottom of the second part.
Optionally, the process of etching the substrate at the bottom of the second sub-section by using the third mask layer as a mask includes a wet etching process or an isotropic dry etching process.
Optionally, the material of the third mask layer includes photoresist.
Optionally, the bottom of the third portion is recessed into the leadframe, or the bottom surface of the third portion is planar.
Optionally, the projected pattern of the chip loading area on the surface of the substrate is rectangular.
Optionally, the lead area includes a plurality of circles of sub-areas, the plurality of circles of sub-areas are concentrically distributed around the chip loading area, and a plurality of mutually separated lead parts are arranged in any circle of sub-areas.
Optionally, the central axes of the two adjacent circles of lead parts are not coincident.
Optionally, the substrate further includes a plurality of through holes penetrating from the first surface to the second surface of the substrate, where the through holes are located between a portion of the lead regions, or the through holes are located between a portion of the chip loading region and the lead regions.
Optionally, the method further comprises: and etching the lead area to form a plurality of openings in the lead area, wherein the openings extend from the second surface to the first surface and are communicated with the grooves.
Optionally, the forming method of the plastic sealing layer comprises the following steps: preheating the lead frame structure; injection molding a plastic packaging material layer on the lead frame; the chip, the lead part and the lead are positioned in the plastic package material layer, and the plastic package material layer is also positioned in the groove; under the action of heat treatment, the plastic sealing material layer is solidified to form a plastic sealing layer; cooling is performed after forming the plastic layer.
Optionally, the material of the plastic package material layer includes epoxy resin.
Optionally, the method for fixing the chip on the surface of the chip loading area includes: forming an adhesive layer on the chip loading region; the chip is disposed on the adhesive layer.
Optionally, the material of the leadframe structure includes a metal including copper, a copper alloy, or an iron-nickel alloy having a nickel content of 42%.
Optionally, the number of times of etching the lead area is: 2-5 times.
Optionally, the dimension of the center point of the adjacent lead portion between the first direction or the second direction is 0.4 mm or more.
Optionally, the size range of the narrowest part of the groove is more than or equal to 0.1 millimeter; the depth of the groove is 50% -70% of the thickness of the substrate.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the packaging structure formed by the technical scheme, grooves extending from the first surface and the second surface are formed between adjacent lead parts of the lead frame structure and between the lead parts and the chip loading area, the grooves are provided with the narrowest parts and the widest parts which are distributed along the direction vertical to the surface of the substrate, and the distance between the narrowest parts and the surface of the first surface of the substrate is smaller than the distance between the widest parts and the surface of the first surface of the substrate. Therefore, the size of the groove along the direction perpendicular to the surface of the lead frame is irregularly changed, so that the plastic sealing layer filled in the groove and the groove can realize a physical clamping structure during plastic sealing, the binding force between the plastic sealing layer and the side wall of the groove is improved, and the reliability of a device after plastic sealing can be improved.
Further, the groove includes a first portion having a first dimension at a top in a first direction parallel to the leadframe surface and a second portion at a bottom of the first portion having a second dimension at a bottom of the first portion and a top of the second portion in the first direction, the largest dimension of the second portion in the first direction being a third dimension, the first dimension being greater than the second dimension, the second dimension being less than the third dimension. The second size is smaller than the third size, so that the plastic sealing layer filled in the groove and the groove can realize a physical clamping structure, the bonding force between the plastic sealing layer and the side wall of the groove is improved, and the reliability of the device after plastic sealing is improved.
Drawings
FIGS. 1 and 2 are schematic cross-sectional views illustrating a package structure forming process according to an embodiment;
fig. 3 to 10 are schematic cross-sectional views illustrating a process of forming a package structure according to an embodiment of the invention;
fig. 11 to 13 are schematic cross-sectional views illustrating a process of forming a package structure according to another embodiment of the present invention;
fig. 14 and 15 are schematic cross-sectional views illustrating a process of forming a package structure according to another embodiment of the present invention;
fig. 16 and 17 are schematic cross-sectional views illustrating a process of forming a package structure according to another embodiment of the present invention.
Detailed Description
As mentioned in the background, the existing packaging process needs to be improved continuously to meet the higher requirements. The analysis will now be described with reference to specific examples.
Fig. 1 and 2 are schematic cross-sectional views illustrating a package structure forming process in an embodiment.
Referring to fig. 1, a lead frame 100 is provided, the lead frame 100 includes a chip loading area (not labeled), a lead portion (not labeled), and a groove 101 between the chip loading area and the lead portion; providing a chip 102, and fixing the chip 102 on a chip loading area; leads 103 are provided which electrically connect the chip 102 and the lead portions.
Referring to fig. 2, a molding layer 104 is formed on the leadframe 100, the chip 102 and the leads 103 are located in the molding layer 104, and the molding layer 104 is also located in the groove 101.
The package structure, the plastic sealing layer 104 is located in the groove 101, so that the contact area between the plastic sealing layer 104 and the surface of the lead frame 100 is increased, and the bonding force between the plastic sealing layer 104 and the lead frame 100 is increased, which is beneficial to improving the reliability of the package structure.
However, since the recess 101 is a bowl-shaped structure with a wide top and a narrow bottom, the plastic layer 104 and the lead frame 100 are bonded together by a surface bonding force, and when a temperature change or an external force is encountered, delamination of the plastic layer 104 and the lead frame 100 easily occurs, so that the chip fails.
In order to solve the above-mentioned problems, the present invention provides a method for forming a package structure, wherein grooves extending from a first surface and a second surface are formed between adjacent lead portions of a lead frame structure and between the lead portions and a chip loading area of the package structure, the grooves have narrowest portions and widest portions distributed in a direction perpendicular to a surface of a substrate, and a distance between the narrowest portions and the surface of the first surface of the substrate is smaller than a distance between the widest portions and the surface of the first surface of the substrate. Therefore, the size of the groove along the direction perpendicular to the surface of the lead frame is irregularly changed, so that the plastic sealing layer filled in the groove and the groove can realize a physical clamping structure during plastic sealing, the binding force between the plastic sealing layer and the side wall of the groove is improved, and the reliability of a device after plastic sealing can be improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 10 are schematic cross-sectional views illustrating a process of forming a package structure according to an embodiment of the invention.
Forming a leadframe structure comprising opposing first and second faces 201, 202, the leadframe structure comprising: a plurality of chip loading areas I; the lead areas around each chip loading area I include a plurality of protruding lead portions 204, and grooves 205 extending from the first surface 201 to the second surface 202 are provided between adjacent lead portions 204 and between the lead portions 204 and the chip loading area I, the grooves 205 having narrowest portions and widest portions distributed in a direction perpendicular to the surface of the substrate 200, and a distance between the narrowest portions and the surface of the first surface 201 of the substrate 200 is smaller than a distance between the widest portions II and the surface of the first surface 201 of the substrate 200. The process of forming the leadframe structure is shown in fig. 3-8.
Referring to fig. 3 and 4, fig. 3 is a top view of fig. 4, fig. 4 is a schematic structural view of fig. 3 along a section line BB1, and a substrate 200 is provided, wherein the substrate 200 includes a first surface 201 and a second surface 202 opposite to each other, and the substrate 200 includes a plurality of chip loading regions I and lead regions around each chip loading region I.
In this embodiment, the projected pattern of the chip loading area I on the surface of the substrate 200 is rectangular.
The lead area comprises a plurality of circles of sub-areas II, and the circles of sub-areas II are concentrically distributed around the chip loading area I.
The material of the substrate 200 includes a metal including copper, a copper alloy, or an iron-nickel alloy (42 alloy) having a nickel content of 42%.
In the present embodiment, the dimension range of the center point of the adjacent lead portion 204 between the first direction or the second direction is 0.4 mm or more.
In other embodiments, the substrate further includes a plurality of through holes extending from the first side to the second side of the substrate, the through holes being located between a portion of the lead regions, or the through holes being located between a portion of the chip loading region and the lead regions.
Next, the lead region is etched using at least two etching processes to form a plurality of raised lead portions 204, and grooves 205 between adjacent lead portions 204, between the lead portions 204 and I of the chip loading region, the grooves 205 having narrowest portions and widest portions distributed in a direction perpendicular to the surface of the substrate 200, and a distance between the narrowest portions and the surface of the first face 201 of the substrate 200 is smaller than a distance between the widest portions and the surface of the first face 201 of the substrate 200.
In this embodiment, there are several mutually discrete lead portions 204 within any one of the circles of sub-areas I. The central axes of the lead portions 204 in the adjacent two circles of sub-regions II do not coincide. So that a multi-layered wire is subsequently implemented between the wire portion 204 and the chip loading area I.
The number of times of etching the lead area is as follows: 2-5 times.
In this embodiment, the number of times the lead area is etched is 2.
In this embodiment, the groove 205 includes a first portion 206 and a second portion 207 located at the bottom of the first portion 206, where the top of the second portion 207 is in communication with the bottom of the first portion 206, and the sidewall surface of the second portion 207 is a concave surface. The process of forming the recess 205 is shown in fig. 5-8.
Referring to fig. 5, a first mask layer 210 is formed on the substrate 200, and a portion of the surface of the first surface 201 of the lead area is exposed by the first mask layer 210.
The material of the first mask layer 210 includes photoresist, which includes dry film photoresist or wet film photoresist.
In one embodiment, the material of the first mask layer 210 includes wet film photoresist, and the forming process of the first mask layer 210 includes spraying or spin coating, and exposure and development.
In another embodiment, when the material of the first mask layer 210 is a dry film photoresist, the forming process of the first mask layer 210 includes hot roll film formation and exposure development. The dry film photoresist is a full-face solid photoresist covered with a protective film.
Referring to fig. 6, the first mask layer 210 is used as a mask to etch the lead region, so as to form the first portion 206.
The process of etching the substrate 200 with the first mask layer 210 includes a wet etching process; the parameters of the wet etching process include: the etching liquid comprises a copper chloride solution or an iron chloride solution.
Referring to fig. 7, a second mask layer 211 is formed on the surface of the first portion 206 and the surface of the leadframe, and the second mask layer 211 exposes a portion of the bottom surface of the first portion 206.
The material of the second mask layer 211 includes photoresist, and the photoresist includes dry film photoresist or wet film photoresist.
In one embodiment, the material of the second mask layer 211 includes wet film photoresist; the second mask layer 211 is formed by spraying or spin coating, and exposure and development.
In another embodiment, the material of the second mask layer 211 includes a dry film photoresist, and the forming process of the second mask layer 211 includes vacuum film pressing and exposure development. The dry film photoresist is a full-face solid photoresist covered with a protective film. At this time, the surface of the lead frame is an uneven surface, and a vacuum film pressing process is required to make the second mask layer 211 closely adhere to the surface of the lead frame.
Referring to fig. 8, the substrate 200 at the bottom of the first portion 206 is etched using the second mask layer 211 as a mask, and a second portion 207 is formed at the bottom of the first portion 206.
The process of etching the substrate 200 at the bottom of the first section 206 using the second mask layer 211 as a mask includes a wet etching process or an isotropic dry etching process.
In this embodiment, the process of etching the substrate 200 at the bottom of the first section 206 with the second mask layer 211 as a mask includes a wet etching process, and parameters of the wet etching process include: the etching liquid comprises a copper chloride solution or an iron chloride solution.
The narrowest part is the bottom of the first subsection 206 and the top of the second subsection 207, the top of the first subsection 206 in the first direction X and the second direction parallel to the surface of the lead frame has a first dimension d1, the narrowest part in the first direction X and the second direction has a second dimension d2, the maximum dimension of the widest part in the first direction X and the second direction is a third dimension d3, the first dimension d1 is larger than the second dimension d2, the second dimension d2 is smaller than the third dimension d3, and the first direction X and the second direction are perpendicular to each other.
The dimensions of the groove 205 in the direction perpendicular to the leadframe surface are irregularly varied, the first dimension d1 being larger than the second dimension d2, the second dimension d2 being smaller than the third dimension d3. The plastic packaging material filled in the groove 205 and the narrowest part of the groove 205 can realize a physical clamping structure during plastic packaging, so that the bonding force between the plastic packaging material and the side wall of the groove 205 is improved, and the reliability of the device after plastic packaging can be improved.
In this embodiment, the bottom surface of the second section 207 is a concave surface.
In other embodiments, the bottom surface of the second subsection is planar.
In this embodiment, the cross section of the groove 205 in the direction perpendicular to the surface of the lead frame is an axisymmetric pattern, and the third dimension d3 is greater than the second dimension d2 on one side and is greater than 10 micrometers. To ensure that the plastic package material filled in the groove 205 later, the plastic package material in the second part 207 and the narrowest part of the groove 205 can realize a physical clamping structure, thereby improving the bonding force between the plastic package material and the side wall of the groove 205.
In this embodiment, the narrowest portion of the groove 205 has a size range of 0.1 mm or more; the depth of the groove 205 is 50% -70% of the thickness of the substrate.
Referring to fig. 9, a chip 232 is provided; the chip 232 is fixed to the surface of the first face 201 of the chip loading area I.
The method of attaching the chip 232 to the surface of the chip loading area I includes: forming an adhesive layer (not shown) on the chip loading region I; the chip 232 is disposed on the adhesive layer.
The chip 232 and the first surface 201 of the chip loading area I are fixed by means of adhesion.
With continued reference to fig. 9, a wire bonding process is used to electrically connect between the chip 232 and the lead portions 204 via leads 231.
The lead area comprises a plurality of circles of sub-areas II, the circles of sub-areas II are concentrically distributed around the chip loading area I, and a plurality of mutually separated lead parts 204 are arranged in any circle of sub-area I. The central axes of the lead portions 204 in the adjacent two circles of sub-regions II do not coincide. The lead 231 thus enables multi-layered connection between the lead portion 204 and the chip loading area I.
Referring to fig. 10, a molding layer 230 is formed on the lead frame, the chip 232 and the lead 231, the molding layer 230 encapsulates the chip 232, the lead portion 204 and the lead 231, and the molding layer 230 is further located in the groove 205.
The forming method of the plastic layer 230 includes: preheating the lead frame structure; molding a plastic package material layer on the lead frame, wherein the chip 232, the lead part 204 and the lead 231 are positioned in the plastic package material layer, and the plastic package material layer is also positioned in the groove 205; under the effect of heat treatment, the plastic sealing material layer is solidified to form a plastic sealing layer 230; the molding layer 230 is formed and then cooled.
In this embodiment, the material of the plastic layer 230 includes epoxy.
The dimensions of the groove 205 in the direction perpendicular to the leadframe surface are irregularly varied, the first dimension d1 being larger than the second dimension d2, the second dimension d2 being smaller than the third dimension d3. The narrowest part of the plastic sealing layer 230 filled in the groove 205 and the groove 205 can realize a physical clamping structure during plastic sealing, so that the bonding force between the plastic sealing layer 230 and the side wall of the groove 205 is improved, and the reliability of the device after plastic sealing can be improved.
Fig. 11 to 13 are schematic cross-sectional views illustrating a process of forming a package structure according to another embodiment of the invention.
In this embodiment, the number of times the lead area is etched is 3.
The recess 205 further comprises: a third section 408 located at the bottom of the second section 207, the top of the third section 408 being in communication with the bottom of the second section 207, the side walls of the third section 408 being recessed into the leadframe.
Referring to fig. 11, fig. 11 is a schematic structural diagram of fig. 8, in which a third mask layer 312 is formed on the surface of the first portion 206, the surface of the second portion 207 and the surface of the lead frame, and the third mask layer 312 exposes a portion of the bottom surface of the second portion 207.
In this embodiment, the material of the third mask layer 312 includes a photoresist, and the photoresist includes a dry film photoresist or a wet film photoresist.
In one embodiment, the material of the third mask layer 312 includes wet film photoresist; the third mask layer 312 is formed by spraying or spin coating, and exposure and development.
In another embodiment, the material of the third mask layer 312 includes a dry film photoresist, and the forming process of the third mask layer 312 includes vacuum film pressing and exposure and development. The dry film photoresist is a full-face solid photoresist covered with a protective film. At this time, the surface of the lead frame is uneven, and a vacuum film pressing process is required to tightly adhere the third mask layer 312 to the surface of the lead frame.
Referring to fig. 12, the substrate at the bottom of the second portion 207 is etched using the third mask layer 312 as a mask, and a third portion 408 is formed at the bottom of the second portion 207.
The process of etching the substrate at the bottom of the second section 208 using the third mask layer 312 as a mask includes a wet etching process or an isotropic dry etching process.
In this embodiment, the process of etching the substrate at the bottom of the second section 208 with the third mask layer 312 as a mask includes a wet etching process, and parameters of the wet etching process include: the etching liquid comprises a copper chloride solution or an iron chloride solution.
The narrowest part is the bottom of the first subsection 206 and the top of the second subsection 207, the top of the first subsection 206 in the first direction X and the second direction parallel to the surface of the lead frame has a first dimension d1, the narrowest part in the first direction X and the second direction has a second dimension d2, the maximum dimension of the widest part in the first direction X and the second direction is a third dimension d3, the first dimension d1 is larger than the second dimension d2, and the second dimension d2 is smaller than the third dimension d3.
The bottom of the second subsection 207 in the first direction X and the second direction and the top of the third subsection 408 in the first direction X and the second direction have a fourth dimension d4, the largest dimension of the third subsection 408 in the first direction being the widest part of the third dimension d3, the fourth dimension d4 being smaller than the third dimension d3, the fourth dimension d4 being larger than the second dimension d2.
The dimensions of the groove 205 in the direction perpendicular to the surface of the lead frame are irregularly varied, the first dimension d1 is larger than the second dimension d2, the second dimension d2 is smaller than the third dimension d3, the fourth dimension d4 is smaller than the third dimension d3, and the fourth dimension d4 is larger than the second dimension d2. The plastic packaging material filled in the groove 205 and the narrowest part of the groove 205 can realize a physical clamping structure during plastic packaging, so that the bonding force between the plastic packaging material and the side wall of the groove 205 is improved, and the reliability of the device after plastic packaging can be improved.
In this embodiment, the cross section of the groove 205 in the direction perpendicular to the surface of the lead frame is an axisymmetric pattern, and the third dimension d3 is greater than the fourth dimension d4 on one side and is greater than 10 micrometers.
In this embodiment, the bottom surface of the third section 408 of the groove 205 is a concave surface.
In other embodiments, the bottom surface of the third subsection is planar.
Referring to fig. 13, a chip 432 is provided; securing chip 432 to the surface of first face 201 of chip loading area I; a wire bonding process is used to electrically connect between chip 432 and lead portion 204 via lead 431; a molding layer 430 is formed on the leadframe, on the chip 432, and on the leads 431, the molding layer 430 encapsulating the chip 432, the lead portions 204, and the leads 431, the molding layer 430 also being located within the grooves 205.
The specific process of the plastic packaging is shown in fig. 9 and 10, and will not be described herein.
Fig. 14 and 15 are schematic cross-sectional views illustrating a process of forming a package structure according to another embodiment of the present invention.
Referring to fig. 14, fig. 14 is a schematic view of fig. 8, the lead area is etched, and a plurality of openings 620 are formed in the lead area, wherein the openings 620 extend from the second surface 202 to the first surface 201 and are in communication with the bottom of the recess 205.
The method for forming the opening 620 includes: forming a fourth mask layer (not shown) on the surface of the second surface 202 of the substrate 200, wherein the fourth mask layer exposes a part of the surface of the second surface 202 at the bottom of the groove 205; and etching the substrate 200 by taking the fourth mask layer as a mask until the fourth mask layer is communicated with the bottom of the groove 205, so as to form the opening 620.
In this embodiment, the process of etching the substrate 200 using the fourth mask layer as a mask includes a dry etching process.
Referring to fig. 15, a chip 632 is provided; fixing the chip 632 on the surface of the first surface 201 of the chip loading area I; a wire bonding process is used to electrically connect between chip 632 and lead portion 204 via lead 631; forming a plastic layer 630 on the lead frame, the chip 632 and the lead 631, wherein the plastic layer 630 covers the chip 632, the lead part 204 and the lead 631, and the plastic layer 630 is also positioned in the groove 205; the molding layer 630 is also located within the opening 620.
The specific process of the plastic packaging is shown in fig. 9 and 10, and will not be described herein.
The opening 620 is communicated with the bottom of the groove 205, so that the plastic layer 630 can be filled into the opening 620, and when the multi-layer wire is subsequently implemented between the wire part 204 and the chip loading area I, the plastic layer 630 located in the opening 620 plays a further role in isolation, which is beneficial to implementing the multi-layer wire.
Fig. 16 and 17 are schematic cross-sectional views illustrating a process of forming a package structure according to another embodiment of the present invention.
Referring to fig. 16, fig. 16 is a schematic view of fig. 12, the lead area is etched, and a plurality of openings 720 are formed in the lead area, wherein the openings 720 extend from the second surface 202 to the first surface 201 and are in communication with the bottom of the recess 205.
Referring to fig. 17, a chip 732 is provided; fixing a chip 732 to the surface of the first surface 201 of the chip loading area I; a wire bonding process is used to electrically connect between the chip 732 and the lead portions 204 via leads 731; forming a plastic layer 730 on the lead frame, the chip 732 and the leads 731, wherein the plastic layer 730 covers the chip 732, the lead portions 204 and the leads 731, and the plastic layer 730 is also located in the grooves 205; the molding layer 730 is also positioned within the opening 620.
The specific process of the plastic packaging is shown in fig. 9 and 10, and will not be described herein.
The opening 720 is communicated with the bottom of the groove 205, so that the plastic layer 630 can be filled into the opening 720, and the plastic layer 730 located in the opening 720 plays a further isolating role when the multi-layer lead is realized between the lead part 204 and the chip loading area I, which is beneficial to realizing the multi-layer lead.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (28)

1. The method for forming the packaging structure is characterized by comprising the following steps:
forming a leadframe structure, the leadframe structure including opposing first and second faces, the leadframe structure comprising: a plurality of chip loading areas; a lead region around each chip loading region, wherein a plurality of protruding lead parts are arranged in the lead region, grooves extending from a first surface and a second surface are arranged between adjacent lead parts and between the lead parts and the chip loading region, the grooves are provided with narrowest parts and widest parts which are distributed along a direction vertical to the surface of the substrate, and the distance between the narrowest parts and the surface of the first surface of the substrate is smaller than the distance between the widest parts and the surface of the first surface of the substrate;
providing a chip;
fixing the chip on the first surface of the chip loading area;
the chip and the lead part are electrically connected through a lead by adopting a wire bonding process;
and forming a plastic sealing layer on the lead frame, the chip and the lead, wherein the plastic sealing layer covers the chip, the lead part and the lead, and the plastic sealing layer is also positioned in the groove.
2. The method of forming a package structure of claim 1, wherein the method of forming a leadframe structure comprises: providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite, and the substrate comprises a plurality of chip loading areas and lead areas positioned around the chip loading areas; and etching the lead area by adopting at least two etching processes to form a plurality of raised lead parts and grooves positioned between adjacent lead parts and between the lead parts and the chip loading area.
3. The method of forming a package structure of claim 2, wherein the recess includes a first portion and a second portion at a bottom of the first portion, a top of the second portion being in communication with a bottom of the first portion, a sidewall surface of the second portion being a recessed surface; the narrowest portion is a bottom of the first portion and a top of the second portion, the first portion has a first dimension at a top in a first direction parallel to the leadframe surface, the narrowest portion has a second dimension in the first direction, a maximum dimension of the widest portion in the first direction is a third dimension, the first dimension is greater than the second dimension, and the second dimension is less than the third dimension.
4. The method of claim 3, wherein the cross-section of the recess in the direction perpendicular to the surface of the substrate is an axisymmetric pattern, and the third dimension is greater than the second dimension by more than 10 micrometers.
5. The method of forming a package structure of claim 3, wherein the method of forming the recess comprises: forming a first mask layer on a substrate, wherein the first mask layer exposes part of the surface of the substrate; etching the substrate by taking the first mask layer as a mask to form the first subsection; forming a second mask layer on the first subsection surface and the lead frame surface, wherein the second mask layer exposes part of the bottom surface of the first subsection; and etching the substrate at the bottom of the first subsection by taking the second mask layer as a mask, and forming a second subsection at the bottom of the first subsection.
6. The method of forming a package structure of claim 5, wherein etching the substrate with the first mask layer comprises a wet etching process; the parameters of the wet etching process include: the etching liquid comprises a copper chloride solution or an iron chloride solution.
7. The method of claim 5, wherein the etching the substrate at the bottom of the first portion with the second mask layer as a mask comprises wet etching or isotropic dry etching; the parameters of the wet etching process include: the etching liquid comprises a copper chloride solution or an iron chloride solution.
8. The method of claim 5, wherein the material of the first mask layer comprises photoresist.
9. The method of claim 5, wherein the material of the second mask layer comprises photoresist.
10. The method of claim 3, wherein the bottom surface of the second sub-portion is a concave surface or the bottom surface of the second sub-portion is a flat surface.
11. The method of forming a package structure of claim 3, wherein the recess further comprises: the top of the third part is communicated with the bottom of the second part, and the side wall of the third part is recessed into the lead frame; the bottom of the second subsection in the first direction and the top of the third subsection in the first direction have a fourth dimension, the largest dimension of the third subsection in the first direction being a fifth dimension, the fourth dimension being smaller than the fifth dimension, the fourth dimension being greater than the second dimension.
12. The method of claim 11, wherein the grooves have an axisymmetric pattern in cross-section in a direction perpendicular to the leadframe surface, and wherein the fifth dimension is greater than the fourth dimension by a single side in a range of greater than 10 microns.
13. The method of forming a package structure of claim 12, wherein the method of forming the third subsection comprises: forming a third mask layer on the first sub surface, the second sub surface and the lead frame surface, wherein the third mask layer exposes part of the bottom surface of the second sub; and etching the substrate at the bottom of the second part by taking the third mask layer as a mask, and forming a third part at the bottom of the second part.
14. The method of claim 13, wherein the process of etching the substrate at the bottom of the second sub-portion using the third mask layer as a mask comprises a wet etching process or an isotropic dry etching process.
15. The method of claim 13, wherein the material of the third mask layer comprises photoresist.
16. The method of claim 11, wherein a bottom of the third portion is recessed into the leadframe or a bottom surface of the third portion is planar.
17. The method of claim 1, wherein the projected pattern of the chip loading area on the surface of the substrate is rectangular.
18. The method of claim 17, wherein the lead region comprises a plurality of circles of sub-regions, the plurality of circles of sub-regions being concentrically distributed around the chip loading region, and wherein each circle of sub-regions has a plurality of mutually discrete lead portions therein.
19. The method of claim 18, wherein the central axes of two adjacent turns of the lead portion do not coincide.
20. The method of forming a package structure of claim 2, wherein the substrate further comprises a plurality of through holes extending from the first side to the second side of the substrate, the through holes being located between portions of the lead regions or between portions of the chip loading region and the lead regions.
21. The method of forming a package structure of claim 2, further comprising: and etching the lead area to form a plurality of openings in the lead area, wherein the openings extend from the second surface to the first surface and are communicated with the grooves.
22. The method of forming a package structure of claim 1, wherein the method of forming a molding layer comprises: preheating the lead frame structure; injection molding a plastic packaging material layer on the lead frame; the chip, the lead part and the lead are positioned in the plastic package material layer, and the plastic package material layer is also positioned in the groove; under the action of heat treatment, the plastic sealing material layer is solidified to form a plastic sealing layer; cooling is performed after forming the plastic layer.
23. The method of claim 22, wherein the material of the molding material layer comprises epoxy.
24. The method of forming a package structure of claim 1, wherein the method of attaching the chip to the surface of the chip loading area comprises: forming an adhesive layer on the chip loading region; the chip is disposed on the adhesive layer.
25. The method of forming a package structure of claim 1, wherein the material of the leadframe structure comprises a metal comprising copper, a copper alloy, or an iron-nickel alloy having a nickel content of 42%.
26. The method of forming a package structure of claim 2, wherein the number of times the lead region is etched is: 2-5 times.
27. The method of forming a package structure of claim 1, wherein a dimension of a center point of adjacent lead portions between the first direction or the second direction is 0.4 mm or more.
28. The method of forming a package structure of claim 3, wherein the narrowest portion of the recess has a size in a range of 0.1 mm or more; the depth of the groove is 50% -70% of the thickness of the substrate.
CN202111550129.6A 2021-12-17 2021-12-17 Method for forming package structure Pending CN116266539A (en)

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CN202111550129.6A CN116266539A (en) 2021-12-17 2021-12-17 Method for forming package structure
TW111147058A TW202326876A (en) 2021-12-17 2022-12-07 Method for forming packaging structure capable of increasing the reliability of a packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111550129.6A CN116266539A (en) 2021-12-17 2021-12-17 Method for forming package structure

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CN116266539A true CN116266539A (en) 2023-06-20

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