JP2755731B2 - TAB tape - Google Patents
TAB tapeInfo
- Publication number
- JP2755731B2 JP2755731B2 JP1269317A JP26931789A JP2755731B2 JP 2755731 B2 JP2755731 B2 JP 2755731B2 JP 1269317 A JP1269317 A JP 1269317A JP 26931789 A JP26931789 A JP 26931789A JP 2755731 B2 JP2755731 B2 JP 2755731B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- opening
- electrode lead
- tab tape
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明はTABテープ、更に詳しくは電気絶縁性薄板（T
ABフィルム）の表面に積層した電極導出用リードの配線
間の間隔が不均一の場合に、この電極導出用リードの寸
法精度及び位置精度をより向上させたTABテープに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a TAB tape, and more specifically, an electrically insulating thin plate (T
The present invention relates to a TAB tape with improved dimensional accuracy and positional accuracy of the electrode lead when the spacing between the leads of the electrode lead stacked on the surface of the AB film is uneven.
（従来の技術） TAB（Tape Automated Bonding）は、テープ状のフィ
ルムキャリアによる自動ボンディング技術であり、ここ
で使用されているTABテープは、従来、一般に第２図及
び第３図に示すように構成されていた。(Prior Art) TAB (Tape Automated Bonding) is an automatic bonding technique using a tape-like film carrier, and the TAB tape used here is generally configured as shown in FIGS. 2 and 3. It had been.
即ち、TABテープ１′は、例えばポリイミド等の合成
樹脂フィルム等の可撓性材料からなる電気絶縁性薄板２
の内部に半導体素子取付け用の開孔2aを設け、このTAB
フィルム１′の表面に、上記開孔2a内に端部3aを延出さ
せた複数の電極導出用リード３を積層して構成されてい
る。That is, the TAB tape 1 'is made of an electrically insulating thin plate 2 made of a flexible material such as a synthetic resin film such as polyimide.
An opening 2a for mounting a semiconductor element is provided inside the
On the surface of the film 1 ', a plurality of electrode lead-outs 3 each having an end 3a extending into the opening 2a are laminated.
この電極導出用リード３は、一般に電気絶縁性薄板２
の全表面に銅箔等の金属層を接続等によって積層し、こ
の金属層にエッチング等の加工処理を施すことによって
パターン成形されたものである。The electrode lead 3 is generally made of an electrically insulating thin plate 2.
Is formed by laminating a metal layer such as a copper foil on the entire surface by connection or the like, and subjecting the metal layer to processing such as etching.
そして、このようなTABテープ１′の開孔2aの内部に
半導体素子４を配置し、この半導体素子４の各電極4aと
上記電極導出用リード３の端部（延出端）2aとを熱圧着
等により電気的に接続（ボンディング）し、更にエポキ
シ樹脂等の封止樹脂５で半導体素子４の周囲とTABテー
プ１′とを一体に樹脂封止して、半導体装置を製造する
ようになされている。Then, the semiconductor element 4 is disposed inside the opening 2a of the TAB tape 1 ', and each electrode 4a of the semiconductor element 4 and the end (extending end) 2a of the electrode lead 3 are thermally connected. The periphery of the semiconductor element 4 and the TAB tape 1 'are integrally resin-sealed with a sealing resin 5 such as an epoxy resin by pressure bonding or the like, and a semiconductor device is manufactured. ing.
ここに、上記電極導出用リード３の配列は、半導体素
子４の電極4aの位置や、装着すべき半導体基板等の種々
の条件によって決まり、第２図に示すように、配線間の
間隔が不均一で、これが狭い区域と広い区域とが混在す
る場合がある。Here, the arrangement of the electrode lead-outs 3 is determined by various conditions such as the position of the electrode 4a of the semiconductor element 4 and the semiconductor substrate to be mounted. As shown in FIG. In some cases, the area is uniform, and a narrow area and a wide area are mixed.
（発明が解決しようとする課題） このように、電極導出用リード３が複数本あり、かつ
配線間の間隔が不均一で狭い場合等に、エッチング等の
加工を施す際、エッチング速度の相違により電極導出用
リードの幅が変化してしまったり、この時のエッチング
速度の差や接着剤の硬化の差等の影響によって発生する
加工応力や熱応力、更にはTABテープ自体の収縮等によ
り、電極導出用リードの位置が不均一になって、ボンデ
ィングの時の位置ずれが発生してしまうことがあるとい
った問題点があった。(Problems to be Solved by the Invention) As described above, when there are a plurality of electrode lead-out leads 3 and the intervals between the wirings are uneven and narrow, when performing a process such as etching, due to a difference in etching rate. The width of the lead for electrode lead changes, the processing stress and thermal stress generated by the difference of the etching rate and the curing of the adhesive at this time, and the shrinkage of the TAB tape itself. There has been a problem that the positions of the lead-out leads become non-uniform, which may cause a displacement during bonding.
本発明は上記に鑑み、電極導出用リードの寸法精度を
向上させるとともに、銅箔のエッチング等による加工応
力及び熱応力等によるリードの位置精度のバラツキを極
力防止するようにしたものを提供することを目的とす
る。In view of the above, the present invention provides an electrode lead for improving the dimensional accuracy of an electrode lead and minimizing variations in position accuracy of the lead due to processing stress and thermal stress due to etching of a copper foil or the like. With the goal.
［発明の構成］ （課題を解決するための手段） 上記目的を達成するため、本発明に係るTABテープ
は、内部に開孔を穿設した可撓性材料からなる電気絶縁
性薄板の表面に、この開孔内に端部を延出させた複数の
電極導出用リードを積層して構成され、上記開孔内に半
導体素子を位置させて該半導体素子の電極と上記電極導
出用リードの延出端とを電気的に接続して半導体装置を
構成するようにしたTABテープにおいて、上記電気絶縁
性薄板の表面の各電極導出用リード間の間隔が広い箇所
の上記開孔の外側に、上記電極導出用リードの上記開孔
の外側へ延びた部分に等価に対応させたダミーリードを
設けて、上記電極導出用リードとこのダミーリードとが
上記開孔の中央を中心として上下及び左右にほぼ対称に
分布するようにしたものである。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a TAB tape according to the present invention is provided on a surface of an electrically insulating thin plate made of a flexible material having an opening formed therein. A plurality of electrode lead-outs each having an end extending into the opening. The semiconductor lead is positioned in the hole, and the electrodes of the semiconductor element and the electrode lead-out are extended. In the TAB tape which is electrically connected to the protruding end to constitute a semiconductor device, the outer surface of the electrically insulating thin plate has a large space between the electrode lead-out leads, and the outside of the opening at a location where the distance is large. A dummy lead equivalently corresponding to a portion of the electrode lead leading to the outside of the opening is provided, and the electrode lead and the dummy lead are substantially vertically and horizontally around the center of the hole. The distribution is symmetrical.
（作用） 上記のように構成した本発明によれば、電気絶縁性薄
板の表面に積層した銅箔等にエッチング加工を施してリ
ードを形成する際、ダミーリードを設けることによりこ
の時のエッチング速度をより均一になり、エッチング寸
法のばらつきを少なくするとともに、エッチング後の加
工応力及び熱応力等による電極導出用リードの位置ず
れ、更には、樹脂封止後に生じる熱的ストレスによるTA
Bテープ自体の反りや捩じれ等の変形を極力防止するこ
とができる。(Function) According to the present invention configured as described above, when etching is performed on a copper foil or the like laminated on the surface of an electrically insulating thin plate to form a lead, a dummy lead is provided to provide an etching rate at this time. In addition to reducing the variation in the etching dimensions, the displacement of the lead for electrode derivation due to the processing stress and thermal stress after etching, and the TA caused by thermal stress generated after resin sealing.
It is possible to prevent deformation of the B tape itself such as warping and twisting as much as possible.
（実施例） 以下、本発明の一実施例を第１図を参照して説明す
る。Embodiment An embodiment of the present invention will be described below with reference to FIG.
本実施例において、TABテープ１は、例えばポリイミ
ド等の合成樹脂フィルム等の可撓性材料からなる電気絶
縁性薄板２の内部に半導体素子取付け用の開孔2aを設
け、このTABフィルム１の表面に、上記開孔2a内に端部3
aを延出させた複数の電極導出用リード３と、端面と開
孔2aの周面に一致させたダミーリード６とを積層するこ
とによって構成されている。In this embodiment, the TAB tape 1 is provided with an opening 2a for mounting a semiconductor element inside an electrically insulating thin plate 2 made of a flexible material such as a synthetic resin film such as polyimide. Then, the end 3 is inserted into the opening 2a.
It is constituted by laminating a plurality of electrode lead-outs 3 extending a, and dummy leads 6 whose end faces coincide with the peripheral surface of the opening 2a.
即ち、この電極導出用リード３の配列は、半導体素子
４の電極4aの位置や、半導体基板等の種々の条件によっ
て決まり、配線間の間隔が不均一で、これが狭い区域と
広い区域とが混在するのであるが、この間隔が広い区域
にダミーリード６を設けて、このダミーリード６と上記
電極導出用リード３が、上記開孔2aの中央を中心として
水平軸（Ｘ−Ｘ軸）に対して上下対称に、鉛直軸（Ｙ−
Ｙ軸）に対して左右対称に夫々分布するようなされてい
る。That is, the arrangement of the electrode lead-outs 3 is determined by the position of the electrode 4a of the semiconductor element 4 and various conditions such as the semiconductor substrate, and the intervals between the wirings are uneven, and a narrow area and a wide area are mixed. However, a dummy lead 6 is provided in the area where the space is wide, and the dummy lead 6 and the electrode lead-out lead 3 are centered on the center of the opening 2a with respect to a horizontal axis (XX axis). Vertical axis (Y-
Each of them is distributed symmetrically with respect to the Y axis).
この電極導出用リード３及びダミーリード６は、電気
絶縁性薄板２の全表面の銅箔等の金属層を積層し、この
金属層にエッチング等の加工処理を施すことによってパ
ターン成形されたものである。The electrode lead 3 and the dummy lead 6 are formed by laminating a metal layer such as a copper foil on the entire surface of the electrically insulating thin plate 2 and subjecting the metal layer to processing such as etching. is there.
即ち、このように電極導出用リード３及びダミーリー
ド６とを同時にエッチングによるパターン成形すること
により、この時のエッチング速度をより均一にして、エ
ッチング寸法のばらつきを少なくするとともに、エッチ
ング後の加工応力及び熱応力等による電極導出用リード
の位置ずれを極力防止し、更にTABテープ１自体の特に
弱い部分をダミーリード６で補強するとともに、樹脂封
止後に生じる熱的ストレスによるTABテープ１自体の反
りや捩じれ等の変形を極力防止することができるような
されている。That is, by simultaneously forming the electrode lead 3 and the dummy lead 6 by patterning by etching in this manner, the etching rate at this time is made more uniform, the variation in etching dimensions is reduced, and the processing stress after etching is reduced. In addition, the position of the lead for electrode lead-out due to thermal stress and the like is prevented as much as possible, the particularly weak portion of the TAB tape 1 itself is reinforced by the dummy lead 6, and the TAB tape 1 itself is warped due to thermal stress generated after resin sealing. It is designed to minimize deformation such as twisting and twisting.
そして、第３図に示すように、このTABテープ１の開
孔2aの内部に半導体素子４を配置し、この半導体素子４
の各電極4aと上記電極導出用リード３の端部（延出端）
2aとを熱圧着等により電気的に接続（ボンディング）
し、更にエポキシ樹脂等の封止材５で半導体素子４の周
囲をTABテープ１を一体に樹脂封止して、半導体装置を
製造するのである。Then, as shown in FIG. 3, the semiconductor element 4 is arranged inside the opening 2a of the TAB tape 1, and the semiconductor element 4
Of each electrode 4a and the electrode lead 3 (extended end)
2a is electrically connected (bonding) by thermocompression bonding etc.
Then, the TAB tape 1 is integrally resin-sealed around the semiconductor element 4 with a sealing material 5 such as an epoxy resin to manufacture a semiconductor device.
なお、上記実施例においては、ダミーリード６は、半
導体素子部としての開孔2a内に延出しないよう構成され
ているが、ダミーリード６の端部を開孔2a内に延出さ
せ、このダミーリードの延出部を半導体素子に設けたこ
の内部との導通のないダミーの電極とを接続するように
しても良いことは勿論である。In the above embodiment, the dummy lead 6 is configured so as not to extend into the opening 2a as the semiconductor element portion. However, the end of the dummy lead 6 is extended into the opening 2a. It goes without saying that the extension of the dummy lead may be connected to a dummy electrode provided on the semiconductor element and having no electrical connection with the inside.
［発明の効果］ 本発明は上記のような構成であるので、エッチング加
工時のエッチング速度をより均一にしてエッチング寸法
のばらつきを少なくして、電極導出用リードの寸法精度
を高めることができる。[Effects of the Invention] Since the present invention has the above-described configuration, the etching rate at the time of etching processing can be made more uniform, the variation in the etching dimension can be reduced, and the dimensional accuracy of the electrode lead can be increased.
しかも、ダミーリードによる補強と応力緩和を介し
て、エッチング後の加工応力及び熱応力等による電極導
出用リードの位置ずれを極力防止するとともに、樹脂封
止後に生じる熱的ストレスによりTABテープ自体の反り
や捩じり等の変形も極力防止することができるといった
効果がある。Moreover, through the reinforcement and stress relaxation by the dummy leads, the displacement of the lead for electrode lead due to the processing stress and thermal stress after etching is prevented as much as possible, and the TAB tape itself is warped due to the thermal stress generated after resin sealing. There is an effect that deformation such as deformation and torsion can be prevented as much as possible.
第１図は本発明の一実施例を示す半導体素子にボンディ
ングした状態を示す平面図、第２図は従来例を示す第１
図相当図、第３図は樹脂モールド後の断面図である。 １……TABテープ、２……電気絶縁性薄板、2a……同開
孔、３……電極導出用リード、3a……同端部（延出
部）、４……半導体素子、６……ダミーリード。FIG. 1 is a plan view showing a state of bonding to a semiconductor device according to one embodiment of the present invention, and FIG.
FIG. 3 is a sectional view after resin molding. DESCRIPTION OF SYMBOLS 1 ... TAB tape, 2 ... Electrically insulating thin plate, 2a ... Opening hole, 3 ... Lead for lead-out electrode, 3a ... End (extending portion), 4 ... Semiconductor element, 6 ... Dummy read.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−44732（ＪＰ，Ａ) 特開 昭63−107126（ＪＰ，Ａ) 特開 昭58−31566（ＪＰ，Ａ) 特開 昭64−28621（ＪＰ，Ａ) 実開 平２−142569（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-44732 (JP, A) JP-A-63-107126 (JP, A) JP-A-58-31566 (JP, A) JP-A 64-64 28621 (JP, A) Hikaru 2-142569 (JP, U) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/60
Claims (1)
電気絶縁性薄板の表面に、この開孔内に端部を延出させ
た複数の電極導出用リードを積層して構成され、上記開
孔内に半導体素子を位置させて該半導体素子の電極と上
記電極導出用リードの延出端とを電気的に接続して半導
体装置を構成するようにしたTABテープにおいて、 上記電気絶縁性薄板の表面の各電極導出用リード間の間
隔が広い箇所の上記開孔の外側に、上記電極導出用リー
ドの上記開孔の外側へ延びた部分に等価に対応させたダ
ミーリードを設けて、 上記電極導出用リードとこのダミーリードとが上記開孔
の中央を中心として上下及び左右にほぼ対称に分布する
ようにしたことを特徴とするTABテープ。1. A structure in which a plurality of electrode lead-outs each having an end extending into the opening are laminated on the surface of an electrically insulating thin plate made of a flexible material having an opening formed therein. In a TAB tape in which a semiconductor device is configured by positioning a semiconductor element in the opening and electrically connecting an electrode of the semiconductor element and an extended end of the electrode lead-out lead to form a semiconductor device, On the surface of the insulating thin plate, a dummy lead is provided outside the opening at a location where the distance between the respective electrode lead-out leads is wide, and equivalently corresponding to a portion of the electrode lead-out lead extending outside the opening. A TAB tape wherein the electrode lead and the dummy lead are distributed substantially symmetrically in the vertical and horizontal directions with the center of the opening as a center.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1269317A JP2755731B2 (en) | 1989-10-17 | 1989-10-17 | TAB tape |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1269317A JP2755731B2 (en) | 1989-10-17 | 1989-10-17 | TAB tape |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03131047A JPH03131047A (en) | 1991-06-04 |
| JP2755731B2 true JP2755731B2 (en) | 1998-05-25 |
Family
ID=17470664
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1269317A Expired - Fee Related JP2755731B2 (en) | 1989-10-17 | 1989-10-17 | TAB tape |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2755731B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5289032A (en) * | 1991-08-16 | 1994-02-22 | Motorola, Inc. | Tape automated bonding(tab)semiconductor device and method for making the same |
| US5471077A (en) * | 1991-10-10 | 1995-11-28 | Hughes Aircraft Company | High electron mobility transistor and methode of making |
| JP4993178B2 (en) * | 2006-10-03 | 2012-08-08 | 日立電線株式会社 | TAB tape manufacturing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6344732A (en) * | 1986-08-11 | 1988-02-25 | Seiko Epson Corp | Manufacture of tape carrier |
| JPS63107126A (en) * | 1986-10-24 | 1988-05-12 | Hitachi Ltd | Semiconductor device |
-
1989
- 1989-10-17 JP JP1269317A patent/JP2755731B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03131047A (en) | 1991-06-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |