JPH03131031A - Thin-film wiring, manufacture thereof and semiconductor device - Google Patents
Thin-film wiring, manufacture thereof and semiconductor deviceInfo
- Publication number
- JPH03131031A JPH03131031A JP26997289A JP26997289A JPH03131031A JP H03131031 A JPH03131031 A JP H03131031A JP 26997289 A JP26997289 A JP 26997289A JP 26997289 A JP26997289 A JP 26997289A JP H03131031 A JPH03131031 A JP H03131031A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- high melting
- thin film
- layer
- film wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 35
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 75
- 239000000956 alloy Substances 0.000 claims abstract description 75
- 238000002844 melting Methods 0.000 claims abstract description 58
- 230000008018 melting Effects 0.000 claims abstract description 56
- 239000000126 substance Substances 0.000 claims abstract description 34
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 9
- 229910052802 copper Inorganic materials 0.000 claims abstract description 8
- 229910052735 hafnium Inorganic materials 0.000 claims abstract description 6
- 239000000654 additive Substances 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 22
- 239000010936 titanium Substances 0.000 claims description 18
- 239000010408 film Substances 0.000 claims description 17
- 229910000838 Al alloy Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000006722 reduction reaction Methods 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 3
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000006479 redox reaction Methods 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 239000011135 tin Substances 0.000 claims description 2
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- 238000013508 migration Methods 0.000 abstract description 8
- 230000000996 additive effect Effects 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 4
- 230000002269 spontaneous effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 39
- 230000000694 effects Effects 0.000 description 10
- 230000005012 migration Effects 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 229910001069 Ti alloy Inorganic materials 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910000967 As alloy Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- -1 M g +Ca Chemical compound 0.000 description 1
- 229910000861 Mg alloy Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003746 solid phase reaction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、耐エレクトロマイグレーション性が向上した
薄膜配線及び、その製造方法と、それを用いた半導体装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film wiring with improved electromigration resistance, a method for manufacturing the same, and a semiconductor device using the same.
従来、半導体用薄膜配線は、通常Ａｆｉ合金単層で用い
られてきた。しかしながら、この薄膜配線では、配線の
微細化に伴い、絶縁膜等から受ける応力により断線して
しまうストレスマイグレーシミンという現象が発生した
。又、高電流密度化に伴う、配線の断線（エレクトロマ
イグレーション）も発生し、不良の原因となっていた。Conventionally, thin film wiring for semiconductors has usually been used as a single layer of Afi alloy. However, in this thin film wiring, as the wiring becomes finer, a phenomenon called stress migration shimin occurs in which the wiring breaks due to stress received from an insulating film or the like. Furthermore, as the current density increases, wire breakage (electromigration) also occurs, causing defects.
この問題を解決するため、例えば特開昭６２−１９０８
５０号公報のように、マイグレーションによる断線のほ
とんど起らない高融点金属を、Ａ４合金と積層したり、
これを包んだりして一体化し、たとえＡ４合金が断線し
たとしても、高融点金属により、電気的接続を取ること
により、配線の断線を防止していた。In order to solve this problem, for example, Japanese Patent Application Laid-Open No. 62-1908
As in Publication No. 50, a high melting point metal that hardly causes disconnection due to migration is laminated with A4 alloy,
They were wrapped and integrated, and even if the A4 alloy were to break, the high-melting point metal would maintain an electrical connection to prevent the wiring from breaking.
又、Ａ２合金中に、Ｃｕ、Ｔｉ、Ｐｄ、Ｚｒ等の元素を
添加することにより、Ａｌ合金自身の耐マイグレーショ
ン、性を向上することも試みられてきた。Furthermore, attempts have been made to improve the migration resistance and properties of the Al alloy itself by adding elements such as Cu, Ti, Pd, and Zr to the A2 alloy.
しかしながら、この方法では、金属上にＡΩ膜を堆積す
るため、Ａαの結晶配向性が旧来のＳｉｎｍ上に堆積し
たときに比べ悪くなり、Ａｌ合金自身の耐マイグレーシ
ョン性は悪くなる。そのため、一端Ａｆｌに断線が発生
すると、断線部のスリットは、Ａｌのエレクトロマイグ
レーションによる移動により、どんどん広くなる。However, in this method, since the AΩ film is deposited on the metal, the crystal orientation of Aα becomes worse than when deposited on the conventional Sinm, and the migration resistance of the Al alloy itself becomes worse. Therefore, when a disconnection occurs at one end Afl, the slit at the disconnection portion becomes wider and wider due to movement of Al due to electromigration.
更に説明を加えると、高融点物質と、良導電性合金を積
層した場合、たとえ、マイグレーションに弱い良導電合
金は断線したとしても、高融点物質は、マイグレーショ
ンにたいして、十分強いので、高融点物質が断線するこ
とはなく、電気的接続は、取り続けられる。しかしなが
ら、良導電性合金の断線部のスリットが拡大すると、配
線の電気抵抗が上昇してしまう。To explain further, when a high melting point material and a good conductive alloy are laminated, even if the good conductive alloy, which is weak against migration, breaks, the high melting point material is strong enough against migration, so the high melting point material There is no disconnection, and the electrical connection continues. However, when the slit in the disconnected portion of the highly conductive alloy becomes enlarged, the electrical resistance of the wiring increases.
高融点物質表面には、高融点物質中に含まれる最も酸素
と結合しやすい元素Ｍの自然酸化膜が存在している。そ
の様な状態で、高融点物質上に良導電性合金を堆積する
と、良導電性合金と高融点物質界面には、Ｍの自然酸化
膜が存在し、良導電性合金と高融点物質の密着性が良く
ない。そのため、良導電性合金は、エレクトロマイグレ
ーションにより、急速に移動し、断線部スリットを拡大
してしまう。On the surface of the high melting point substance, there exists a natural oxide film of the element M, which is included in the high melting point substance and is most likely to bond with oxygen. When a highly conductive alloy is deposited on a high melting point substance in such a state, a natural oxide film of M exists at the interface between the good conductive alloy and the high melting point substance, and the adhesion between the good conductive alloy and the high melting point substance increases. Sex is not good. Therefore, the highly conductive alloy rapidly moves due to electromigration and enlarges the slit at the disconnection portion.
又、Ａｌ合金中に種々の元素を添加し、Ａｌ合金自身の
耐マイグレーション性を向上したとしても、その効果だ
けでは、スリットの拡大を防止するには不十分である。Further, even if various elements are added to the Al alloy to improve the migration resistance of the Al alloy itself, the effect alone is insufficient to prevent the slit from expanding.
その結果、高抵抗の高融点金属層のみの部分が拡大し、
配線の電気抵抗が高くなる。これが、半導体装置の不良
発生の原因となる。As a result, the area containing only the high-resistance, high-melting-point metal layer expands,
The electrical resistance of the wiring increases. This causes defects in the semiconductor device.
以上説明したように上記従来技術は、Ａｌｆ！！ｉ！線
断線後の、エレクトロマイグレーションによるスリット
の拡大に伴う電気抵抗上昇について考慮されておらず、
配線の電気抵抗上昇による半導体装置の不良発生の問題
があった。As explained above, the above conventional technology is based on Alf! ! i! It does not take into account the increase in electrical resistance due to the enlargement of the slit due to electromigration after the wire is broken.
There has been a problem of failure of semiconductor devices due to increased electrical resistance of wiring.
本発明の目的は、エレクトロマイグレーションによるス
リットの拡大を防止することにあり、高信頼性の薄膜配
線、及びその製造方法を提供することを目的としている
。An object of the present invention is to prevent the expansion of slits due to electromigration, and an object of the present invention is to provide a highly reliable thin film wiring and a method for manufacturing the same.
又、別の目的は、本発明による薄膜配線を用いることに
より、高信頼性の半導体装置を提供することにある。Another object is to provide a highly reliable semiconductor device by using the thin film wiring according to the present invention.
上記目的を達成するため１本発明に係る薄膜配線は、融
点が１８００に以上の高融点物質層と。In order to achieve the above object, a thin film wiring according to the present invention includes a high melting point material layer having a melting point of 1800 or more.
良導電性合金層とが直接接触して一体化されているもの
である。すなわち、酸化膜を介さないで直接高融点物質
層と良導電性合金層とが積層している構造である。ここ
で、高融点物質層と良導電性合金層との直接接触は、高
融点物質層の表面に形成された自然酸化膜が、その上に
積層された良導電性合金層中に添加された添加物により
還元されることにより形成されたものであるのがよい。It is integrated with a highly conductive alloy layer in direct contact with it. That is, it has a structure in which a high melting point material layer and a highly conductive alloy layer are directly laminated without an oxide film interposed therebetween. Here, the direct contact between the high melting point material layer and the highly conductive alloy layer means that the natural oxide film formed on the surface of the high melting point material layer is added to the highly conductive alloy layer laminated thereon. It is preferably formed by reduction with an additive.
ここで形成される良導電性合金層は薄膜、例えば１μｍ
以下の状態で５μΩＣ■以下好ましくは４μΩＣ鳳以下
のものである。The conductive alloy layer formed here is a thin film, for example, 1 μm thick.
Under the following conditions, it is 5 μΩC or less, preferably 4 μΩC or less.
また、本発明に係る薄膜配線は、Ｔｉを０．１％以上に
含んだ融点が１８００に以上の高融点物質層と、Ｍｇ、
Ｃａ、Ｂｅ、Ｎａ、にの少なくとも１種類を０．１％以
上含んでいるＡｌ合金から成る良導電性合金層とが直接
接触して一体化されているものである。ここで、Ａｌ合
金は更に、Ｃｕ、Ｐｄ、Ｔｉ、Ｈｆ、Ｚｒの少なくとも
１種類を０．１％以上含んでいるものがよい。また、良
導電性合金としてはＣｕ、Ａｇ、Ａｕの各基合金でもよ
い、高融点物質はＴｉ、Ｗ−Ｔｉ合金、ＴｉＮ、チタン
シリサイドのいずれかであるものが挙げられる。Further, the thin film wiring according to the present invention includes a layer of a high melting point material containing 0.1% or more of Ti and having a melting point of 1800 or more, Mg,
A highly conductive alloy layer made of an Al alloy containing 0.1% or more of at least one of Ca, Be, and Na is integrated in direct contact with the layer. Here, it is preferable that the Al alloy further contains 0.1% or more of at least one of Cu, Pd, Ti, Hf, and Zr. Further, examples of the highly conductive alloy include alloys based on Cu, Ag, and Au, and examples of the high melting point substance include Ti, W--Ti alloy, TiN, and titanium silicide.
前記薄膜配線において、高融点物質中に０．１％以上含
まれる元素のうちで４５０”Ｃでの酸化物の標準生成自
由エネルギーが最も小さい元素をＭとし、良導電性合金
中の０．１％以上含まれる元素のうちで４５０℃での酸
化物の標準生成自由エネルギーが最も小さい金属元素を
Ｎとすると、ｎ Ｍ Ｏｍ ＋ Ｎ ４ ｎ Ｍ ＋
Ｎ Ｏｎ ｍ（ｎｍｍは定数、ｎｌは。と、の積、０は
酸素原子）の酸化還元反応における４５０℃での標準自
由エネルギー変化が一１００ＫＪ以下であるような元素
Ｍ及びＮを各々含むものであるのがよい、また、前記薄
膜配線において、良導電性合金層中に予め含まれている
金属元素の酸化物が存在しているものがよい。In the thin film wiring, M is the element with the smallest standard free energy of formation of an oxide at 450"C among the elements contained at 0.1% or more in the high melting point material, and 0.1% in the high conductive alloy. If the metal element with the smallest standard free energy of formation of an oxide at 450°C is N among the elements contained at least %, then n M Om + N 4 n M +
Contains the elements M and N such that the standard free energy change at 450°C in the redox reaction of N On m (nmm is a constant, nl is the product of , and 0 is an oxygen atom) is 1100 KJ or less In addition, in the thin film wiring, it is preferable that an oxide of a metal element previously contained in the highly conductive alloy layer is present.
本発明に係る薄膜配線の製造方法は、他部材に高融点物
質層を設ける工程と、その上に良導電性合金層を設ける
工程と、高融点物質層表面にできる自然酸化物を良導電
性合金中に予め添加されている添加物により還元させて
除き、前記高融点物質層と良導電性合金層とを直接接触
させた構造とする工程と、を含むのがよい。ここで、高
融点物質層はＴｉを０．１％以上含んだ融点１８００に
以上のものであり、良導電性合金層はＭｇ、Ｃａ。The method for manufacturing thin film wiring according to the present invention includes a step of providing a high melting point material layer on another member, a step of providing a highly conductive alloy layer thereon, and a step of providing a highly conductive alloy layer on the surface of the high melting point material layer. It is preferable to include the step of reducing and removing an additive previously added to the alloy to form a structure in which the high melting point substance layer and the highly conductive alloy layer are in direct contact with each other. Here, the high melting point material layer contains Ti at 0.1% or more and has a melting point of 1800 or more, and the highly conductive alloy layer is made of Mg and Ca.
Ｂｅ、Ｎａ、にの少なくとも１種類を０．１％以上含ん
でいるＡｆｉ合金であり１両層を設けた後、３５０℃以
上で１ｏ分以上加熱して前記還元反応をさせるものであ
るのがよい。好ましくは３５０℃以上５００℃以下であ
り更に好ましくは４００〜４５０℃である。あまり、高
温で処理すると半導体基板に対して悪影響を及ぼす原因
となるためである。It is an Afi alloy containing 0.1% or more of at least one of Be, Na, etc. After forming both layers, it is heated at 350° C. or higher for 10 minutes or more to cause the reduction reaction. good. The temperature is preferably 350°C or higher and 500°C or lower, and more preferably 400 to 450°C. This is because processing at too high a temperature may cause an adverse effect on the semiconductor substrate.
本発明に係る半導体装置は、ベース部材と、ベース部材
上に配設されたＬＳＩチップと、該ＬＳＩチップ上に設
けられた薄膜配線と、ベース材より突設され他部材と電
気的接続をする接続ピンと、この接続ピンと前記ＬＳＩ
チップ上の薄膜配線とを接続するリード線と、前記ＬＳ
Ｉチップを封止する封止部材とを備えた半導体装置にお
いて、その薄膜配線を前記のいずれかのもので形成した
ものである。A semiconductor device according to the present invention includes a base member, an LSI chip disposed on the base member, a thin film wiring provided on the LSI chip, and a thin film wiring protruding from the base member for electrical connection with other members. a connection pin, this connection pin and the LSI
A lead wire connecting the thin film wiring on the chip and the LS
In a semiconductor device equipped with a sealing member for sealing an I-chip, the thin film wiring is formed of one of the above-mentioned materials.
高融点物質層と、良導電性合金層とが酸化膜を介するこ
となく、直接接触して一体化されていると、高融点物質
と良導電性合金の密着性が向上する。このように、両層
間の密着性が向上すると、良導電性合金が、エレクトロ
マイグレーションにより移動しようとしても、高融点物
質からの拘束により移動できなくなる。この結果、断線
部スリットが拡大しなくなり、配線の電気抵抗上昇を防
止できる。そこで、良導電性合金中に、十分酸素と結合
しやすい元素Ｎを添加しておくと、ＮによりＭの自然酸
化膜が還元され、高融点物質と、良導電性合金が、直接
コンタクトできる様になる。When the high melting point substance layer and the good conductive alloy layer are directly contacted and integrated without intervening an oxide film, the adhesion between the high melting point substance and the good conductive alloy is improved. In this way, when the adhesion between both layers is improved, even if the highly conductive alloy tries to move by electromigration, it will not be able to move due to the restriction from the high melting point substance. As a result, the disconnection slit does not expand, and an increase in electrical resistance of the wiring can be prevented. Therefore, if enough N, an element that easily combines with oxygen, is added to a highly conductive alloy, the natural oxide film of M will be reduced by N, allowing direct contact between the high melting point substance and the highly conductive alloy. become.
又、現在半導体配線用膜として最も多く用いられれてい
る、ＡＭ基の合金を良導電性合金として選んだ場合、Ａ
Ｉ２配線自身の耐エレクトロマイグレーション性を向上
するため、Ｃｕ、Ｐｄ、Ｈｆ。In addition, if an AM-based alloy, which is currently most commonly used as a film for semiconductor wiring, is selected as a highly conductive alloy,
Cu, Pd, and Hf to improve the electromigration resistance of the I2 wiring itself.
Ｔｉ等を添加することがある。本発明は、これらの元素
を添加しても達成されるので、Ａｌ配線中にＣｕ、Ｐｄ
、Ｈｆ、Ｔｉ等を添加し、さらに、十分酸素と結合しや
すい金属元素、例えばＭ ｇ ＋Ｃａ、Ｂｅ、Ｎａ、Ｋ
を添加することも有効である。Ti or the like may be added. The present invention can be achieved even when these elements are added, so Cu, Pd is added to the Al wiring.
, Hf, Ti, etc., and furthermore, metal elements that easily combine with oxygen, such as M g +Ca, Be, Na, K
It is also effective to add
さらに、本発明の目的を十分達成するには、Ｎによる自
然酸化膜の還元反応を十分に起させる必要がある。一方
、この反応は、固相反応であり、この反応を限られた時
間に十分起させるには、最低限３５０”Ｃ以上で１０分
間以上の加熱がよい。Furthermore, in order to fully achieve the object of the present invention, it is necessary to sufficiently cause the reduction reaction of the natural oxide film by N. On the other hand, this reaction is a solid-phase reaction, and in order to cause this reaction to occur sufficiently in a limited time, heating at a temperature of at least 350''C or more for 10 minutes or more is recommended.
又、本発明の目的は、高融点物質と、良導電性合金を積
層して一体化するだけでなく、良導電性合金を高融点物
質で包んで一体化しても達成される。Further, the object of the present invention can be achieved not only by laminating and integrating a high melting point substance and a highly conductive alloy, but also by wrapping the highly conductive alloy with a high melting point substance and integrating them.
以下本発明を実施例によって詳細に説明する。 The present invention will be explained in detail below using examples.
第１図は、本発明における実施例の構造を示した断面図
である。第１図において、１はシリコンウェハー、２は
拡散層、３は熱酸化Ｓ ｉ Ｏ，膜で、それにドライエ
ツチングによりコンタクトホール６が形成されている。FIG. 1 is a sectional view showing the structure of an embodiment of the present invention. In FIG. 1, 1 is a silicon wafer, 2 is a diffusion layer, 3 is a thermally oxidized SiO film, and a contact hole 6 is formed therein by dry etching.
その上に、スパッタ法により高融点物質層４を堆積し、
その上に良導電性合金層５が堆積されている６次に、高
融点物ｇｔ、層４と、良導電性合金層５を同時にパター
ンニングする。なお、この高融点物質層４は、コンタク
トホール６で拡散層２と接触している。次に、素子表面
を保護するパッシベーション膜７をＣＶＤ法により堆積
する。この様な状態にしたウェハーを４５０℃で３０分
間加熱し急冷した。これにより、高融点物質Ｍ４の表面
にできた自然酸化膜を良導電性合金中に添加した添加物
によって還元し、両層４，５を酸化膜のない直接接触状
態のものとした。このようにして作製したウェハーを１
チツプごと分割する。A high melting point material layer 4 is deposited thereon by sputtering,
A highly conductive alloy layer 5 is deposited thereon.Next, the high melting point substance gt layer 4 and the highly conductive alloy layer 5 are patterned simultaneously. Note that this high melting point material layer 4 is in contact with the diffusion layer 2 through a contact hole 6. Next, a passivation film 7 for protecting the element surface is deposited by CVD. The wafer in this state was heated at 450° C. for 30 minutes and then rapidly cooled. As a result, the natural oxide film formed on the surface of the high melting point substance M4 was reduced by the additive added to the highly conductive alloy, and both layers 4 and 5 were brought into direct contact with no oxide film. One wafer prepared in this way
Divide each chip.
このようにして作製したサンプルに、電流密度５ Ｘ
１０’Ａ／ａＪ、温度１５０℃で通電したときの、通電
時間による電気抵抗変化を測定した。The sample prepared in this way was given a current density of 5×
When electricity was applied at 10'A/aJ and a temperature of 150°C, changes in electrical resistance depending on the electricity application time were measured.
（実施例１）
高融点物質として、Ｗ−１０％Ｔｉ合金を、良導電性合
金トシテ、Ａｌ−１％５ｉ−０，３％Ｍｇ合金を用いた
場合について、また比較例としては良導電性合金として
、Ａｌ−１％Ｓｉを、高融点金属として、Ｗ−１０％Ｔ
ｉ合金を用いた場合を挙げてのべる。(Example 1) As a high melting point substance, W-10% Ti alloy, a good conductive alloy Toshite, and an Al-1%5i-0.3% Mg alloy were used, and as a comparative example, a good conductive alloy was used. Al-1%Si as alloy, W-10%T as high melting point metal
A case in which i alloy is used will be described.
第２図に、通電時間による電気抵抗の変化を示したグラ
フを示す。同図により、Ａｌ−１％Ｓｉの良導電性合金
の場合は、時間の経過とともに、急速に電気抵抗の上昇
があったが、本発明に係るＡｌ−１％５ｉ−０，３％Ｍ
ｇの良導電性合金の場合には、電気抵抗の上昇がそれほ
ど急速ではなかった。FIG. 2 shows a graph showing the change in electrical resistance depending on the energization time. According to the same figure, in the case of the highly conductive alloy of Al-1%Si, the electrical resistance increased rapidly with the passage of time, but the Al-1%5i-0.3%M alloy according to the present invention
In the case of the highly conductive alloy of g, the increase in electrical resistance was not as rapid.
第３図に３００時間通電後の配線を、表面からａｍした
結果を示す、ＡＭ−１％Ｓｉを用いた比較例の配線では
、断線部８が、１０μｍ程度に広がっているが２本発明
に係るＡｌ−１％５ｉ−０，３％Ｍｇを用いた場合、断
線部９は、３μｍ程度広がっているのみである。Fig. 3 shows the result of ampering the wiring from the surface after being energized for 300 hours. In the wiring of a comparative example using AM-1%Si, the disconnection part 8 has spread to about 10 μm. When such Al-1%5i-0.3%Mg is used, the disconnection portion 9 only extends by about 3 μm.
又、本発明に係るＡｌ−１％５ｉ−０，３％ＭｇとＷ−
１０％Ｔｉ界面を４５０℃３０分アニール前と、アニー
ル後のサンプルでＸＰｓ分析した。その結果、Ｔｉ−０
結合ピークが、アニール前の試料では検出されたが、ア
ニール後の試料では、検出されなかった。又、Ｍｇ−０
ピークについても測定したところ、アニール前の試料で
は検出されなかったが、アニール後の試料では検出され
た。又、比較例のＡｌ−１％ＳｉとＷ−１０％Ｔｉ界面
にも測定したが、アニール前、後、両方の試料について
Ｔｉ−０ビークが検出された。これらの結果により１Ｍ
ｇをＡｌ合全中に添加すると、Ｗ−１０％Ｔｉ合金上に
あるＴｉ酸化物がＭｇにより還元されることがわかる。Moreover, Al-1%5i-0.3%Mg and W-
XPs analysis of the 10% Ti interface was performed on samples before and after annealing at 450°C for 30 minutes. As a result, Ti-0
A binding peak was detected in the pre-annealed sample but not in the post-annealed sample. Also, Mg-0
When the peak was also measured, it was not detected in the sample before annealing, but it was detected in the sample after annealing. In addition, measurement was also performed on the Al-1%Si and W-10%Ti interfaces of the comparative example, and Ti-0 peaks were detected for both samples before and after annealing. Based on these results, 1M
It can be seen that when g is added during Al synthesis, Ti oxide on the W-10% Ti alloy is reduced by Mg.
この時、次の反応
の４５０℃における標準自由エネルギー変化ΔＧは、−
１２２ｋＪである。又、次の反応の４５０℃における標
準自由エネルギー変化は、−８３ｋＪである。このよう
に、通常の半導体プロセスで、
ｎＭＯｍ＋Ｎ−＋ｎＭ＋ＮＯｎｍ
（ｎｍｍは定数＋ｎｍは。と、の積、０は酸素原子）の
反応を十分に起こさせるには、この反応の標準自由エネ
ルギー変化は、−１００ｋＪ以下でなくてはならない。At this time, the standard free energy change ΔG at 450°C for the following reaction is -
It is 122kJ. Further, the standard free energy change at 450°C for the following reaction is -83 kJ. In this way, in a normal semiconductor process, in order to sufficiently cause the reaction nMOm+N-+nM+NOnm (nmm is a constant + nm is the product of , where 0 is an oxygen atom), the standard free energy change for this reaction is - Must be less than 100kJ.
Ａｌ基合金に添加する元素としては、Ｍｇ以外にもＭｇ
よりも酸素と結合しやすい、Ｃａ ＨＢ ｅ ？Ｎａ、
Ｋを添加しても有効である。Elements added to Al-based alloys include Mg as well as Mg.
Ca HB e ? Na,
It is also effective to add K.
（実施例２） 次に、薄膜配線の加熱の効果について述べる。(Example 2) Next, the effect of heating thin film wiring will be described.
第４図に、良導電性合金としてＡｌ−１％５ｉ−０，３
％Ｍｇを、高融点物質として、Ｗ−１０％Ｔｉを用いた
場合の、３００’Ｃで３０分加熱した試料と、４００℃
で３０分加熱した試料の通電時間による電気抵抗変化を
示す、この図より、３００℃での加熱では、この場合は
不十分であり。Figure 4 shows Al-1%5i-0,3 as a good conductive alloy.
%Mg and W-10%Ti as a high melting point substance, a sample heated at 300'C for 30 minutes and a sample heated at 400°C
From this figure, which shows the electrical resistance change depending on the current application time of a sample heated for 30 minutes at 300° C., heating at 300° C. is insufficient in this case.
４００”Ｃで十分な効果が現われたことを示している。This shows that a sufficient effect was obtained at 400''C.
したがって、この実施例では少なくとも３５０℃で１０
分以上加熱しなくては１本発明の効果が得られないこと
が分かる。Therefore, in this example at least 10
It can be seen that the effects of the present invention cannot be obtained unless heating is performed for more than 1 minute.
（実施例３）
次に、Ａｌ合金中にＭｇ等以外の、従来よりＡ１２配線
自身の耐エレクトロマイグレーション性を向上するため
に添加されていた元素、例えばＣｕ、Ｐｄ、Ｔｉ、Ｈｆ
等を添加した場合について述べる。(Example 3) Next, elements other than Mg, which have been conventionally added to the Al alloy to improve the electromigration resistance of the A12 wiring itself, such as Cu, Pd, Ti, and Hf.
The following describes the case where the following substances are added.
第５図に、高融点物質としてＷ−１０％Ｔｉを、良導電
性合金としてＡｌ２−１％Ｓ ｉ−０，３％Ｍｇ−０，
３％Ｐｄを用いた場合の、電流密度５Ｘ１０’Ａ／ｃｄ
で通電したときの通電時間による電気抵抗変化のグラフ
を、従来より用いられてきたＡＭ−１％５ｉ−０，３％
Ｐｄと比較して記載する。コノ図より、Ａｌ−１％５ｉ
−０，３％Ｐｄでも電気抵抗の上昇は、ある程度抑えら
れるが、０．３％のＭｇを添加すると、さらに電気抵抗
上昇を抑えられる事がわかる。Figure 5 shows W-10%Ti as a high melting point substance, Al2-1%Si-0, 3%Mg-0, and a high-conductivity alloy.
Current density 5X10'A/cd when using 3% Pd
The graph of the change in electrical resistance depending on the energization time when energized with AM-1%5i-0.3%, which has been used conventionally, is
This will be described in comparison with Pd. From the diagram, Al-1%5i
It can be seen that even -0.3% Pd can suppress the increase in electrical resistance to some extent, but adding 0.3% Mg can further suppress the increase in electrical resistance.
このように、Ｊｕ１合金自身の耐エレクトロマイグレー
ション性を向上する元素を添加し、さらに本発明の、高
融点物質と良導電性合金の密着性を向上させる元素を添
加すると、これらの相乗効果により、さらに電気抵抗上
昇が抑えられる。In this way, by adding an element that improves the electromigration resistance of the Ju1 alloy itself, and further adding an element that improves the adhesion between the high melting point substance and the conductive alloy of the present invention, the synergistic effect of these elements will result in Furthermore, the increase in electrical resistance is suppressed.
（実施例４）
以上は、良導電性合金としてＡｌ金合金用いた場合の実
施例について述べたが他のＣｕ、Ａｇ。(Example 4) In the above, an example was described in which an Al-gold alloy was used as a good conductive alloy, but other Cu and Ag alloys were used.
Ａｕ基合金を用いてもよい。次にＡｌ合金以外のＣｕ合
金を用いた場合の実施例について述べる。An Au-based alloy may also be used. Next, an example in which a Cu alloy other than an Al alloy is used will be described.
高融点物質としてＭ ｏ 、良導電性合金としてＣｕ−
１％Ａｌ合金を用いた場合の実施例を、良導電性合金と
して純Ｃｕを用いた場合と比較して第６図に示す。同図
は、Ｉ Ｘ １０’Ａ／ａＪの電流密度で１５０℃にお
いて通電した場合の電気抵抗変化を示している。この図
のように、Ｃｕ単体では、電気抵抗が上昇するが、Ｃｕ
−１％Ａｌを用いると、はとんど電気抵抗は上昇しない
、このように本発明は、Ａｌ以外のＣｕ ｇ Ａ ｕ
ｒ Ａ ｇ等をベースにした配線にも用いることができ
る。Mo as a high melting point substance, Cu as a good conductive alloy
An example using a 1% Al alloy is shown in FIG. 6 in comparison with a case using pure Cu as a highly conductive alloy. The figure shows the change in electrical resistance when electricity is applied at a current density of I x 10'A/aJ at 150°C. As shown in this figure, the electrical resistance increases with Cu alone, but Cu
- When 1% Al is used, the electrical resistance hardly increases.In this way, the present invention can be applied to Cu g A u other than Al.
It can also be used for wiring based on rAg, etc.
第７図は本発明に係る半導体装置の断面図を示す。図に
おいて１０はセラミックからなるベース部材、１１はＬ
ＳＩチップ、１２は他部材と電気的接続を図るための接
続ピン、１３は薄膜配線、１４はリード線、１５はキャ
ップ状の封止部材、１６はガラス又はゴム封止材、１７
はろう材を示す。この半導体装置の薄膜配線１３は前記
した高融点物質層と良導電性合金層とが直線接触して一
体化されている薄膜配線で形成されている。これにより
、半導体装置全体の信頼性が向上する。FIG. 7 shows a cross-sectional view of a semiconductor device according to the present invention. In the figure, 10 is a base member made of ceramic, 11 is L
SI chip, 12 is a connecting pin for electrically connecting with other components, 13 is a thin film wiring, 14 is a lead wire, 15 is a cap-shaped sealing member, 16 is a glass or rubber sealing material, 17
indicates filler metal. The thin film wiring 13 of this semiconductor device is formed of a thin film wiring in which the above-described high melting point material layer and a highly conductive alloy layer are integrated in linear contact with each other. This improves the reliability of the entire semiconductor device.
本発明によれば、高融点物質と良導電性合金の密着性を
向上することができるので、エレクトロマイグレーショ
ンによる薄膜配線の電気抵抗上昇を抑制することができ
る。この効果により、微細配線パターンを有する半導体
装置の信頼性を向上することができる。According to the present invention, it is possible to improve the adhesion between a high melting point substance and a highly conductive alloy, so it is possible to suppress an increase in electrical resistance of thin film wiring due to electromigration. This effect makes it possible to improve the reliability of a semiconductor device having a fine wiring pattern.
本発明に係る製造方法によれば、前記薄膜配線を簡単に
製造することができる。According to the manufacturing method according to the present invention, the thin film wiring can be easily manufactured.
第１図は本発明の実施例の断面図、第２＠は本発明の一
実施例の電気抵抗の通電時間による変化を公知例として
比較した図、第３図は第２図の試料を表面からｌｌ１ｔ
察した図、第４図は焼鈍の効果について第２図と同様に
示した図、第５図は添加元素の効果について示した図、
第６図はＣｕ基合金の実施例について示した図、第７図
は本発明に係る半導体装置の断面図を示す。
１・・・シリコンウェハー ２・・・拡散層、３・・・
熱酸化ＳｉＯ２膜、４・・・高融点物質層、５・・・良
導電性合金層、
６・・・コンタクトホール、
７・・・パッシベーション膜、
１３・・・薄膜配線。Figure 1 is a cross-sectional view of an embodiment of the present invention, Figure 2 is a diagram comparing the change in electrical resistance of an embodiment of the present invention with current application time as a known example, and Figure 3 is a cross-sectional view of the sample in Figure 2. From ll1t
Figure 4 shows the effect of annealing in the same way as Figure 2, Figure 5 shows the effect of added elements,
FIG. 6 shows an example of a Cu-based alloy, and FIG. 7 shows a cross-sectional view of a semiconductor device according to the present invention. 1... Silicon wafer 2... Diffusion layer, 3...
Thermal oxidation SiO2 film, 4... High melting point material layer, 5... Good conductive alloy layer, 6... Contact hole, 7... Passivation film, 13... Thin film wiring.
Claims (1)
合金層とが直接接触して一体化されている薄膜配線。 ２、請求項１において、高融点物質と良導電性合金層と
の直接接触は、高融点物質層の表面に形成された自然酸
化膜が、その上に積層された良導電性合金層中に添加さ
れた添加物により還元されることにより形成されたもの
である薄膜配線。 ３、Ｔｉを０．１％以上に含んだ融点が１８００Ｋ以上
の高融点物質層と、Ｍｇ、Ｃａ、Ｂｅ、Ｎａ、Ｋの少な
くとも１種類を０．１％以上含んでいるＡｌ合金から成
る良導電性合金層とが直接接触して一体化されている薄
膜配線。 ４、請求項３において、Ａｌ合金は更に、Ｃｕ、Ｐｄ、
Ｔｉ、Ｈｆ、Ｚｒの少なくとも１種類を０．１％以上含
んでいる薄膜配線。 ５、請求項３において、高融点物質層はＴｉ、Ｗ−Ｔｉ
合金、ＴｉＮ、チタンシリサイドのいずれかからなる薄
膜配線。 ６、請求項１又は２において、高融点物質中に０．１％
以上含まれる元素のうちで４５０℃での酸化物の標準生
成自由エネルギーが最も小さい元素をＭとし、良導電性
合金中の０．１％以上含まれる元素のうちで４５０℃で
の酸化物の標準生成自由エネルギーが最も小さい金属元
素をＮとすると、 ｎＭＯ＿ｍ＋Ｎ→ｎＭ＋ＮＯ＿ｎ＿ｍ （ｎ、ｍは定数、ｎｍはｎとｍの積、Ｏは酸素原子）の
酸化還元反応における４５０℃での標準自由エネルギー
変化が−１００ＫＪ以下であるような元素Ｍ及びＮを各
々含むものである薄膜配線。 ７、請求項２において、良導電性合金層中に予め含まれ
ている金属元素の酸化物が存在している薄膜配線。 ８、他部材に高融点物質層を設ける工程と、その上に良
導電性合金層を設ける工程と、高融点物質層表面にでき
る自然酸化物を良導電性合金中に予め添加されている添
加物により還元させて除き、前記高融点物質層と良導電
性合金層とを直接接触させた構造とする工程と、を含む
薄膜配線の製造方法。 ９、請求項８において、高融点物質層はＴｉを０．１％
以上含んだ融点１８００Ｋ以上のものであり、良導電性
合金層はＭｇ、Ｃａ、Ｂｅ、Ｎａ、Ｋの少なくとも１種
類を０．１％以上含んだＡｌ合金であり、両層を設けた
後、３５０℃以上で１０分以上加熱して前記還元反応を
させるものである薄膜配線の製造方法。 １０、ベース部材と、ベース部材上に配設されたＬＳＩ
チップと、該ＬＳＩチップ上に設けられた薄膜配線と、
ベース材より突設され他部材と電気的接続をする接続ピ
ンと、この接続ピンと前記ＬＳＩチップ上の薄膜配線と
を接続するリード線と、前記ＬＳＩチップを封止する封
止部材とを備えた半導体装置において、前記薄膜配線は
請求項１〜７のいずれかのものである半導体装置。[Claims] 1. A thin film wiring in which a high melting point material layer with a melting point of 1800K or more and a highly conductive alloy layer are directly contacted and integrated. 2. In claim 1, the direct contact between the high melting point substance and the conductive alloy layer means that the natural oxide film formed on the surface of the high melting point substance layer is in the conductive alloy layer laminated thereon. Thin film wiring formed by being reduced by added additives. 3. A high-melting material layer containing 0.1% or more of Ti and having a melting point of 1800K or more, and an Al alloy containing 0.1% or more of at least one of Mg, Ca, Be, Na, and K. Thin film wiring that is integrated with a conductive alloy layer in direct contact. 4. In claim 3, the Al alloy further includes Cu, Pd,
A thin film wiring containing 0.1% or more of at least one of Ti, Hf, and Zr. 5. In claim 3, the high melting point material layer is Ti, W-Ti
Thin film wiring made of alloy, TiN, or titanium silicide. 6. In claim 1 or 2, 0.1% in the high melting point substance
Among the elements contained above, the element with the smallest standard free energy of formation of an oxide at 450°C is defined as M, and among the elements contained at 0.1% or more in the conductive alloy, the oxide at 450°C is If the metal element with the lowest standard free energy of formation is N, then the standard free energy change at 450°C in the redox reaction of nMO_m+N→nM+NO_n_m (n, m are constants, nm is the product of n and m, O is oxygen atom) A thin film wiring containing elements M and N, each of which has a value of -100 KJ or less. 7. The thin film wiring according to claim 2, wherein an oxide of a metal element previously contained in the highly conductive alloy layer is present. 8. The process of providing a high melting point substance layer on another member, the process of providing a good conductive alloy layer thereon, and the addition of natural oxides formed on the surface of the high melting point substance layer to the good conductive alloy in advance. A method for producing a thin film wiring comprising the step of reducing and removing the high melting point substance layer with a substance to form a structure in which the high melting point substance layer and the highly conductive alloy layer are in direct contact with each other. 9. In claim 8, the high melting point material layer contains 0.1% Ti.
The well-conductive alloy layer is an Al alloy containing 0.1% or more of at least one of Mg, Ca, Be, Na, and K, and after providing both layers, A method for manufacturing thin film wiring, which involves heating at 350° C. or higher for 10 minutes or more to cause the reduction reaction. 10. Base member and LSI arranged on the base member
a chip, a thin film wiring provided on the LSI chip,
A semiconductor comprising a connecting pin that protrudes from a base material and makes an electrical connection to another member, a lead wire that connects the connecting pin to the thin film wiring on the LSI chip, and a sealing member that seals the LSI chip. 8. A semiconductor device, wherein the thin film wiring is any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26997289A JP2936483B2 (en) | 1989-10-17 | 1989-10-17 | Thin film wiring and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26997289A JP2936483B2 (en) | 1989-10-17 | 1989-10-17 | Thin film wiring and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03131031A true JPH03131031A (en) | 1991-06-04 |
| JP2936483B2 JP2936483B2 (en) | 1999-08-23 |
Family
ID=17479792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26997289A Expired - Fee Related JP2936483B2 (en) | 1989-10-17 | 1989-10-17 | Thin film wiring and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2936483B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102152A (en) * | 1991-10-11 | 1993-04-23 | Sony Corp | Semiconductor device |
-
1989
- 1989-10-17 JP JP26997289A patent/JP2936483B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102152A (en) * | 1991-10-11 | 1993-04-23 | Sony Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2936483B2 (en) | 1999-08-23 |
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