JP2936483B2 - Thin film wiring and semiconductor device - Google Patents
Thin film wiring and semiconductor deviceInfo
- Publication number
- JP2936483B2 JP2936483B2 JP26997289A JP26997289A JP2936483B2 JP 2936483 B2 JP2936483 B2 JP 2936483B2 JP 26997289 A JP26997289 A JP 26997289A JP 26997289 A JP26997289 A JP 26997289A JP 2936483 B2 JP2936483 B2 JP 2936483B2
- Authority
- JP
- Japan
- Prior art keywords
- alloy
- film wiring
- melting point
- thin film
- high melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、耐エレクトロマイグレーション性が向上し
た薄膜配線及び、それを用いた半導体装置に関する。Description: TECHNICAL FIELD The present invention relates to a thin film wiring with improved electromigration resistance and a semiconductor device using the same.
従来、半導体用薄膜配線は、通常Al合金単層で用いら
れてきた。しかしながら、この薄膜配線では、配線の微
細化に伴い、絶縁膜等から受ける応力により断線してし
まうストレスマイグレーションという現象が発生した。
又、高電流密度化に伴う、配線の断線（エレクトロマイ
グレーション）も発生し、不良の原因となっていた。Conventionally, thin film wiring for semiconductors has been usually used as a single layer of Al alloy. However, in this thin-film wiring, a phenomenon called stress migration, in which the wiring is broken by a stress received from an insulating film or the like, has occurred with the miniaturization of the wiring.
In addition, the disconnection (electromigration) of the wiring was also caused by the increase in the current density, which was the cause of the failure.
この問題を解決するため、例えば特開昭62−190850号
公報のように、マイグレーションによる断線のほとんど
起らない高融点金属を、Al合金と積層したり、これを包
んだりして一体化し、たとえAl合金が断線したとして
も、高融点金属により、電気的接続を取ることにより、
配線の断線を防止していた。To solve this problem, for example, as disclosed in Japanese Patent Application Laid-Open No. 62-190850, a high-melting-point metal that hardly causes disconnection due to migration is laminated with an Al alloy, or wrapped around and integrated. Even if the Al alloy breaks, by making electrical connection with the high melting point metal,
The disconnection of the wiring was prevented.
又、Al合金中に、Cu,Ti,Pd,Zr等の元素を添加するこ
とにより、Al合金自身の耐マイグレーション性を向上す
ることも試みられてきた。Attempts have also been made to improve the migration resistance of the Al alloy itself by adding elements such as Cu, Ti, Pd, and Zr to the Al alloy.
しかしながら、この方法では、金属上にAl膜を堆積す
るため、Alの結晶配向性が旧来のSiO2上に堆積したとき
に比べ悪くなり、Al合金自身の耐マイグレーション性は
悪くなる。そのため、一端Alに断線が発生すると、断線
部のスリットは、Alのエレクトロマイグレーションによ
る移動により、どんどん広くなる。However, in this method, since an Al film is deposited on a metal, the crystal orientation of Al is worse than that of a conventional SiO 2 film, and the migration resistance of the Al alloy itself is worse. Therefore, when a disconnection occurs at one end Al, the slit at the disconnection portion becomes wider gradually due to the movement of Al by electromigration.
更に説明を加えると、高融点物質と、良導電性合金を
積層した場合、たとえ、マイグレーションに弱い良導電
合金は断線したとしても、高融点物質は、マイグレーシ
ョンにたいして、十分強いので、高融点物質が断線する
ことはなく、電気的接続は、取り続けられる。しかしな
がら、良導電性合金の断線部のスリットが拡大すると、
配線の電気抵抗が上昇してしまう。To further explain, when a high melting point material and a good conductive alloy are laminated, even if a good conductive alloy weak to migration breaks, the high melting point material is sufficiently strong against migration. There is no disconnection and the electrical connection is maintained. However, when the slit at the break of the good conductive alloy is enlarged,
The electric resistance of the wiring increases.
高融点物質表面には、高融点物質中に含まれる最も酸
素と結合しやすい元素Ｍの自然酸化膜が存在している。
その様な状態で、高融点物質上に良導電性合金を堆積す
ると、良導電性合金と高融点物質界面には、Ｍの自然酸
化膜が存在し、良導電性合金と高融点物質の密着性が良
くない。そのため、良導電性合金は、エレクトロマイグ
レーションにより、急速に移動し、断線部スリットを拡
大してしまう。On the surface of the high-melting substance, there is a natural oxide film of the element M which is most easily bonded to oxygen contained in the high-melting substance.
In such a state, when a good conductive alloy is deposited on the high melting point material, a natural oxide film of M exists at the interface between the good conductive alloy and the high melting point material, and the close contact between the good conductive alloy and the high melting point material. Not good. Therefore, the good conductive alloy moves rapidly due to electromigration, and enlarges the disconnection slit.
又、Al合金中に種々の元素を添加し、Al合金自身の耐
マイグレーション性を向上したとしても、その効果だけ
では、スリットの拡大を防止するには不十分である。そ
の結果、高抵抗の高融点金属層のみの部分が拡大し、配
線の電気抵抗が高くなる。これが、半導体装置の不良発
生の原因となる。Even if various elements are added to the Al alloy to improve the migration resistance of the Al alloy itself, the effect alone is not enough to prevent the slit from expanding. As a result, the portion of only the high-resistance refractory metal layer is enlarged, and the electrical resistance of the wiring is increased. This causes a failure of the semiconductor device.
以上説明したように上記従来技術は、Al配線断線後
の、エレクトロマイグレーションによるスリットの拡大
に伴う電気抵抗上昇について考慮されておらず、配線の
電気抵抗上昇による半導体装置の不良発生の問題があっ
た。As described above, the conventional technique does not consider the increase in electrical resistance due to the expansion of the slit due to electromigration after disconnection of the Al wiring, and there has been a problem of occurrence of a defect in the semiconductor device due to the increase in electrical resistance of the wiring. .
本発明の目的は、エレクトロマイグレーションによる
スリットの拡大を防止することにあり、高信頼性の薄膜
配線を提供することを目的としている。An object of the present invention is to prevent a slit from expanding due to electromigration, and an object of the present invention is to provide a highly reliable thin film wiring.
又、別の目的は、本発明による薄膜配線を用いること
により、高信頼性の半導体装置を提供することにある。Another object is to provide a highly reliable semiconductor device by using the thin film wiring according to the present invention.
上記目的を達成するために、本発明に係る薄膜配線
は、Tiを0.1％以上に含んだ融点が1800K以上の高融点物
質層と、Mg,Ca,Be,Na,Kの少なくとも１種類を0.1％以上
含んでいるAl合金から成る良導電性合金層とが直接接触
して一体化されているものである。ここで、Al合金は更
に、Cu,Pd,Ti,Hf,Zrの少なくとも１種類を0.1％以上含
んでいるものがよい。また、良導電性合金としてはCu,A
g,Auの各基合金でもよい。高融点物質はTi,W−Ti合金、
TiN,チタンシリサイドのいずれかであるものが挙げられ
る。In order to achieve the above object, a thin film wiring according to the present invention includes a high melting point material layer containing Ti at 0.1% or more and having a melting point of 1800K or more, and at least one of Mg, Ca, Be, Na, and K. %, And is in direct contact with and integrated with a good conductive alloy layer made of an Al alloy containing at least 10%. Here, the Al alloy preferably further contains at least one of Cu, Pd, Ti, Hf, and Zr in an amount of 0.1% or more. In addition, Cu, A
Each base alloy of g and Au may be used. High melting point material is Ti, W-Ti alloy,
One that is either TiN or titanium silicide can be mentioned.
前記薄膜配線において、高融点物質中に0.1％以上含
まれる元素のうちで450℃での酸化物の標準生成自由エ
ネルギーが最も小さい元素をＭとし、良導電性合金中の
0.1％以上含まれる元素のうちで450℃での酸化物の標準
生成自由エネルギーが最も小さい金属元素をＮとする
と、 nMOm＋Ｎ→nM＋NOnm （n,mは定数、nmはｎとｍの積、Ｏは酸素原子） の酸化還元反応における450℃での標準自由エネルギー
変化が−100KJ以下であるような元素Ｍ及びＮを各々含
むものであるのがよい。In the thin-film wiring, among the elements contained in the high melting point material of 0.1% or more, the element having the smallest standard free energy of formation of oxide at 450 ° C. is defined as M,
Assuming that the metal element having the smallest standard free energy of formation of oxide at 450 ° C. among the elements contained at 0.1% or more is N, nMO m + N → nM + NO nm (where n and m are constants and nm is the product of n and m ) , O is an oxygen atom.) It is preferable that each element contains elements M and N such that the standard free energy change at 450 ° C. in the oxidation-reduction reaction is −100 KJ or less.
本発明に係る半導体装置は、ベース部材と、ベース部
材上に配設されたLSIチップと、該LSIチップ上に設けら
れた薄膜配線と、ベース材より突設され他部材と電気的
接続をする接続ピンと、この接続ピンと前記LSIチップ
上の薄膜配線とを接続するリード線と、前記LSIチップ
を封止する封止部材とを備えた半導体装置において、そ
の薄膜配線を前記のいずれかのもので形成したものであ
る。A semiconductor device according to the present invention includes a base member, an LSI chip provided on the base member, a thin-film wiring provided on the LSI chip, and an electrical connection with other members protruded from the base material. In a semiconductor device comprising a connection pin, a lead wire connecting the connection pin and a thin film wiring on the LSI chip, and a sealing member for sealing the LSI chip, the thin film wiring may be any one of the above. It is formed.
高融点物質層と、良導電性合金層とが酸化膜を介する
ことなく、直接接触して一体化されていると、高融点物
質と良導電性合金の密着性が向上する。このように、両
層間の密着性が向上すると、良導電性合金が、エレクト
ロマイグレーションにより移動しようとしても、高融点
物質からの拘束により移動できなくなる。この結果、断
線部スリットが拡大しなくなり、配線の電気抵抗上昇を
防止できる。When the high melting point material layer and the good conductive alloy layer are directly contacted and integrated without passing through the oxide film, the adhesion between the high melting point material and the good conductive alloy is improved. As described above, when the adhesion between the two layers is improved, even if the good conductive alloy attempts to move by electromigration, it cannot move due to the constraint from the high melting point material. As a result, the disconnection slit does not expand, and an increase in the electrical resistance of the wiring can be prevented.
又、現在半導体配線用膜として最も多く用いられれて
いる、Al基の合金を良導電性合金として選んだ場合、Al
配線自身の耐エレクトロマイグレーション性を向上する
ため、Cu,Pd,Hf,Ti等を添加することがある。本発明
は、これらの元素を添加しても達成されるので、Al配線
中にCu,Pd,Hf,Ti等を添加し、さらに、十分酸素と結合
しやすい金属元素、例えばMg,Ca,Be,Na,Kを添加するこ
とも有効である。In addition, when an Al-based alloy, which is currently most frequently used as a film for semiconductor wiring, is selected as a good conductive alloy,
In order to improve the electromigration resistance of the wiring itself, Cu, Pd, Hf, Ti or the like may be added. Since the present invention can be achieved by adding these elements, Cu, Pd, Hf, Ti, etc. are added to the Al wiring, and further, a metal element which easily bonds to oxygen, for example, Mg, Ca, Be , Na and K are also effective.
又、本発明の目的は、高融点物質と、良導伝性合金を
積層して一体化するだけでなく、良導伝性合金を高融点
物質で包んで一体化しても達成される。Further, the object of the present invention can be achieved not only by laminating and integrating a high-melting substance and a high-conductivity alloy, but also by wrapping and integrating the high-conductivity alloy with a high-melting substance.
以下本発明を実施例によって詳細に説明する。第１図
は、本発明における実施例の構造を示した断面図であ
る。第１図において、１はシリコンウエハー、２は拡散
層、３は熱酸化SiO2膜で、それにドライエッチングによ
りコンタクトホール６が形成されている。その上に、ス
パッタ法により高融点物質層４を推積し、その上に良導
電性合金層５が推積されている。次に、高融点物質層４
と、良導電性合金層５を同時にパターンニングする。な
お、この高融点物質層４は、コンタクトホール６で拡散
層２と接触している。次に、素子表面を保護するパッシ
ベーション膜７をCVD法により推積する。この様な状態
にしたウエハーを450℃で30分間加熱し急冷した。これ
により、高融点物質層４の表面にできた自然酸化膜を良
導電性合金中に添加した添加物によって還元し、両層4,
5を酸化膜のない直接接触状態のものとした。このよう
にして作製したウエハーを１チップごと分割する。Hereinafter, the present invention will be described in detail with reference to examples. FIG. 1 is a sectional view showing the structure of an embodiment of the present invention. In FIG. 1, 1 is a silicon wafer, 2 is a diffusion layer, 3 is a thermally oxidized SiO 2 film, and a contact hole 6 is formed in the film by dry etching. A high melting point material layer 4 is deposited thereon by a sputtering method, and a good conductive alloy layer 5 is deposited thereon. Next, the high melting point material layer 4
And the good conductive alloy layer 5 are simultaneously patterned. The high melting point material layer 4 is in contact with the diffusion layer 2 at the contact hole 6. Next, a passivation film 7 for protecting the element surface is deposited by a CVD method. The wafer in such a state was heated at 450 ° C. for 30 minutes and rapidly cooled. As a result, the natural oxide film formed on the surface of the high melting point material layer 4 is reduced by the additive added to the good conductive alloy,
5 was in direct contact without an oxide film. The wafer thus manufactured is divided for each chip.
このようにして作製したサンプルに、電流密度５×10
6A/cm2,温度150℃で通電したときの、通電時間による電
気抵抗変化を測定した。A sample having a current density of 5 × 10
When a current was supplied at 6 A / cm 2 and a temperature of 150 ° C., a change in electric resistance with the current supply time was measured.
（実施例１） 高融点物質として、Ｗ−10％Ti合金を、良導電性合金
として、Al−１％Si−0.3％Mg合金を用いた場合につい
て、また比較例としては良導電性合金として、Al−１％
Siを、高融点金属として、Ｗ−10％Ti合金を用いた場合
を挙げてのべる。(Example 1) A case where a W-10% Ti alloy was used as a high melting point material and an Al-1% Si-0.3% Mg alloy was used as a good conductive alloy, and a comparative example was a good conductive alloy. , Al-1%
The case where a W-10% Ti alloy is used as Si as the high melting point metal will be described.
第２図に、通電時間による電気抵抗の変化を示したグ
ラフを示す。同図により、Al−１％Siの良導電性合金の
場合は、時間の経過とともに、急速に電気抵抗の上昇が
あったが、本発明に係るAl−１％Si−0.3％Mgの良導電
性合金の場合には、電気抵抗の上昇がそれほど急速では
なかった。FIG. 2 is a graph showing a change in electric resistance according to the energization time. According to the figure, in the case of a good conductive alloy of Al-1% Si, the electric resistance rapidly increased with time, but the good conductive alloy of Al-1% Si-0.3% Mg according to the present invention. In the case of a neutral alloy, the increase in electric resistance was not so rapid.
第３図に300時間通電後の配線を、表面から観察した
結果を示す。Al−１％Siを用いた比較例の配線では、断
線部８が、10μｍ程度に広がっているが、本発明に係る
Al−１％Si−0.3％Mgを用いた場合、断線部９は、３μ
ｍ程度広がっているのみである。FIG. 3 shows the result of observing the wiring after conducting for 300 hours from the surface. In the wiring of the comparative example using Al-1% Si, the disconnection portion 8 is spread to about 10 μm.
In the case of using Al-1% Si-0.3% Mg, the disconnection portion 9 is 3 μm.
only about m.
又、本発明に係るAl−１％Si−0.3％MgとＷ−10％Ti
界面を450℃30分アニール前と、アニール後のサンプル
でXPS分析した。その結果、Ti−０結合ピークが、アニ
ール前の試料では検出されたが、アニール後の試料で
は、検出されなかった。又、Mg−０ピークについても測
定したところ、アニール前の試料では検出されなかった
が、アニール後の試料では検出された。又、比較例のAl
−１％SiとＷ−10％Ti界面にも測定したが、アニール
前、後、両方の試料についてTi−０ピークが検出され
た。これらの結果により、MgをAl合金中に添加すると、
Ｗ−10％Ti合金上にあるTi酸化物がMgにより還元される
ことがわかる。この時、次の反応 の450℃における標準自由エネルギー変化ΔＧは、−122
kJである。又、次の反応 の450℃における標準自由エネルギー変化は、−83kJで
ある。このように、通常の半導体プロセスで、 nMOm＋Ｎ→nM＋NOnm （n,mは定数、nmはｎとｍの積、Ｏは酸素原子）の反応
を十分に起こさせるには、この反応の標準自由エネルギ
ー変化は、−100kJ以下でなくてはならない。Also, according to the present invention, Al-1% Si-0.3% Mg and W-10% Ti
XPS analysis was performed on the interface before and after annealing at 450 ° C. for 30 minutes. As a result, a Ti-0 binding peak was detected in the sample before annealing, but not detected in the sample after annealing. The measurement of the Mg-0 peak was not detected in the sample before annealing, but was detected in the sample after annealing. Also, Al of the comparative example
Measurements were also made at the -1% Si and W-10% Ti interfaces, but a Ti-0 peak was detected in both samples before and after annealing. According to these results, when Mg is added to Al alloy,
It can be seen that the Ti oxide on the W-10% Ti alloy is reduced by Mg. At this time, the next reaction The standard free energy change ΔG at 450 ° C. is −122
kJ. Also, the next reaction The standard free energy change at 450 ° C. is -83 kJ. Thus, in the normal semiconductor process, nMO m + N → nM + NO nm (n, m is a constant, nm is the product of n and m , and O is an oxygen atom). Free energy change must be less than -100 kJ.
Al基合金に添加する元素としては、Mg以外にもMgより
も酸素と結合しやすい、Ca,Be,Na,Kを添加しても有効で
ある。As an element to be added to the Al-based alloy, it is effective to add Ca, Be, Na, and K, which are more easily bonded to oxygen than Mg, in addition to Mg.
（実施例２） 次に、薄膜配線の加熱の効果について述べる。第４図
に、良導電性合金としてAl−１％Si−0.3％Mgを、高融
点物質として、Ｗ−10％Tiを用いた場合の、300℃で30
分加熱した試料と、400℃で30分加熱した試料の通電時
間による電気抵抗変化を示す。この図より、300℃での
加熱では、この場合は不十分であり、400℃で十分な効
果が現われたことを示している。したがって、この実施
例では少なくとも350℃で10分以上加熱しなくては、本
発明の効果が得られないことが分かる。Second Embodiment Next, the effect of heating the thin film wiring will be described. FIG. 4 shows the case where Al-1% Si-0.3% Mg is used as a good conductive alloy and W-10% Ti is used as a high melting point material.
The change in electric resistance of the sample heated for a minute and the sample heated at 400 ° C. for 30 minutes with the energization time is shown. This figure shows that heating at 300 ° C. is insufficient in this case, and that a sufficient effect has been achieved at 400 ° C. Therefore, in this example, it is understood that the effect of the present invention cannot be obtained unless heating is performed at 350 ° C. for at least 10 minutes.
（実施例３） 次に、Al合金中にMg等以外の、従来よりAl配線自身の
耐エレクトロマイグレーション性を向上するために添加
されていた元素、例えばCu,Pd,Ti,Hf等を添加した場合
について述べる。Example 3 Next, elements other than Mg and the like, which have been conventionally added to improve the electromigration resistance of the Al wiring itself, such as Cu, Pd, Ti, and Hf, were added to the Al alloy. The case will be described.
第５図に、高融点物質としてＷ−10％Tiを、良導電性
合金としてAl−１％Si−0.3％Mg−0.3％Pdを用いた場合
の、電流密度５×106A/cm2で通電したときの通電時間に
よる電気抵抗変化のグラフを、従来より用いられてきた
Al−１％Si−0.3％Pdと比較して記載する。この図よ
り、Al−１％Si−0.3％Pdでも電気抵抗の上昇は、ある
程度抑えられるが、0.3％のMgを添加すると、さらに電
気抵抗上昇を抑えられる事がわかる。FIG. 5 shows a current density of 5 × 10 6 A / cm 2 when W-10% Ti is used as the high melting point material and Al-1% Si-0.3% Mg-0.3% Pd is used as the good conductive alloy. The graph of the change in electrical resistance with the energization time when energized at
It is described in comparison with Al-1% Si-0.3% Pd. From this figure, it can be seen that the increase in electric resistance can be suppressed to some extent even with Al-1% Si-0.3% Pd, but the increase in electric resistance can be further suppressed by adding 0.3% Mg.
このように、Al合金自身の耐エレクトロマイグレーシ
ョン性を向上する元素を添加し、さらに本発明の、高融
点物質と良導電性合金の密着性を向上させる元素を添加
すると、これらの相乗効果により、さらに電気抵抗上昇
が抑えられる。As described above, by adding an element that improves the electromigration resistance of the Al alloy itself, and further adding an element that improves the adhesion between the high melting point material and the good conductive alloy of the present invention, a synergistic effect of these elements allows Further, an increase in electric resistance is suppressed.
（実施例４） 以上は、良導電性合金としてAl合金を用いた場合の実
施例について述べたが他のCu,Ag,Au基合金を用いてもよ
い。次にAl合金以外のCu合金を用いた場合の実施例につ
いて述べる。(Embodiment 4) The embodiment in which the Al alloy is used as the good conductive alloy has been described above, but other Cu, Ag, and Au-based alloys may be used. Next, an example in which a Cu alloy other than the Al alloy is used will be described.
高融点物質としてMo,良導電性合金としてCu−１％Al
合金を用いた場合の実施例を、良導電性合金として純Cu
を用いた場合と比較して第６図に示す。同図は、１×10
7A/cm2の電流密度で150℃において通電した場合の電気
抵抗変化を示している。この図のように、Cu単体では、
電気抵抗が上昇するが、Cu−１％Alを用いると、ほとん
ど電気抵抗は上昇しない。このように本発明は、Al以外
のCu,Au,Ag等をベースにした配線にも用いることができ
る。Mo as high melting point material, Cu-1% Al as good conductive alloy
In the case of using an alloy, the pure conductive Cu is used as a good conductive alloy.
FIG. 6 shows a comparison with the case of using. The figure shows 1 × 10
It shows a change in electric resistance when current is applied at 150 ° C. at a current density of 7 A / cm 2 . As shown in this figure, Cu alone
Although the electric resistance increases, the electric resistance hardly increases when Cu-1% Al is used. Thus, the present invention can be used for wiring based on Cu, Au, Ag, etc. other than Al.
第７図は本発明に係る半導体装置の断面図を示す。図
において10はセラミックからなるベース部材、11はLSI
チップ、12は他部材と電気的接続を図るための接続ピ
ン、13は薄膜配線、14はリード線、15はキャップ状の封
止部材、16はガラス又はゴム封止材、17はろう材を示
す。この半導体装置の薄膜配線13は前記した高融点物質
層と良導電性合金層とが直線接触して一体化されている
薄膜配線で形成されている。これにより、半導体装置全
体の信頼性が向上する。FIG. 7 is a sectional view of a semiconductor device according to the present invention. In the figure, 10 is a base member made of ceramic, and 11 is an LSI.
Chip, 12 is a connection pin for electrical connection with other members, 13 is a thin film wiring, 14 is a lead wire, 15 is a cap-shaped sealing member, 16 is a glass or rubber sealing material, and 17 is a brazing material. Show. The thin film wiring 13 of this semiconductor device is formed by a thin film wiring in which the high melting point material layer and the good conductive alloy layer are linearly contacted and integrated. Thereby, the reliability of the entire semiconductor device is improved.
本発明によれば、高融点物質と良導電性合金の密着性
を向上することができるので、エレクトロマイグレーシ
ョンによる薄膜配線の電気抵抗上昇を抑制することがで
きる。この効果により、微細配線パターンを有する半導
体装置の信頼性を向上することができる。ADVANTAGE OF THE INVENTION According to this invention, since the adhesiveness of a high melting point substance and a good conductive alloy can be improved, the electrical resistance rise of the thin film wiring by electromigration can be suppressed. With this effect, the reliability of a semiconductor device having a fine wiring pattern can be improved.
第１図は本発明の実施例の断面図、第２図は本発明の一
実施例の電気抵抗の通電時間による変化を公知例として
比較した図、第３図は第２図の試料を表面から観察した
図、第４図は焼鈍の効果について第２図と同様に示した
図、第５図は添加元素の効果について示した図、第６図
はCu基合金の実施例について示した図、第７図は本発明
に係る半導体装置の断面図を示す。 １……シリコンウエハー、２……拡散層、 ３……熱酸化SiO2膜、４……高融点物質層、 ５……良導電性合金層、６……コンタクトホール、 ７……パッシベーション膜、13……薄膜配線。FIG. 1 is a cross-sectional view of an embodiment of the present invention, FIG. 2 is a diagram comparing changes in electric resistance according to an energizing time of one embodiment of the present invention as a known example, and FIG. , FIG. 4 shows the effect of annealing in the same manner as FIG. 2, FIG. 5 shows the effect of the added element, and FIG. 6 shows the example of the Cu-based alloy. FIG. 7 is a sectional view of a semiconductor device according to the present invention. 1 ...... silicon wafer, 2 ...... diffusion layer, 3 ...... thermal oxide SiO 2 film, 4 ...... refractory material layer, 5 ...... highly conductive alloy layer, 6 ...... contact hole, 7 ...... passivation film, 13 ... Thin film wiring.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 塩田 勝彦 茨城県日立市久慈町4026番地 株式会社 日立製作所日立研究所内 (72)発明者 深田 晋一 茨城県日立市久慈町4026番地 株式会社 日立製作所日立研究所内 (72)発明者 二瓶 正恭 茨城県日立市久慈町4026番地 株式会社 日立製作所日立研究所内 (72)発明者 宮崎 邦夫 茨城県日立市久慈町4026番地 株式会社 日立製作所日立研究所内 (56)参考文献 特開 昭51−147290（ＪＰ，Ａ) 特開 昭62−32610（ＪＰ，Ａ) 特開 昭62−190850（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/3205 H01L 21/3213 H01L 21/768 ──────────────────────────────────────────────────の Continued on the front page (72) Katsuhiko Shioda, Inventor 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratories (72) Inventor Shinichi Fukada 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi Research, Ltd. In-house (72) Inventor Masayasu Nihei 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Laboratory (72) Inventor Kunio Miyazaki 4026 Kuji-machi, Hitachi City, Ibaraki Prefecture In-house Hitachi Research Laboratory, Hitachi Ltd. (56) References JP-A-51-147290 (JP, A) JP-A-62-32610 (JP, A) JP-A-62-190850 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768
Claims (5)
高融点物質層と、Mg,Ca,Be,Na,Kの少なくとも１種類を
0.1％以上含んでいるAl合金から成る良導電性合金層と
が直接接触して一体化されている薄膜配線。1. A high melting point material layer containing Ti at 0.1% or more and having a melting point of 1800K or more, and at least one of Mg, Ca, Be, Na and K.
Thin-film wiring with direct contact and integration with a highly conductive alloy layer composed of an Al alloy containing 0.1% or more.
Ti,Hf,Zrの少なくとも１種類を0.1％以上含んでいる薄
膜配線。2. The aluminum alloy according to claim 1, further comprising Cu, Pd,
Thin film wiring containing 0.1% or more of at least one of Ti, Hf, and Zr.
Ti合金,TiN,チタンシリサイドのいずれかからなる薄膜
配線。3. The high melting point material layer according to claim 1, wherein the high melting point material layer is Ti, W—
Thin film wiring made of any of Ti alloy, TiN, and titanium silicide.
うちで450℃での酸化物の標準生成自由エネルギーが最
も小さい元素をＭとし、良導電性合金中の0.1％以上含
まれる元素のうちで450℃での酸化物の標準生成自由エ
ネルギーが最も小さい金属元素をＮとすると、 nMOm＋Ｎ→nM＋NOnm （n,mは定数、nmはｎとｍの積、Ｏは酸素原子） の酸化還元反応における450℃での標準自由エネルギー
変化が−100KJ以下であるような元素Ｍ及びＮを各々含
むものである薄膜配線。4. The element having the smallest standard free energy of formation of oxide at 450 ° C. among the elements contained in the high melting point substance of 0.1% or more, and the element contained in the good conductive alloy at 0.1% or more. When N is the metal element having the smallest standard free energy of formation of oxide at 450 ° C., nMO m + N → nM + NO nm (n and m are constants, nm is the product of n and m , and O is an oxygen atom) A thin-film wiring comprising the elements M and N, respectively, such that the standard free energy change at 450 ° C. in the oxidation-reduction reaction is −100 KJ or less.
LSIチップと、該LSIチップ上に設けられた薄膜配線と、
ベース材より突設され他部材と電気的接続をする接続ピ
ンと、この接続ピンと前記LSIチップ上の薄膜配線とを
接続するリード線と、前記LSIチップを封止する封止部
材とを備えた半導体装置において、前記薄膜配線は請求
項１〜４のいずれかのものである半導体装置。5. A base member and a base member disposed on the base member.
An LSI chip, a thin film wiring provided on the LSI chip,
A semiconductor comprising: a connection pin protruding from a base material and electrically connecting to another member; a lead wire connecting the connection pin to a thin film wiring on the LSI chip; and a sealing member for sealing the LSI chip. 5. A semiconductor device according to claim 1, wherein said thin film wiring is any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26997289A JP2936483B2 (en) | 1989-10-17 | 1989-10-17 | Thin film wiring and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26997289A JP2936483B2 (en) | 1989-10-17 | 1989-10-17 | Thin film wiring and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03131031A JPH03131031A (en) | 1991-06-04 |
| JP2936483B2 true JP2936483B2 (en) | 1999-08-23 |
Family
ID=17479792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26997289A Expired - Fee Related JP2936483B2 (en) | 1989-10-17 | 1989-10-17 | Thin film wiring and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2936483B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102152A (en) * | 1991-10-11 | 1993-04-23 | Sony Corp | Semiconductor device |
-
1989
- 1989-10-17 JP JP26997289A patent/JP2936483B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03131031A (en) | 1991-06-04 |
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