JPH0241905B2 - - Google Patents

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Publication number
JPH0241905B2
JPH0241905B2 JP58163916A JP16391683A JPH0241905B2 JP H0241905 B2 JPH0241905 B2 JP H0241905B2 JP 58163916 A JP58163916 A JP 58163916A JP 16391683 A JP16391683 A JP 16391683A JP H0241905 B2 JPH0241905 B2 JP H0241905B2
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JP
Japan
Prior art keywords
film
gold
electrode
electrode pad
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58163916A
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Japanese (ja)
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JPS6054462A (en
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Priority to JP58163916A priority Critical patent/JPS6054462A/en
Publication of JPS6054462A publication Critical patent/JPS6054462A/en
Publication of JPH0241905B2 publication Critical patent/JPH0241905B2/ja
Granted legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置のうち、特に電極構造に関
する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to an electrode structure.

(b) 従来技術と問題点 半導体集積回路（IC）において、トランジス
タ素子のエミツタ電極、ベース電極、コレクタ電
極、ゲート電極、ソース電極、ドレイン電極ある
いはその他の電極とそれらからの配線は、一般に
アルミニウム膜が用いられ、特にワイヤーボンデ
イングするためのボンデイングパツド（電極パツ
ド）部分は殆どすべてアルミニウム膜又はアルミ
ニウム合金膜で形成されている。且つ、電極パツ
ドと半導体容器のリード端子とを接続するための
ボンデイングワイヤーは20〜30μｍφの金線が一
般に用いられる。ボンデイングワイヤーとして
は、その他にアルミニウム線もよく用いられてい
るが、金線の方がボンデイング性が良くて、配線
作業（ネールヘツドボンデイング）も容易である
から、金線が汎用されている現状である。(b) Prior art and problems In semiconductor integrated circuits (ICs), the emitter electrode, base electrode, collector electrode, gate electrode, source electrode, drain electrode, or other electrodes of a transistor element and the wiring from them are generally made of aluminum film. In particular, the bonding pad (electrode pad) portion for wire bonding is almost entirely formed of an aluminum film or an aluminum alloy film. Further, a gold wire having a diameter of 20 to 30 μm is generally used as a bonding wire for connecting the electrode pad and the lead terminal of the semiconductor container. Aluminum wire is also often used as bonding wire, but gold wire has better bonding properties and is easier to wire (nail head bonding), so gold wire is currently in general use. be.

第１図にその電極パツド部の断面図を図示して
おり、１は半導体基板、２はアルミニウム膜（電
極パツド）、３は金線、４は絶縁膜である。 FIG. 1 shows a cross-sectional view of the electrode pad portion, where 1 is a semiconductor substrate, 2 is an aluminum film (electrode pad), 3 is a gold wire, and 4 is an insulating film.

しかしながら、このようにアルミニウム膜と金
線とを接着すれば、長時間使用した場合にパープ
ルプレーク５を起こし、やがては断線に至ること
が知られている。パープルプレーク７とはアルミ
ニウム（Al）と金（Au）とが反応してAuAl2（紫
色の化合物）を生じ、コンタクト抵抗が大きくな
つて破壊することで、断線する場合は電極パツド
全体が紫色に変つた状態となることがあるため
に、パープルプレークと称されている。 However, it is known that if the aluminum film and the gold wire are bonded together in this way, purple flakes 5 will occur when used for a long time, eventually leading to disconnection. Purple plaque 7 is caused by the reaction between aluminum (Al) and gold (Au) to produce AuAl 2 (a purple compound), which increases the contact resistance and causes breakage. If the wire breaks, the entire electrode pad turns purple. It is called purple flake because it can be in an altered state.

一方、このようなパープルプレークを避けるた
め、金膜の電極パツドを考えられるが、金の微細
加工はイオンミリングによるのみであり、量産面
でアルミニウム膜に劣つている。 On the other hand, in order to avoid such purple flakes, electrode pads made of gold film can be considered, but gold can only be microfabricated by ion milling, and is inferior to aluminum film in terms of mass production.

(c) 発明の目的 本発明は、このような問題点を除去し、パープ
ルプレークを発生しない電極構造を有する半導体
装置を提案するものである。(c) Object of the Invention The present invention eliminates such problems and proposes a semiconductor device having an electrode structure that does not generate purple flakes.

(d) 発明の構成 その目的は、アルミニウム又はアルミニウム合
金電極配線上に高融点金属窒化膜又は高融点金属
炭化膜を介して金膜を被覆した電極パツドが設け
られ、該電極パツドの金膜に金線がボンデイング
された構造を有する半導体装置によつて達成され
る。(d) Structure of the Invention The object of the invention is to provide an electrode pad coated with a gold film via a high melting point metal nitride film or a high melting point metal carbide film on an aluminum or aluminum alloy electrode wiring, and to cover the gold film of the electrode pad. This is achieved by a semiconductor device having a structure in which gold wires are bonded.

(e) 発明の実施例 以下、図面を参照して実施例によつて詳細に説
明する。(e) Examples of the invention Hereinafter, examples will be described in detail with reference to the drawings.

第２図は本発明にかかる一実施例の電極パツド
の断面図で、膜厚1.5μｍのアルミニウム膜２の上
に膜厚3000Åの窒化チタン（TiN）膜６を被着
し、更にその上に膜厚3000〜6000Åの金膜７を形
成して、金膜７に金線３をボンデイングしてい
る。TiN膜６、金膜７はいずれもスパツタ法で
被着される。このような電極構造にすれば、
TiN膜がバリヤ層になつてAuとAlとを隔離して
反応することがなくなり、パープルプレークが発
生しない。これはTiN膜６が高融点で、化学的
に安定であるためにAuとAlとを完全に隔離させ
て反応が進行しないためと考えられる。実施テス
トによれば500℃、数時間熱処理してもパープル
プレーク発生の兆しは見られなかつた。 FIG. 2 is a cross-sectional view of an electrode pad according to an embodiment of the present invention, in which a titanium nitride (TiN) film 6 with a thickness of 3000 Å is deposited on an aluminum film 2 with a thickness of 1.5 μm, and A gold film 7 having a thickness of 3000 to 6000 Å is formed, and a gold wire 3 is bonded to the gold film 7. Both the TiN film 6 and the gold film 7 are deposited by sputtering. With this kind of electrode structure,
The TiN film acts as a barrier layer and separates Au and Al, preventing them from reacting and causing no purple flakes. This is thought to be because the TiN film 6 has a high melting point and is chemically stable, completely separating Au and Al and preventing the reaction from proceeding. According to tests conducted, no signs of purple plaque were observed even after heat treatment at 500°C for several hours.

また、第３図は本発明にかかる他の実施例の断
面図で、アルミニウム膜２の上にTiN膜６を被
着し、その上に膜厚3000Åの白金（Pt）膜８を
被着し、更にその上に膜厚3000〜6000Åの金膜７
を形成した電極パツドの例である。白金膜は接着
を良くするために介在させた膜で、このような構
造においても同様にパープルプレークが防止され
ることは勿論である。 FIG. 3 is a cross-sectional view of another embodiment according to the present invention, in which a TiN film 6 is deposited on an aluminum film 2, and a platinum (Pt) film 8 with a thickness of 3000 Å is deposited on top of the TiN film 6. , and then a gold film 7 with a thickness of 3000 to 6000 Å on top of that.
This is an example of an electrode pad formed with . The platinum film is interposed to improve adhesion, and it goes without saying that purple flakes can be similarly prevented in such a structure.

上記の実施例はバリヤ層をTiN膜で形成した
ものであり、TiN膜は融点が高く、化学的に安
定であつて導電性のある膜であるが、炭化チタン
（TiC）膜を使用しても同様のパープルプレーク
抑制の効果が得られ、このTiC膜も高融点で、化
学的に安定で、且つ、導電性を有する膜である。
更に、チタン（Ti）の他にタングステン（Ｗ）、
モリブデン（Mo）、タンタル（Ta）、ハフニウム
（Hf）、ヂルコニウ（Zr）、ニオビウム（Nb）、バ
ナジウム（Ｖ）、クロム（Cr）等の高融点金属の
窒化膜や炭化膜もTiN膜やTiC膜と同様に化学的
に安定で導電性ある性質を有しており、従つて、
これらをバリヤ層としても同様の効果が得られる
ものである。 In the above example, the barrier layer is formed with a TiN film, and the TiN film has a high melting point, is chemically stable, and is conductive. A similar effect of suppressing purple flakes can be obtained, and this TiC film also has a high melting point, is chemically stable, and has electrical conductivity.
Furthermore, in addition to titanium (Ti), tungsten (W),
Nitride and carbide films of high-melting point metals such as molybdenum (Mo), tantalum (Ta), hafnium (Hf), zirconium (Zr), niobium (Nb), vanadium (V), and chromium (Cr) are also used for TiN and TiC films. Like membranes, it has chemically stable and conductive properties, and therefore,
Similar effects can be obtained by using these as a barrier layer.

(f) 発明の効果 以上の説明から明らかなように、本発明によれ
ば金線を配線ワイヤーとした半導体装置において
コンタクト抵抗不良の心配がなくなり、半導体装
置の信頼性を著しく向上することができる。(f) Effects of the Invention As is clear from the above description, according to the present invention, there is no need to worry about contact resistance defects in semiconductor devices using gold wire as wiring wires, and the reliability of the semiconductor devices can be significantly improved. .

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の電極パツド部の断面図、第２図
および第３図は本発明にかかる電極パツド部の断
面図である。 図中、１は半導体基板、２はアルミニウム膜、
３は金線、４は絶縁膜、５はパープルプレーク部
分、６は窒化チタン、７は金膜、８は白金膜を示
している。 FIG. 1 is a sectional view of a conventional electrode pad part, and FIGS. 2 and 3 are sectional views of an electrode pad part according to the present invention. In the figure, 1 is a semiconductor substrate, 2 is an aluminum film,
3 is a gold wire, 4 is an insulating film, 5 is a purple plaque portion, 6 is titanium nitride, 7 is a gold film, and 8 is a platinum film.

Claims (1)

【特許請求の範囲】[Claims] １ アルミニウム又はアルミニウム合金電極上に
高融点金属窒化膜又は高融点金属炭化膜を介して
金膜を被覆した電極パツドが設けられ、該電極パ
ツドの金膜に金線がボンデイングされた構造を有
することを特徴とする半導体装置。1. Having a structure in which an electrode pad is provided on an aluminum or aluminum alloy electrode and coated with a gold film via a high melting point metal nitride film or a high melting point metal carbide film, and a gold wire is bonded to the gold film of the electrode pad. A semiconductor device characterized by:
JP58163916A 1983-09-05 1983-09-05 Semiconductor device Granted JPS6054462A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58163916A JPS6054462A (en) 1983-09-05 1983-09-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58163916A JPS6054462A (en) 1983-09-05 1983-09-05 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6054462A JPS6054462A (en) 1985-03-28
JPH0241905B2 true JPH0241905B2 (en) 1990-09-19

Family

ID=15783256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58163916A Granted JPS6054462A (en) 1983-09-05 1983-09-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6054462A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0262930U (en) * 1988-10-26 1990-05-10
JP5331610B2 (en) 2008-12-03 2013-10-30 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit device
JP6420721B2 (en) * 2014-07-09 2018-11-07 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
CN108093655B (en) * 2016-09-21 2022-03-29 新电元工业株式会社 Semiconductor device with a plurality of semiconductor chips

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192172A (en) * 1975-02-10 1976-08-12 Denkyokuhyomen oo taishokuseihogomaku no keiseihoho
JPS5192179A (en) * 1975-02-10 1976-08-12 Bisaipataanno keiseihoho

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192172A (en) * 1975-02-10 1976-08-12 Denkyokuhyomen oo taishokuseihogomaku no keiseihoho
JPS5192179A (en) * 1975-02-10 1976-08-12 Bisaipataanno keiseihoho

Also Published As

Publication number Publication date
JPS6054462A (en) 1985-03-28

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