JPS62144355A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62144355A JPS62144355A JP28612485A JP28612485A JPS62144355A JP S62144355 A JPS62144355 A JP S62144355A JP 28612485 A JP28612485 A JP 28612485A JP 28612485 A JP28612485 A JP 28612485A JP S62144355 A JPS62144355 A JP S62144355A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- layer
- aluminum
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は超高速電子計算機や高速信号処理回路などに用
いることのできる半導体集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor integrated circuit that can be used in ultra-high-speed electronic computers, high-speed signal processing circuits, and the like.
従来の技術
近年、半導体集積回路はキーデバイスとして使われてい
る。BACKGROUND OF THE INVENTION In recent years, semiconductor integrated circuits have been used as key devices.
以下、図面を参照しながら上述したような従来の半導体
集積回路を化合物半導体集積回路を仮りにして説明する
。Hereinafter, a conventional semiconductor integrated circuit as described above will be explained using a compound semiconductor integrated circuit with reference to the drawings.
第2図は従来の砒化ガリウム集積回路の購遣t1h面図
を示すものである。第2図において、1は集積回路が形
成される半絶縁性砒化ガリウム基板である。2は電界効
果トランジスタやダイオードなど集積回路を構成する素
子の電極で金もしくは金糸合金から成っている。3は絶
縁膜で電極2と上;・Δ配線1jη4とを電気的に絶縁
している。4は個々の電極を電気的に接続するアルミニ
ウム・配線層である。FIG. 2 shows a purchase t1h side view of a conventional gallium arsenide integrated circuit. In FIG. 2, 1 is a semi-insulating gallium arsenide substrate on which an integrated circuit is formed. Reference numeral 2 denotes an electrode of an element constituting an integrated circuit such as a field effect transistor or a diode, and is made of gold or gold thread alloy. 3 is an insulating film that electrically insulates the electrode 2 and the upper wire 1jη4. 4 is an aluminum wiring layer that electrically connects the individual electrodes.
発明が解決しようとする問題点
上記のように構成された集積回路では金もしくは金糸合
金からなる電(j2とアルミニウムからなる配線層4と
が絶縁膜3に設けられた開孔部において直接接触してい
るため、長時間の高温放置によって容易に金とアルミニ
ウムの合金が形成される。よく知られているようにこの
金とアルミニウムの合金は非常にもろく電極と配線層と
の接触抵抗の増大をまねき最後には素子の動作を停止せ
しめるという欠点を有していた。Problems to be Solved by the Invention In the integrated circuit configured as described above, the wiring layer 4 made of aluminum and the wiring layer 4 made of gold or gold thread alloy are in direct contact at the opening provided in the insulating film 3. Therefore, an alloy of gold and aluminum is easily formed when left at high temperatures for a long time.As is well known, this alloy of gold and aluminum is extremely brittle and increases the contact resistance between the electrode and the wiring layer. This has the disadvantage that the operation of the device is eventually stopped.
本発明は上記欠点に鑑み、金とアルミニウムの合金化を
防止しは・1γ11姓の高い配線層(iを有する導体集
積回路を提供するものである。In view of the above-mentioned drawbacks, the present invention provides a conductor integrated circuit which prevents alloying of gold and aluminum and has a high wiring layer (i) of 1.gamma.11.
問題点を解決するための手段
上記問題点を解決するために、本発明の半導体集積回路
は、電極が金もしくは金糸合金、配線層がタングステン
層とアルミニウム層を含む多層金、l萬膜からそれぞれ
削成され、電極とアルミニウム層の間にタングステン層
が介在する構造からなっている。Means for Solving the Problems In order to solve the above problems, the semiconductor integrated circuit of the present invention has electrodes made of gold or a gold thread alloy, and wiring layers made of a multilayer gold film including a tungsten layer and an aluminum layer. It has a structure in which a tungsten layer is interposed between the electrode and the aluminum layer.
作用
この構成によって、中間に設けられたタングステン層が
金およびアルミニウムの拡散を抑制する働きをし、金と
アルミニウムの合金が形成するのを防止することができ
信頼性の高い半導体集積回路が得られることとなる。Function: With this configuration, the tungsten layer provided in the middle acts to suppress the diffusion of gold and aluminum, and prevents the formation of an alloy of gold and aluminum, resulting in a highly reliable semiconductor integrated circuit. That will happen.
実施例
以下、本発明の一実施例について、図面を参照しながら
説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例における化合物半導体集積回
路の配線部分の構造断面図を示すものである。第1図に
おいて、1は比抵抗10’Ωα以上の半絶縁性砒化ガリ
ウム基板、2は金−ゲルマニウム合金、3はシリコン窒
fヒ)漢で以上は第2図と同じ]イ4成である。4は基
板側よりチタン/タングステン/アルミニウムの]頃に
形成された多1俗配線層である。FIG. 1 shows a structural sectional view of a wiring portion of a compound semiconductor integrated circuit according to an embodiment of the present invention. In Figure 1, 1 is a semi-insulating gallium arsenide substrate with a specific resistance of 10'Ωα or more, 2 is a gold-germanium alloy, 3 is silicon nitride, and the above is the same as in Figure 2. . Reference numeral 4 denotes a multi-layer interconnection layer formed from titanium/tungsten/aluminum from the substrate side.
以上のようにI’!成されだ砒化ガリウム集積回路にお
いて電極を形成する金−ゲルマニウム合金と配線層のア
ルミニウムは直接接触しておらず間にタングステン層が
介在しておりこれが金およびアルミニウムの拡散を止め
る役割を果たす。本発明の砒化ガリウム集積回路に25
0°Cの高温保存試験を行なったが200時間以上経過
しても異常は見られず配線層の高信頼性が確認された。As above, I'! In the formed gallium arsenide integrated circuit, the gold-germanium alloy forming the electrode and the aluminum of the wiring layer are not in direct contact with each other, but a tungsten layer is interposed between them, and this serves to stop the diffusion of gold and aluminum. 25 in the gallium arsenide integrated circuit of the present invention.
A high temperature storage test at 0°C was conducted, but no abnormality was observed even after more than 200 hours, confirming the high reliability of the wiring layer.
なお、本実施例では配線層をチタン/タングステン/ア
ルミニウムとしたがチタンは層間絶縁膜と配線層の密着
性をよくするためのもので、チタン以外にクロムなどで
もよい。In this embodiment, the wiring layer is made of titanium/tungsten/aluminum, but titanium is used to improve the adhesion between the interlayer insulating film and the wiring layer, and chromium or the like may be used instead of titanium.
発明の効果
以上のように本発明は、金もしくは金糸合金を電極とし
て用いた半導体集積回路において、配線層に電fl 1
111よりタングステン層、アルミニウム層の頓でこれ
らを含む多層金属層を設けることにより金とアルミニウ
ムの合金反応を防止することができ、高信頼性の半導体
集積回路を得ることができその実用的効果は大なるもの
がある。Effects of the Invention As described above, the present invention provides a semiconductor integrated circuit using gold or a gold thread alloy as an electrode, in which an electric current fl 1
111, by providing a multilayer metal layer containing a tungsten layer and an aluminum layer, it is possible to prevent the alloy reaction between gold and aluminum, and a highly reliable semiconductor integrated circuit can be obtained.The practical effect is that There is something big.
第1図は本発明の一実施例における化合物半導体集積回
路の構造断面図、第2図は従来の化合物半導体集積回路
の構造断面図である。
1・・・・・砒化ガリウム基板、2・・・・・金−ゲル
マニウム合金重囲、4−・・・・・アルミニウム層、5
・・・・・チタン、苦、6・・・タングステンm。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名1−
一砥化M9りに基板
5− チタン1
6−−−タシグヌテン、11
\ム゛
第 2 図FIG. 1 is a structural sectional view of a compound semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a structural sectional view of a conventional compound semiconductor integrated circuit. 1...Gallium arsenide substrate, 2...Gold-germanium alloy overlay, 4-...Aluminum layer, 5
...Titanium, bitter, 6...tungsten m. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
Substrate 5-Titanium 1 6--Titanium 11 \M゛Fig. 2
Claims (1)
記電極側より順にタングステン層とアルミニウム層を含
む多層金属膜からなることを特徴とする半導体集積回路(1) A semiconductor integrated circuit characterized in that the electrode is made of gold or a gold thread alloy, and the wiring layer is made of a multilayer metal film including a tungsten layer and an aluminum layer in this order from the electrode side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28612485A JPS62144355A (en) | 1985-12-19 | 1985-12-19 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28612485A JPS62144355A (en) | 1985-12-19 | 1985-12-19 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62144355A true JPS62144355A (en) | 1987-06-27 |
Family
ID=17700238
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28612485A Pending JPS62144355A (en) | 1985-12-19 | 1985-12-19 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62144355A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02125446A (en) * | 1988-11-02 | 1990-05-14 | Nec Corp | Gold electrode multilayer interconnection structure |
US5416971A (en) * | 1991-07-18 | 1995-05-23 | Hegazi; Gamal M. | Method of assembling a monolithic gallium arsenide phased array using integrated gold post interconnects |
-
1985
- 1985-12-19 JP JP28612485A patent/JPS62144355A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02125446A (en) * | 1988-11-02 | 1990-05-14 | Nec Corp | Gold electrode multilayer interconnection structure |
US5416971A (en) * | 1991-07-18 | 1995-05-23 | Hegazi; Gamal M. | Method of assembling a monolithic gallium arsenide phased array using integrated gold post interconnects |
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