JPH0312740B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a mask memory control circuit in a memory system such as an image processing device, and in particular to a mask memory control circuit that is capable of performing mask processing on both two-dimensional memory and three-dimensional memory data. This invention relates to a general-purpose mask memory control circuit.

[Prior Art] In general image processing, it is often necessary to cut out or delete a part of an image.
For this reason, conventional image processing devices are equipped with a processing memory that stores image data to be processed and a mask memory that stores mask data, and match the image data and mask data read from corresponding locations in both memories. , mask processing was performed by gating image data using mask data.

Furthermore, in general image processing, processing such as overlapping and compositing multiple images or hiding a rear image with a front image is often performed. Therefore, we have installed multiple processing memories as well as functions to perform logical and arithmetic operations such as AND, OR, and EOR between image data.
This makes it possible to perform such image processing at high speed. FIG. 8 shows an example in which such calculations between a plurality of image data and mask processing are combined.

By the way, conventional processing memory is usually either a two-dimensional memory as shown in FIG. 1a or a three-dimensional memory as shown in FIG. 1b, There is nothing that allows one memory to be used in both two-dimensional and three-dimensional modes. Mask processing uses a two-dimensional mask memory, and for two-dimensional processing memory, for example, data read out in bytes is gated in bit correspondence, and for three-dimensional processing memory, data read out is For example, a method of applying a gate to all data in the depth direction of byte length, which is a unit, has been used individually. However, recent image processing devices do not use only two-dimensional memory to develop characters/vectors, but are also desired to store three-dimensional images. In this case, if there is memory that can only be accessed in two dimensions, a place that only handles three-dimensional images will have wasted memory. Therefore, memory that can be used in either two-dimensional or three-dimensional mode has been put into practical use by setting which mode it operates in at the beginning of memory access, but among these, there is a memory that can be used as a mask memory. Memory (this memory can also be used as processing memory depending on settings)
Regardless of whether the processing memory is 2D or 3D,
Since data is stored two-dimensionally, mask processing must be performed for each pixel in the processing memory during operation. As described above, a mask memory control circuit with a simple configuration that can perform mask processing in both two-dimensional and three-dimensional modes has become desirable.

[Object and structure of the invention]

An object of the present invention is to provide a mask memory control circuit that enables mask processing in both modes using a single mask memory in a system in which a processing memory can be used in two dimensional and three dimensional modes. It is about providing.

The configuration of the present invention uses a plane that has a depth of 1 bit and extends in the X direction/Y direction as a unit of access, and by connecting this plane in one or more plane directions, multiple two-dimensional operations can be performed. It has multiple memory modules that perform three-dimensional operation by connecting them in the depth direction.
In addition, in a memory system in which it is set in advance whether each module is accessed as processing memory or as mask memory during calculation, one memory module that functions as mask memory among the plurality of memory modules mentioned above module selector means for selecting read data; means for selecting one bit in the read data of the selected memory module; and when the processing memory is accessed as a two-dimensional memory, the data in the mask memory is When the memory system corresponds as it is and is accessed as a three-dimensional memory, one bit of the mask memory is effective by that amount in the depth direction, and when the memory system operates in the two-dimensional mode, the means for directly selecting the read data output from the module selector means, and when the memory system operates in three-dimensional mode, selecting the bit expansion data output from the bit expansion means and outputting it as mask data; It is characterized by having the following.

[Embodiments of the invention]

The details of the present invention will be explained below with reference to Examples.

FIG. 2 is an overall configuration diagram of an example of a mask processing system to which the present invention is applied. In the figure, 1-1 to 1-n are n memory modules each consisting of eight planes, 2-1 and 2-2 are processing data output units, 3 is a mask data output unit, 4 is a calculation unit, 5 is a write data bus, 6 is an address and control bus, and 7 is data to be masked.

In the two-dimensional mode, each memory module 1-1 to 1-n is read/written in byte units along the plane, and in the three-dimensional mode, it is read/written in units of 1 bit along the plane and 1 byte in the depth direction. It is read/written by .

Each of the memory modules 1-1 to 1-n is used to store either processing data or mask data.

These multiple memory modules are all equal and can each serve as processing memory or mask memory. For example, when performing masked operations on two images, set the same upper address in the registers in the memory module to read the two processing memories and the mask memory at once, and also set the processing memory to one output section. Set a select signal to select image data from one of the
Similarly, a select signal is set on one other output to select image data from another one of the processing memories, and a select signal is set on the mask data output to select image data from the mask memory. Set. By doing so, processing data and mask data can be obtained from each output section at the same time.

Whether each module is allocated for processing data or mask data is dynamically determined depending on the processing content and memory usage status, and is managed by software using, for example, an allocation table. Each module consists of eight planes, and each plane can be expanded into one plane and used as a two-dimensional memory, and the overlapping direction of each of the eight planes can be used as a three-dimensional memory with an 8-bit depth. Can be configured.

In addition, in the embodiment shown in FIG. 2, two output sections for processing data are provided.
This is because it is assumed that calculations will be performed between two images, and at least two output units are required to calculate data from two processing memories for each pixel.

In addition, only one OR gate and one AND gate are shown in the block of the calculation unit 4 in FIG. 2, but this is merely an example for simplifying the explanation, and Any logical function commonly used in inter-image calculations can be provided, and mask calculations can also be used, for example, if the mask data is "1", the OR of two images is performed, and if the mask data is "0"
However, it is also possible to output the AND result of two images.

Next, the operation of the embodiment shown in FIG. 2 will be explained using a specific example shown in FIG.

The calculation unit 4 in the illustrated example executes logical operations A, OR, and B using two processed data (processed data A from the output unit 2-1 and processed data B from the output unit 2-2) as input. , the result is masked data output unit 3
Mask processing is performed using mask data from . In this case, processing data A is a circular figure, processing data B is a triangular figure, and the upper half of the mask data is "1".
The lower half is "0" data. As a result, the masked data 7, as shown in FIG. 8, is obtained by cutting out only the upper half of a combination of a circle and a triangle using a logical sum.

As mentioned above, the calculation function of the calculation unit 4 can be configured as desired depending on the purpose of the inter-image calculation, and as is commonly used in conventional devices, it is possible to configure the calculation function of the calculation unit 4 in advance. It can be prepared and used selectively as needed. However, since the function of this calculation section is not the main focus of the present invention, further explanation will be omitted.

FIG. 3 shows one three-dimensional memory composed of four memory modules.

In the case of a three-dimensional memory, when one plane of one memory module is used as a processing memory, one plane of another memory module becomes a mask plane. Furthermore, when one memory module is expanded two-dimensionally and used, other memory modules are expanded two-dimensionally and become mask planes.

FIG. 4 shows a case where a large two-dimensional memory is constructed by expanding eight planes of one memory module onto one plane. In this case, the processing memory and mask memory must be planes of the same size. Note that the number of planes used is not limited to eight, and may be any number as long as use is permitted. For example, with only one plane,
Alternatively, it is also possible to configure one plane by all the planes of a plurality of memory modules.

When the processing memory is a three-dimensional memory, just as when the processing memory was two-dimensional, a plane mask memory of the same size was required.
A mask memory is required for each pixel (in the case of a three-dimensional memory, it is a set of several bits including the depth direction; in the case of a two-dimensional memory, it is one bit). At this time, a planar memory is sufficient as the mask memory regardless of whether the processing memory is two-dimensional or three-dimensional. This is because, as shown in FIG. 8, the mask data only needs to be "0" or "1" data.

FIG. 5 shows a case where one memory module is used as a three-dimensional processing memory, and the mask memory includes any one of the other memory modules.
You can guess the number of planes.

Figure 6 shows how four memory modules are combined into one.
This example shows a case in which two three-dimensional processing memories are configured, and a two-dimensional memory obtained by expanding arbitrary four planes in one other memory module is used as the mask memory.

As described above, the memory modules 1-1 to 1-n can be used in different two-dimensional or three-dimensional modes, and the processing memory and mask memory are not fixed in hardware, and the memory modules 1-1 to 1-n can be used in two-dimensional or three-dimensional modes. It is allocated in yule units or plane units as appropriate. Depending on these assignments, the output unit 2-1 or 2-2 selects read data from the processing memory module, and the mask data output unit 3 selects read data from the mask memory module. and applies it to the calculation unit 4 according to the memory mode. The calculation unit 4 performs a logical product of the applied processing data and mask data, masks the processing data, and outputs it on the data 7.

In the two-dimensional mode, the data read from the plane of the mask memory module can be used as mask data as is, but in the three-dimensional mode, the data read from the plane is extended in the depth direction to create the mask data. Must be formatted. The mask data output section 3 is
In these two modes, an adapter function is provided to adapt the format of the read mask data to the processing data.

FIG. 7 shows the detailed configuration of the mask data output section 3, in which 8 is a read data selector of a memory module, 9 is a module selection register, and 10 is a memory module read data selector.
11 is a plane selection register, 12 is an expansion circuit, 13 is a two-dimensional/three-dimensional data selector, and 14 is a mode register.

In two-dimensional mode, it is necessary to select the module of the mask data source, and in three-dimensional mode, it is necessary to select the module and plane. The addresses of the memory module and plane to be selected as the mask data source are set in the module selection register 9 and plane selection register 11, respectively, from a microprocessor MPU (not shown) via the MPU bus. The settings of these registers 9 and 11 are applied to a read data selector 8 and an expansion target bit selector 10, respectively, to select a predetermined module and plane.

Memory 2D/3D mode information is provided by the MPU
It is set in the mode register 14 from the bus, thereby controlling the selection operation of the two-dimensional/three-dimensional data selector 13. In the case of the two-dimensional mode, 1-byte data parallel to the plane output from the read data selector 8 is selected and output to the calculation unit 4 as is. In addition, in the case of three-dimensional mode, one specific bit is selected by the expansion target bit selector 10 from among the 1-byte data extending in the depth direction of the module output from the selector 8, and the value is expanded to 8 bits in parallel. is output to the calculation section 4.

The memory of the memory system targeted by the present invention is a memory that can be handled in either two dimensions or three dimensions, so when the processing memory is two dimensional, the mask memory is also two dimensional, and when the processing memory is three dimensional, the mask memory is also three dimensional. The conventional method is to take the original and mask it with the same dimensions, and this can be done with a simple circuit. However, in the present invention, this is the same when the processing memory is two-dimensional, but when the processing memory is three-dimensional, the mask memory is two-dimensional, and the control circuit uses one bit to avoid wasting the data in the depth direction. Efficient use of memory is achieved by expanding in the depth direction.

In other words, in order to use mask memory efficiently, memory modules allocated as mask memory are always treated as two-dimensional, so if processing memory is allocated as three-dimensional memory, the memory module allocated as mask memory is always treated as two-dimensional. In order to make one bit correspond to one pixel in the processing memory, it is necessary to expand that one bit in the depth direction from 1 bit to 8 bits. Therefore, when the value of the mask data is "1", the data from the mask data output section becomes "11111111". In this manner, in the three-dimensional mode, the bit values on the mask data plane are automatically expanded in the depth direction to generate and output three-dimensional mask data.

〔Effect of the invention〕

As described above, according to the present invention, the mask data output section has a simple configuration, and by being conditioned by the MPU according to the processing memory mode, it can easily take out the mask data corresponding to the memory mode from the mask memory and appropriately output the mask data. The data can be supplied to the calculation unit in a suitable data format.

[Brief explanation of the drawing]

Figures 1a and b are explanatory diagrams of a two-dimensional memory and a three-dimensional memory, respectively, Figure 2 is an overall configuration diagram of an embodiment of the present invention, and Figure 3 is a diagram of a three-dimensional memory that is a combination of four memory modules. Configuration diagram, Figures 4 to 6
The figures are explanatory diagrams of different mask processing examples.
The figure is a circuit diagram of an embodiment of the mask data output section, and FIG. 8 is an explanatory diagram of a specific example of mask processing. In the figure, 1-1 to 1-n are memory modules;
2-1 and 2-2 are processed data output sections, 3 is a mask data output section, 4 is an arithmetic section, 8 is a read data selector, 9 is a module selection register, 10
11 represents an expansion target bit selector, 11 represents a plane selection register, 12 represents an expansion circuit, 13 represents a two-dimensional/three-dimensional data selector, and 14 represents a mode register.

Claims (1)

[Claims] 1. A plane with a depth of 1 bit and an expanse in the X direction/Y direction is used as a unit of access, and by connecting one or more of these planes in the plane direction, two-dimensional operation can be performed. In a memory system that has a plurality of memory modules that perform three-dimensional operations by connecting them in the depth direction, and in which it is set in advance whether each module is accessed as processing memory or mask memory during calculation, the above method is used. module selector means for selecting read data of one memory module functioning as a mask memory among the plurality of memory modules; means for selecting one bit of the read data of the selected memory module; Bit expansion means that when the processing memory is accessed as a two-dimensional memory, the data in the mask memory corresponds as is, and when it is accessed as a three-dimensional memory, one bit of the mask memory is valid by that amount in the depth direction. When the memory system operates in a two-dimensional mode, the read data output from the module selector means is directly selected, and when the memory system operates in a three-dimensional mode, the bit expansion A mask memory control circuit comprising means for selecting bit extension data outputted from the means and outputting it as mask data.