JP2735065B2 - Image processing processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an image processor for synthesizing image data. 2. Description of the Related Art Image data is stored in a memory as bit data.
Stored as a set. Therefore, stored on memory
Combining one image data with another image data
When one image data and another image data are
It is necessary to read in units of
is there. On the other hand, a microprocessor for performing synthesis processing
And other processing units are used to access memory units and
The arithmetic processing unit is a byte unit or a word unit.
The processing of the image data described above is performed by this type of processing device.
To achieve this, the bit address of each bit of the image data must be
Process, such as a microprocessor
The image data is stored between the device and the memory that stores the image data.
Requires a complex circuit to generate the
You. U.S. Patent No.
No. 4,435,792. Further, a memory storing an image is stored in word units.
Which can be accessed in word units
However, only the movement of the image data on the memory,
In reality, no consideration has been given to image synthesis.
You. References to this type of technology include Japanese Unexamined Patent Publication No.
No. 119385. In addition, data is read out in word units, and
There are technologies that try to separate necessary data from within
You. Japanese Patent Application Laid-Open No.
No. 83537. Further, as an apparatus for performing this kind of processing,
One is ADVANCED MICRO D
EVICES Micro Processor A
m29116 and the like. [0007] The present invention has been made in view of the above points.
The purpose of the
Access to the memory storing image data in word units
Access to one image data and another
An image processing program that can be combined with
To get the processor. [0008] In order to achieve the above object, a feature of the present invention is provided.
Is composed of a number of bits, and
Is divided into word units consisting of bits, and
Memory with different addresses assigned to each word
First image data consisting of a set of multiple bits and a plurality of
The second image data consisting of a set of bits is
And the first image data and the second
Is logically synthesized with the image data of
An image processor for storing in the memory,
Stores an arbitrary bit position where the first image data is stored
A first register for storing the second image data.
A second register to store any bit positions
The logical combination of the first image data and the second image data
Third register that stores an arbitrary bit width that is the processing width
Data, the first image data and the second image data
Is the bit position stored in the first and second registers.
From the position, based on the first image data,
Any image data in which the first image data is stored
From the bit position of the third register
The second image data having a desired bit width is sequentially logically synthesized.
A data processing unit and the first register from the memory
The data processing unit based on the contents of the
Logic synthesis processing exceeds the boundary of the segmented word
To determine whether or not the data
By crossing the boundaries of the segmented words
The first image data is stored in the first image data.
The next address of the memory is sequentially generated and the word unit is generated.
Sequentially read from the memory, and from the memory, the second
Based on the contents of the register and the third register, the data
The logic synthesis processing by the data processing unit
The data processing unit to determine whether or not
That the physical synthesis process crosses the boundary of the divided words
Therefore, the second image data is
The next address of the stored memory is sequentially generated and
Read sequentially in word units, sequentially read in word units
Issued the first image data and the second image data
Are sequentially input to the data processing unit, and
Read the first image data from the combined image data
Memory access unit for sequentially storing and storing at said word position
An image processor comprising: According to a preferred embodiment of the present invention, the first
The image data is the composite image data, and the second image data
Is the composite image data. According to a preferred embodiment of the present invention,
The first image data and the second image data are pixel data
It is. With the above configuration, the image data is stored in the memory.
Although access units can be word units,
Logic synthesis of image data on memory
You. Therefore, it is compatible with a processing device such as a microprocessor.
Bits of the image data are stored between the memory and the memory that stores the image data.
This eliminates the need for a complicated circuit for generating the address. In synthesizing images, the first image data
Position of the first image data with respect to the
Is determined in advance as a location to store the image data of
Therefore, storing the combined image data in memory in word units
Operation is easy, and the processing required for storage is unnecessary.
As a result, the image synthesis processing speeds up. Further, according to the above configuration, the first image
First to store any bit position where image data is stored
Register and an arbitrary window in which the second image data is stored.
In addition to a second register for storing the
Synthesis processing of the image data of the second and the second image data
A third register that stores an arbitrary bit width that is a unit
Have. And the memory access part is a memory
Based on the contents of the first and third registers.
The logic synthesis processing by the data processing unit
It is determined whether or not it exceeds the boundary of the word
The boundary of the classified word is obtained by the logic synthesis processing by the processing unit.
By passing the first image data to the first
The next address of the memory in which the image data of
Next, it is generated and read out sequentially in word units. Further notes
The reaccess unit is configured to store the second register and the second
Based on the contents of the three registers, the data processing unit
Whether the logic synthesis processing exceeds the boundary of the divided words
It is determined whether or not the logic synthesis process by the data processing unit is performed.
By crossing the boundary of the segmented word,
Before the second image data is stored in the second image data
Sequentially generate the next address of the memory
Read sequentially. Therefore, the first image data, the second
When reading image data, these image data
If the next address is stored across modes,
Since the memory access unit automatically generates and reads them,
When reading the next word, the next word from an external CPU
Address setting is not required, improving image processing speed.
Can be Also, when reading the next word,
No need to set the next address from an external CPU or the like
Therefore, the burden on the external CPU can be reduced,
The effect is that the processing efficiency of an external CPU can be improved.
You. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image processing as shown in FIG. 1 is taken as an example.
Will be described. In FIG. 1, M1 is a CRT (Cathode
Ray Tube) The image area corresponding to the screen one-to-one, M2 is
A storage area in which image data to be combined is stored, XA,
XB is actual in image area M1 and storage area M2
The processing areas to be image processed, WA0 ~ 2, WB0,1 are examples
For example, a word boundary that divides the bit length into 16-bit units, R
0 to w represent a raster unit, and na and nb are processing areas XA,
The value of the bit shift in each raster R0-m of XB, A0-
n, B0 to n are word addresses in the processing areas XA, XB.
And FC are processing areas X having different bit start values na and nb.
Modif for aligning A and XB internally and performing logical operations
y function. As shown in FIG. 1, the image area M1 and the case
The storage area M2 has a structure conscious of byte or word boundaries.
Build. This is the current operation of microprocessors, etc.
The processing unit is byte or word, so
The data and address are only for byte or word boundaries.
This is because the access method is adopted. But image processing
Is performed, processing areas XA and XB shown in FIG.
Takes a data array ignoring word boundaries. others
To perform image processing between the processing areas XA and XB, use Modif
y The following three processing functions are especially necessary for function FC.
You. (1) Different processing start bit positions na and nb
In order for processing to be possible between rear XA and XB,
However, for example, in a processor that handles word data,
Performs conversion to load data. (2) As described above, the structure of a word boundary is
Data access from memory taken is in word units
Therefore, for example, the data at the address A0 of the processing area XA is
The na bit data is excluded from the processing. Therefore, this
Remove and save na bit data from arithmetic processing
(Mask) function is required. (3) Normal image processing represents pixels
Process on a pixel-by-pixel basis, while this pixel
The unit is expressed as 1 bit per pixel in monochrome display.
In the case of color display, multiple bits per pixel (usually 4 bits)
Bit). Therefore, the operation processing unit can be set to any bit.
And the function of the above (2) is required.
Modify function FC with the above three processing functions
This will be described with reference to FIG. Note that FIG.
It is assumed that data is accessed in units of
In the following description, all word units are assumed. In the figure
SRC (A) and (B) are the software read from the processing area XB.
Register for storing source data, DST (A) and (B) are processed
Store destination data read from area XA
The registers to be stored, MRG (A) and (B) are processing areas XA and XB
The result of the arithmetic processing between the registers SRC (A) and (B)
And the results of the arithmetic processing of registers DST (A) and (B).
This is the register to store. Note that the above-described register SRC
(A), (B) and DST (A), (B) are each two-word data.
Data length. Of these, the registers SRC (A) and (B)
SN indicating each bit address of processing area XA, XB
(= Nb), the following operation is performed using DN (= na). (A) When SN> DN, the value of SN-DN
Only rotate to the left. (B) When SN <DN, the value of DN-SN
Just rotate to the right. (C) Rotate operation when SN = DN
None. As described above, each bit address nb (SN),
Using na (DN), adjust the operation start bit position.
The bit width to be processed is the width of the preset WN.
Data, and saves data that is not subject to processing.
I do. Here, in FIG. 2, the registers DST (A) and (B) are
Star MRG (A) and (B) have different hardware structures
However, there is no effect on operation even with the same register.
The contents of the rotated registers SRC (A) and (B) are
After the calculation processing is completed, the bit position before the calculation processing is automatically again
Restore up to. Next, referring to FIGS.
Image processing between the processing areas XA and XB by the Modify function FC
Details the processing procedure when processing is performed in units of 4 bits, for example.
Will be described. In FIG. 3, S1 is an opening of the processing area XA.
The processing step of setting the start word address A0, S2 is
Processing to set start bit position (address) na to SN
Step S3 is the start word address B0 of the processing area XB
S4 is a processing step for setting the start bit position (add
Less) A processing step of setting nb to SN, S5 is as described above.
Processing flow in the Modify function FC with the modified Modify function
Steps S6 to S9 are processing steps in the processing area XB.
In step S6, a processing step for obtaining the next bit address is performed.
Step S7 is a processing step for setting the next SN.
8 is a processing step of updating the address in word units, S
9 is a processing step for read access to the next word data.
Steps S10 to S14 are processing steps in the processing area XA.
S10 is a processing step for obtaining the next bit address;
S11 is a processing step for setting the next DN, and S12 is a calculation result.
Write the contents of the register MRG (A) where the result is stored
Access processing step, S13 is address in word units.
S14 is a processing step of updating the next word data.
This is a processing step for read access. SB1 and SB2
This is a determination processing step in which the determination processing is performed as follows. (I) Judgment processing in processing step SB1 Next bit address value obtained in processing steps S6 and S7
Is used to determine the presence or absence of a branch. In processing steps S6 and S7
The processing (expression (1)) and the determination method (expression (2)) are shown below. SN = SN + WN (1) Branch processing when SN ≧ (10) Hex (2), that is, the current word in the next arithmetic processing
Whether or not to cross the boundary (read next word data
Access is necessary or unnecessary). (II) Judgment processing in processing step SB2 In processing step SB2, as in (I) above, DN
And in the processing steps S10 and S11
I have. The difference from (I) is that write access (S12) is performed when DN ≧ (10) Hex (3).
In other words, the fact that equation (3) holds holds that the current word boundary
Indicates that the calculation processing in
Write access to the processing area XA
Seth. The operation described so far is actually performed, for example, by processing
Area XA bit start position na (DN) = (A) Hex,
Bit start position of rear XB nb (SN) = (5) Hex
Are shown in FIGS. Note that these series of figures are shown in raster R0.
Only An improvement plan for the above embodiment will be described below.
I do. This is different from the previous embodiment in that (1) the conventional microphone that manages addresses in word units
Processor performs bit-wise arithmetic processing,
An improvement over the point that management / control becomes very complicated
It is. (2) Data of the processing area XA and the processing area XB
Data access timing is different.
It is an improvement of the point that the processing becomes complicated if you try
is there. (3) Target image area M1 and storage area
The data volume of the rear M2 is large, usually 100K to several MByte.
Becomes Therefore, a series of processing flows shown in FIG.
Assuming that the calculation bit width WN is performed in Byte units (8 bits)
Also performs the processing of the order of 10 6.
It is necessary to reduce the number of steps even in one step.
It is an improvement. In view of the above points, the following other embodiments are described.
Has the following features. (1) Management of internal arithmetic processing is basically all
Are managed by bit addresses. (2) For this reason, for example, a conventional word address
To manage bit addresses in addition to addressless adders.
For example, add a new 4-bit bit address adder
I have. (3) In the bit address adder, the current
Adds the current bit address and the bit width to be operated on. (4) The above-mentioned bit address adder and the conventional one
The interface with these word address adders is
This is performed by the carry signal of the bit address adder. (5) The carry signal is used for internal processing management.
In terms of aspects, the current bit management will take effect in the next cycle.
It can be seen as a warning signal that the current word management will be exceeded
Can be. That is, the digit from the bit address adder
Raise signal required for bit operation at next word boundary
For read access from memory to
It becomes a motion signal. (6) On the other hand, as described above,
Address adder and word address adder are hardware
Are logically divided (integrated by carry signal)
Surface). (7) Logically divided as described above
Therefore, if attention is paid only to the bit address adder,
Operates cyclically in code units. Therefore,
The output of the dress adder is always a bit address,
In other words, bit addresses within word boundaries are automatically displayed.
I will do it. (8) The carry signal described so far.
By changing the extraction position of
Bit management can be created. (9) Also, in the bit address adder
Is an arbitrary bit because the bit width to be operated is added independently.
Cut width calculation can be easily changed at any time.
You. Hereinafter, the other embodiments described above will be described with reference to the drawings.
This will be described in detail. In FIG. 7, ADW is a word address, for example.
Memory adder and MIF are memory interface units.
The image area M1 and the storage area M2 described above, and an example
For example, read or write access to word data is performed.
FC is basically the same as the above and has three functions (1)-
(3) and the bit addresses of the processing areas XA and XB described above.
Operation (a) through values SN and DN representing the
The Modify function that performs (b), ADB is, for example, 4-bit
Bit address adder, WNR is the operation bit width
Is a register that stores the value of WN representing
A storage location for the operation start bit position SN in the rear XB.
The register and DNR are the operation start bits in the processing area XA.
Register BR that stores the
Register WNR, SNR, DNR
Bit register, AC is a bit address adder
A carry signal from ADB, MA is a word address adder
For example, an address bus in word units obtained from the ADW,
D is a data bus in word units, for example. Note that this
Address bus MA and data bus D are connected to image area M1 and data bus D.
A bus for accessing the storage area M2 and the BM
Bit register section BR and a bit address adder
It is a bit management unit. Note that, of the bit register BR,
Contents (WN, SN, DN) are in the Modify function FC
Used. First, the bit management which is the point of the present invention
An outline of the operation of the unit BM will be described below. (A) Operation start bit position SN or D
Either SNR or DNR to store N
(B) a register WNR for storing the operation bit width WN
Is added by the (c) bit address adder ADB.
Operation start bit position SN or D for operation processing to be performed
N is obtained, and (d) again in the corresponding register SNR or DNR
Store. As described above, in the bit management unit BM, the operation
Of the bit width WN and the operation start bit position SN or DN.
Calculation, and the next operation start bit position is
We are looking for wear. It should be noted that the normal image synthesizing process is performed in two different ways.
Of the image data in the area to be combined. Follow
Therefore, the calculation start bit position in each area is different
Become. Therefore, the register that stores the operation start bit position
Data must be provided individually (SNR and DNR). here
Then, the register SNR is set to the operation start bit in the processing area XB.
Register DNR and the register DNR
It has a register dedicated to the rear XA operation start bit position.
Therefore, the next operation start bit position in the processing area XA
When the position DN is obtained, the addition result DN is stored in the register
DNR, the next operation start bit of the processing area XB is stored.
When the position SN is obtained, the value S is stored in the register SNR.
N is stored. On the other hand, the register WNR stores the processing area X
Even if A and XB are different, the operation bit width WN has the same value.
Therefore, it is used as a common register. This register WN
R is rewritten until a series of processing is completed or intentionally
Until the same value is maintained. The bit address adder ADB is described above.
, The range of values that can be represented
The boxes are (0) Hex to (F) Hex. That is, the bit add
Output of the adder ADB is always within the word boundary
Represents the bit position in the table. However, Modif
As information on the operation bit width WN required by the y function FC
Are (1) Hex to (F) Hex as actual bit width information, and
In terms of bit position, value (10) Hex that crosses word boundary
Need a range to include. Therefore, the Modify function F
C functions by understanding the operation bit width WN as shown in FIG.
You. As described above, in the bit management unit BM, the word boundary
Bit position (address) in the field (4-bit configuration)
Calculation cyclically, always only bit address
To express. On the other hand, a conventional word-by-word address
The word address adder ADW that updates
Notification of word address update by any means from unit BM
Need. In the following, the word address adder ADW and
Word address between bit address adders ADB
The interface method for updating is described. Wa
The word address adder ADW is in word units as described above.
To update the address by using the interface method
The bit address adder ADB of the bit management unit BM is
Use a method to signal that a word boundary has been crossed. Sand
The carry signal AC from the bit address adder ADB
Was used. However, as described above, the 4-bit configuration
The value that the address adder ADB can represent, and the same four bits
Registers WNR, SNR, and DNR can be expressed
All values are (0) Hex to (F) Hex. Because of this,
Thus, the operation bit width WN and the operation start bit position SN or
Does not necessarily yield carry signal AC in addition to DN.
I can't do that. For example, WN = (F) Hex, SN = (0) Hex
At this time, an operation for one word (as shown in FIG.
Bit operation bit width is specified).
Will cross the current word boundary,
A carry signal indicating that a word boundary is crossed as shown in equation (4).
No signal AC is output. WN + SN = (F) Hex + (0) Hex = (F) Hex (4) Therefore, the bit address adder ADB performs addition processing.
Is performed, be sure to add “1” as in equation (5).
I have to. (WN + 1) + SN = (F) Hex + (1) Hex + (0) Hex = (10) Hex (5) As described above, the carry signal A required by adding “1”
C can be output. Therefore, it is necessary to add this “1”.
It will be essential. The above-mentioned carry signal AC is calculated by the following operation
Position, the bit position crosses the current word boundary.
Can be used as a signal to determine whether
Wear. That is, the digit from the bit address adder ADB
The upstream signal AC is regarded as (1) a warning signal that new data is required.
Can be (2) In addition, using this signal AC,
By updating the address adder ADW, the above (1)
Address for accessing the data of
Will be able to. That is, the bit address adder AD
The carry signal AC from B is processed in the processing area as shown in FIG.
Memory interface unit MIF for XA and XB
Can be used as the access timing. Ma
Register for storing the operation start bit positions SN and DN
Since SNR and DNR exist individually,
(1) and (2) are the respective processing areas XA and XB units
Can function. The embodiment of the present invention described so far is shown in FIG.
The processing flow when applied to the image processing shown in FIG.
Show. In FIG. 10, P1 is an operation start bit position.
Addresses B0 and nb of the processing area XB including the unit nb
(Nb is set to SNR: SN = nb)
Processing step, P2 includes up to the operation start bit position na
The address A0 and na of the processing area XA (na is
Set to DNR: DN = na) processing step,
P3 is a Modify function having the above-described Modify function.
Processing step in function FC, P4 is bit address
Using adder ADB and word address adder ADW
Thus, the next operation start bit position S in the processing area XB
The processing step for finding N, P5 is the same as P4
Find the next operation start bit position SN in area XA
XP1 is a word data from the processing area XB.
Data read access processing step, XP2 processing
Read and write access to the operation result for area XA
XP3 is a word from processing area XA
The processing step for read access to data, PB1
Star R _O Processing to determine the end of a series of processing in units of ~ m
Steps, XB1 and XB2, depend on the presence or absence of the carry signal AC.
Execution of the processing steps XP1, XP2, XP3
This is a processing step for determining. In the processing steps XB1 and XB2 described above,
Performs the following determination processing. (1) The target range of the next arithmetic processing is
Is determined to be within or outside the word boundary. (2) In processing step XB1, the current
Processing step if within word boundary (FIG. 9 Case 1)
XP1 is not executed, and outside the word boundary (FIG. 9 Case2).
If any, the processing area XB requires
Processing step XP1 for read access to
Run. (3) In processing step XB2, the word
If outside the boundary (Case 3 in FIG. 9), processing step XP
2 and XP3 are not executed. However, outside the word boundary (FIG. 9)
In case 4), the processing area XA
Processing steps for read access to the next word data
Execute XP3. (4) Further, in case 4, the following
Processing for write access to processing area XA for reasons
Execute the logical step XP2. That is, the processing area X
A corresponds one-to-one with the CRT screen as described above (FIG. 1).
Included in image area M1, this is the processed data
(Result) Indicates that the area is a write access target area
You. On the other hand, calculation of the processing area XA in the register DNR
The next start position is determined using the DN that manages the start bit position.
As a result, for example, the fact that the current word boundary has been exceeded is 1
Indicates that the processing for the word has been completed. The above processing steps XB1 and XB
The determination in 2 is based on the bit address adder as described above.
This is performed according to the presence or absence of the carry signal AC from the ADB.
Further, this carry signal AC indicates which register DNR or
The four signals shown in FIG.
The cases are easily distinguishable. Therefore, as shown in FIG.
As described above, the determination of the above 4 case is performed, for example, by using the memory interface.
By performing the processing in the chair unit MIF, the processing flow shown in FIG.
Processing step group X composed of steps XB1 and XP1
1 and processing steps XB2, XP2 and XP3.
The processing step group X2 can be deleted. Note that FIG.
P1 to P5 and PB1 are the processing steps shown in FIG.
This is a processing step of performing the same processing as in the above. The operation of the present invention described above will be described with reference to FIGS.
It is shown in FIG. The initial values shown in these figures are
Operation start bit position SN in XB = (5) Hex, word
Address B0, operation start bit in processing area XA
Position DN = (A) Hex, word address is A0, and operation
The case where the cut width WN = (3) Hex is shown. FIG.
FIG. 10 illustrates case 1 and case 3 in FIG.
The figure shows case 4 and the figure 14 shows case 2.
is there. With the above configuration, the following effects can be achieved.
Can be achieved. (1) Conventional word address adder AD
New addition of bit address adder ADB to W
And the operation start bit position SN or DN is different.
Management and control of arithmetic operations between data
You. (2) The bit address adder AD
B carry signal AC of word address adder ADW.
A new signal, plus two separate registers SNR and DN
By providing R, bit-managed internal arithmetic processing
To the processing area XA or XB that is word managed
Data access timing can be individually and easily performed. (3) Bit and word address management
Hardware management for external data access control
This simplifies the processing flow and
Is 1/3 or less compared to the conventional one (see FIGS. 3 and 11).
Therefore, the processing can be speeded up. The embodiment described above has the following
It can be easily realized by hardware. (1) Bit Address Adder ADB (2) Two Registers SNR and DNR The above hardware is, for example, a unit for accessing external data.
If the place is word, 4-bit configuration or access unit
Is a 3-bit configuration if is a byte, and is extremely added
The increase in hardware is small. But this
Software, that is, the effect on processing
As you can see, it is very effective. As is clear from the above description, the present invention
According to, the access unit of the image data is set to the word unit.
Image data in memory,
Logic synthesis of data. Therefore, the micro
A processing device such as a processor and a memory for storing image data;
During the generation of a bit address of the image data complex
No circuit is required. When synthesizing images, the first image data
Position of the first image data with respect to the
Is determined in advance as a location to store the image data of
Therefore, storing the combined image data in memory in word units
Operation is easy, and the processing required for storage is unnecessary.
As a result, the image synthesis processing speeds up. Further, according to the present invention, the first image data
The first register that stores any bit position where
And the arbitrary bit position where the second image data is stored
And a second register for storing the first image data.
Data and the second image data.
A third register for storing an arbitrary bit width is provided.
You. Then, the memory access unit, from the memory,
Based on the contents of the first register and the third register,
The word synthesized by the logic synthesis processing by the data processing unit
The data processing unit determines whether or not the
That the logic synthesis processing
The first image data by the first image data
Sequentially generates the next address of the memory where the data is stored.
Reading is performed sequentially in units of the word. In addition, memory access
The second register and the third register from the memory;
Logic synthesis by the data processing unit based on the data
Determine if processing crosses the boundary of the segmented word
And the logic synthesis processing by the data processing unit
The second image data by crossing the
Data in the memory in which the second image data is stored.
Next address is generated sequentially and read out in word units sequentially
You. Therefore, the first image data, the second image data
When reading image data, these image data
Is stored, the next address is
The next word is automatically generated by the
When reading the next address from the external CPU, etc.
Settings are not required, and image processing speed can be improved.
Wear. When reading the next word, the external CP
Since the setting of the next address from U etc. becomes unnecessary,
The burden on the external CPU etc. can be reduced, and the external CP
There is an effect that the processing efficiency of U etc. can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing image data processing targeted by the present invention. FIG. 2 is a diagram showing one embodiment of the present invention. FIG. 3 is a diagram showing one embodiment of the present invention. FIG. 4 is a diagram showing one embodiment of the present invention. FIG. 5 is a diagram showing one embodiment of the present invention. FIG. 6 is a diagram showing one embodiment of the present invention. FIG. 7 is a diagram showing another embodiment of the present invention. FIG. 8 is a diagram showing another embodiment of the present invention. FIG. 9 is a diagram showing another embodiment of the present invention. FIG. 10 is a diagram showing another embodiment of the present invention. FIG. 11 is a diagram showing another embodiment of the present invention. FIG. 12 is a diagram showing another embodiment of the present invention. FIG. 13 is a view showing another embodiment of the present invention. FIG. 14 is a diagram showing another embodiment of the present invention. [Description of Signs] ADB: Bit address adder WNR: Register SNR for storing operation bit width WN ... Register DNR for storing operation start bit position SN ... Register AC for storing operation start bit position DN: Carry signal

Continuation of front page    (72) Inventor Hiroaki Aozu               292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa               Hitachi, Ltd. Microelectronics               Equipment development laboratory (72) Inventor Kiichiro Urabe               1 Horiyamashita, Hadano-shi, Kanagawa               Inside the Kanagawa Factory                (56) References JP-A-58-99859 (JP, A)                 JP-A-61-9725 (JP, A)                 JP-A-60-54056 (JP, A)                 JP-A-60-172085 (JP, A)

Claims (1)

(57) [Claims] Consists of a number of bits, is divided into word units consisting of predetermined bits, each word that is the segmented
In a memory to which different addresses are assigned , first image data composed of a set of a plurality of bits and second image data composed of a set of a plurality of bits are stored from an arbitrary bit position, and the first image data and the An image processor that logically synthesizes the second image data and stores the synthesized image data in the memory, and a first register that stores an arbitrary bit position where the first image data is stored. A second register that stores an arbitrary bit position where the second image data is stored, and an arbitrary bit width that is a logical synthesis processing width of the first image data and the second image data. A third register for storing the first image data and the second image data from the bit positions stored in the first and second registers; Data with respect to the, to the first image data, from an arbitrary bit position where the first image data is stored sequentially the second image data of the third of the stored arbitrary bit width register a data processing unit for logically combining, from said memory, based-out the contents of said first register and the third register, logic synthesis processing by the data processing unit
Whether the rule exceeds the boundary of the segmented word
And the logic synthesis processing by the data processing unit
The first image data by crossing the
Data in the memory in which the first image data is stored.
Together sequentially generates the next address sequentially read in the word unit, from said memory, based-out the contents of said second register and the third register, by the data processing unit
Whether the logic synthesis processing crosses the boundary of the divided words
Before the logic synthesis processing by the data processing unit is performed.
By crossing the boundaries of the segmented words
The image data of the second image data is stored
The next address of the memory is sequentially generated and sequentially read in the word unit, and the first address sequentially read in the word unit is read out.
Memory access for sequentially inputting the image data and the second image data to the data processing unit, and sequentially storing and storing the combined image data from the data processing unit at the word position where the first image data is read out And an image processor. 2. 2. The image processor according to claim 1, wherein the first image data is image data to be synthesized, and the second image data is image data to be synthesized. 3. 2. The image processor according to claim 1, wherein the first image data and the second image data are pixel data.