JPH03127158A - Common data channel device actuating system in multiprocessor system - Google Patents

Abstract

PURPOSE:To reduce the processing burden of a program by using an actuation origin central processor equipment number received from a common bus and a head command address of a channel program and reading out a channel device control word on a separate storage device of the central processor equipment. CONSTITUTION:When a software of a central processor equipment issues an instruction for writing a head command address (CMA) of a channel program prepared on a separate storage device 102 of the central processor equipment in the corresponding register in a common data channel device 101 at the time of actuating the common data channel device, a common bus control circuit provided on the central processor equipment adds an actuating origin central processor equipment number of the central processor equipment of an actuating origin to the head command address of the channel program and sends it out to a common bus. The common data channel device 101 reads out a channel device control word on the separate storage device by using the received actuating origin central processor equipment number and the head command address of the channel program. In such a way, the CMA setting processing is simplified.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a plurality of (n units) each having an individual storage device IM.
In a multiprocessor system in which a central processing unit CPU, a common data channel device CH, etc. are connected to a common bus, the starting method when the central processing unit CPU starts the common data channel device CH, more specifically, how to start the common data channel device CH. Command address C when starting channel device CH
This relates to the MA writing method. Here, the command address rcMAJ is a channel program prepared on the individual storage device 1M or the common storage device CM on the common bus (1 of the data channel device CH control word CCW).
〉 consisting of a combination of 〉 or more.

As shown in FIG.
When H402 receives activation from central processing unit CPU400, it reads common data channel device CH control word CCW411 prepared on main memory device MM401, and according to its contents, main memory device MM401-10 device 403
This device executes data transfer between i (0≦i≦m-1) independently of the operation of the central processing unit CPU 400, and reports the result to the central processing unit CPU upon completion.

In the present invention, the central processing unit CPU is connected to the data channel device CH.
The "Matsubuto IO method" is used to control the startup of the 310. Rather than using human output-only instructions such as HIO, allocate command write registers and status read registers for common data channel device CH control in the address space, and read and write them using general-purpose load/store instructions or INPUT10UTPUT instructions. The target is methods that control by Matsubuto 1
The 0 method is a well-known technology that has been used in FDP-11 and the like since around 1970.

[Conventional technology]

First, common data channel device CH activation control in a single processor configuration as shown in FIG. 4 will be explained using FIG. 5. In this case, the CMA write method is to write to the CMA dedicated register (CAR) and to write to the SI register.
There are two types of writing to the O order reception register (SIR).

FIG. 5(a) is a sequence diagram when the command address CMA and control start order (SIO order) are written to the command address register CAR and control order register ODR, which are separate registers. Figure (b) shows the SIO reception register SIR exclusively for sro reception.
FIG. 12 is a sequence diagram in the case where a command address CMA is written to the command address CMA. Each case will be briefly explained below.

Explanation of FIG. 5(a): ■) Command address CMA writing: Central processing unit C
The PU 400 writes the command address CMA to the command address register CAR in the common data channel device CH 402 by the load instruction or the 0UTPUT instruction.

2) SIO order writing: vt central processing unit CP
U400 sends an input/output operation start order (SI) to the control order register ODR in the common data channel device CH402.
0 order, 10 device number, etc.). When the common data channel device CH402 detects an access to the control order register ODR, it checks whether the access is correct or not, and sets the result in the activation state register ISR as a condition code CDC.

3) Reading the condition code CDC: Next, the central processing unit CPU400 reads the common data channel device CH.
The contents of the activation state register ISR in 402 are read by executing a store instruction or an INPUT instruction.

4) Condition code CDC reset: When the condition code CDC on the activation status register ISR is correctly read, the central processing unit CPU 400 resets the condition code CDC on the activation status register ISR. In this figure, an example is shown in which the common data channel device CH402 operates so that the condition code CDC is reset by writing arbitrary data to the activation state register ISR. Note that the activation status register I
How to reset sR directly by programming Al110
Condition code
is released, the common data channel device CH uses the received command address CMA information to store the main memory jM.
Access M401 and read the channel device control word CCW.

Explanation of Fig. 5(b): 1) Command address CMA writing (SIO order)
:The central processing unit CPU first issues a load command or 0U
Register S dedicated to SI○ order reception by TPUT command
Write command address CMA to IR. The common data channel device cH detecting this sets the acceptability of the command address CMA in the register ISR as a condition code CDC.

2) Read condition code CDC, reset condition code CDC: Subsequent processing is case (a)
This is the same as 3) and 4).

In Figures 4 and 5, the command address CMA is 0UT.
A PUT or a load instruction writes to the common data channel device CH using the data bus line. For example, if a bus is used in which the number of data signal lines is equal to the number of address signal lines, the command address CMA can be transferred to the common data channel device C by executing an instruction once.
It can be sent to H.

[Problem to be solved by the invention]

However, in a multiprocessor system in which a plurality of central processing units CPU and a common data channel device CH are connected by a common bus and each central processing unit CPU has its own individual storage device IM, the command address
When performing MA writing, the following points arise.

That is, in order for the common data channel device CH to correctly access the channel device control word CCW, the address of the individual storage device IM of the activation source central processing unit CPU must be able to be identified on the common bus. Regarding this, normally the address space of the individual storage device IM is allocated to each central processing unit C.
It is common to all PUs, and a central processing unit CPU identification number is added to it, so that a format of "CPU identification number + IM address" is adopted.

Note that if a common storage WCM exists, the format is "rCM identification number CM-ID+0M address". In a system employing this type of address system, when the central processing unit CPU notifies the common data channel device CH of command address CMA information, it usually does not suffice with one load command or 0UTPUT command. It is the internal bus of the central processing unit CPU or the common data channel device C.
This is because the number of data lines of the H internal bus is usually less than the number of address lines and is not large enough to specify more than the individual memory device IM (+common memory device CM) space.

For example, if there are 32 data lines on the internal bus, the central processing unit CPU identification number is 8b, and the individual storage device IM address space is 32b, the load command or 0UTPUT
The instruction must be executed twice and written to the register in the data channel device CH in two parts as shown in FIG. As a result, ■The common data channel device CH startup sequence of the central processing unit CPU program increases, and the processing load and startup processing time of the program increase. ■On the central processing unit CPU internal bus and the common data channel device CH internal bus. As a matter of course, there are problems such as an increase in the traffic on the bus, which affects other processes using the bus. ■ While the command address CMA is being written in two parts, a command from another central processing unit CPU When the address CMA is written, the central processing unit CPU number and the 32b address are written by different central processing unit CPUs, and the common data channel device CH reads the channel device control word CCW, causing a logical contradiction. Problems may arise, such as the possibility of

An object of the present invention is to provide a common data channel device CH activation method that solves the above-mentioned problems (1), (2), and (2).

[Means to solve the problem]

In order to achieve the above object, the common data channel device startup method of the present invention provides the following features: In a common data channel device activation method in a multiprocessor system configured to be connected to a bus, software of the central processing unit is activated when the common data channel device is activated.
IM> When a command is issued to write the start command address (CMA) of a channel program consisting of a combination of channel device control words (CCW) prepared above to the corresponding register in the common data channel device, the central processing unit (
A common bus control circuit included in the central processing unit (CPU) sets the activation source central processing unit number (caller ID) of the activation source central processing unit in the start command address (CMA) of the channel program received from the central processing unit internal bus. The common data channel device (CH) receives the activation source central processing unit number (CH) from the common bus and sends it to the common bus.
The channel device control word (CCW) on the individual storage device (IM) of the central processing unit is read using the sender ID) and the first command address (CMA) of the channel program.

Further, in the common data channel starting method of the present invention, the software of the central processing unit sets a register corresponding to a first command address (CMA) of the channel program.
Specified in the format of "terminating common data channel device number (terminating ID) + register address in the destination common data channel device", the common bus control circuit included in the destination common data channel device receives the activation from the common bus. It is characterized in that it is replaced with the original central processing unit number (calling ID) and sent to the internal bus of the subordinate common data channel device.

Furthermore, the common data channel device activation scheme of the present invention provides n central processing units (CPs) with individual memory devices (IMs).
In a common data channel device activation method in a multiprocessor system configured by connecting a common memory device (CM) and a common data channel device (CH) to a common bus, the common data channel device has a “common A storage device number (CM-ID) J and a "common storage device (CM)/individual storage device (IM) boundary address" are set, and the software of the central processing unit, when the common data channel device is started, An individual memory (IM) or a common memory (CM) included in the central processing unit
) The first command address (
When issuing a command to write the command address (CMA) to the corresponding register in the common data channel device, the common bus control circuit included in the central processing unit writes the first command address (CMA) of the channel program received from the internal bus of the central processing unit. When the common data channel device reads the channel device control word (CCW), The common storage device (CM
) - Based on the individual memory (IM) boundary address, determine whether the first command address (CMA) of the channel program received from the common bus is on the common memory (CM) or the individual memory (IM), and make this determination. Depending on the result, the first command address (CM
A) is characterized in that either the common storage device number (CM-ID) or the activation source central processing unit number (originating IO) is added to the data and sent to the common bus.

Further, the software of the central processing unit sets the register corresponding to the first command address (CMA) of the channel program to the “terminating common data channel device number (terminating ID
) 10 Register address in the common data channel device", and the common bus control circuit included in the destination common data channel device specifies the destination common data channel device number (destination ID) received from the common bus. It is characterized in that it is replaced with the activation source central processing unit number (caller 10) received from the common bus and sent to the internal bus of the subordinate common data channel device.

[Operation] According to the present invention, when the central processing unit CPU software executes a write command for only the individual storage device IM address (a part of the command address CMA information), the common bus interface control circuit writes data from the central processing unit CPU internal bus. The central processing unit CPt is sent to the received individual storage device IM address.
In order to autonomously add the J identification number (caller ID) and send it to the common bus, the central processing unit CPU program can notify the common data channel device CH of the rcPUi separate number 10 IM address by executing a single command, and as described above. Problems like (2) and (2) can be eliminated. In addition, the common bus interface control circuit in the common data channel device CH is connected to the individual storage device IM.
In order to embed the sender ID in the empty field of the address information of the address write destination register and send it to the internal bus,
There is no need to use the common data channel device CH internal bus twice for sending out the originating ID, and the problem of increased traffic on the common data channel device CH internal bus as in (2) is also eliminated.

Examples will be described below based on the drawings.

〔Example〕

FIG. 1 shows an example of a system configuration to which the present invention is applied. In Figure 1, 1000 to 100n-+ is the central processing unit C
PU, 101 is a common data channel device CH (hereinafter referred to as common channel device), and 102° to 1021%-1 are individual storage devices IMo to IM, -, , connected to central processing units CPU100° to 100n-+, respectively. 103 is a system bus (common bus) connecting a plurality of central processing units CPU and common channel device CH, 104o'=1
04-+ is ■0 device (not necessarily the same type), 105 is the 10 interface bus that connects the common channel device CH and the IO device, and 106 is the common storage device CM (systems with and without CM). system).

The central processing unit CPU100 is composed of a main control unit MPU110, a program memory ROMI 11, a system bus interface control unit 5BIF112, an MPU bus 113, and the like.

The common channel device CHIOI is a local MPU 120,
ROM/RAM section 121, system bus interface control section 122, adapter section ADP123, IO interface bus control section 10BF124, LMPU bus 125
Consists of etc.

FIG. 2 shows a diagram from the common channel device CH to the individual storage device IM.
This is the structure of address information when accessing. Here, as an example, a case is shown in which the CPU identification number is 8 bits and the 1M address is 32 bits.

FIG. 3 shows a configuration example in the case where the boot source CPU number is set to the common channel device CH by hardware when writing the command address CMA in the present invention.

System bus interface control unit 5BIF1 in Figure 3
12, 201, 202, and 203 are registers that latch information on the address modification line, address line, and data line that constitute the main control unit MPU bus inside the central processing unit CPU, respectively, and 204 is assigned to the CPU 100 itself. This is a register that holds an identification number (ie, #0 as the sender ID 11 report), and is a value that is set in advance and does not change during operation.

In addition, the system bus interface control section 5B in FIG.
In the IF 122, 212, 213, and 214 are registers that latch data on the address line, data line, and sending ID line from the system bus 103, respectively, and 215 is an identification number (ID) assigned to the common channel device CH1ot.
216 is a comparator (EOR circuit) that outputs “1” when a match is obtained; 217 is a register that holds information #5);
is a register that holds address information to be output to the internal bus of the common channel device CH under the system bus interface control unit 5BIFI22.

The operation will be explained below.

When the main control unit MPU software on the central processing unit CPU #0 executes an instruction to write the command address CMA, a 32-bit “” is written on the address line of the MPU bus 113.
Called ID (number assigned to CH #5> CAR within 10+ CHs)
(or 5IR) register address, a 1-bit value indicating IO space on the address modification signal line, and 32-bit CMA information (IM or 0
M address) are sent to each register 202 .
201.203. System bus interface IIJ? In the I1 section s B I F 112, these pieces of information are transferred to the common channel device CHIOI side via the system bus 103. At this time, the address qualifier departure/arrival ID information and the information on the address latch 202 are first transferred to the system bus 103. Send using the upper address line twice. Furthermore, the information on the data latch 203 is sent out via the data line. Various methods can be considered for transmitting data on the system bus 103, but this does not particularly apply to the present invention.

When the common channel device CH side receives these on the corresponding register in the system bus interface control unit 5BIF 122, it compares the called ID (#5) on the register 212 with the calling ID (#5) on the register 215. , if they match, the receiver is accepted and flows to the subordinate adapter section ADP123. At this time, the destination ID (#5) replaced with the originating ID (#0) is set on the address output register 217, and this is sent to the adapter unit ADP side.

As described above, the calling ID can be transferred from the activation source central processing unit CPU to the common channel device CH side without making the software aware of it.

Next, the adapter section ADP123 in the common channel device CH
inputs the 8-bit "source IDJ and 32-bit r1M/CM address" from the system bus interface control unit 5BIF122, but there are two register setting methods depending on whether the system has or does not have a common memory CM. (Figures 3-1 and 3-2).

FIG. 3-1 shows a part of the configuration of the intra-CH ADP 123 in the case of a multiprocessor not equipped with a common storage device CM. In Figure 3-1, "the source IDJ is directly set in the source ID register 220, the 32-bit rIM address" is set in the CAR (or 5IR) register 221, and these pieces of information are used to fetch the CCW from then on. .

FIG. 3-2 shows a part of the configuration inside the CH adapter unit ADP 123 in the case of a multiprocessor equipped with a common storage device CM. In Figure 3-2, the adapter part ADP123
The rCM/IM boundary address and the rCM identification number CM-I DJ are registered in advance in registers 230 and 231 in the system bus interface control unit 5BIF1.
22 to■ When entering the M/CM address, CM/IM
The boundary address is compared with the comparator 232, and the individual storage device 1
If it is M area, send the sender ID, and if it is common storage CM area, then CM-
The ID is set in the ID information register 233. Thereafter, this ID information and the address information on the command address register CAR (or 5IR) 234 are used to perform the channel device control word CC pre-fetch process.

The configurations shown in FIGS. 1 and 3 are merely examples, and it goes without saying that any existing configuration may be used as long as it satisfies the gist of the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, in addition to eliminating the conventional problems, the present invention has the following effects.

■Since the software does not need to edit your own CPU number as CMA information, the CMA setting process is simplified.

- Since the software does not need to be conscious of its own CPU number, the startup process on each CPU is made uniform, and CH startup programs can be written without being aware of the fact that it is a multiprocessor.

■It eliminates the problem of incorrect CPU number specification due to software bugs, etc., and improves system reliability.

(2) The common bus control circuit in the CH replaces the destination ID field of the address bus with the origination ID field and sends it to the subordinate, so the origination ID can be efficiently received and used for subsequent CCW fetching.

[Brief explanation of the drawing]

Figure 1 is a diagram of a configuration example of a multiprocessor system to which the present invention is applied, Figure 2 is a diagram of the configuration of address information in the present invention when accessing from CH to IM, and Figure 3 is a diagram of a CMA write in the present invention. In this case, boot source C
Figure 3-1 shows a configuration example when setting the PU number (calling ID) to the CH using hardware.
Figure 3-2 shows the setting of the sender ID and IM address in the P register.
Figure 4 is a diagram showing the general connection configuration of CH. Figure 5 is an example of CH activation control using the Matsubuto method (single (In case of processor configuration) FIG. 6 is an example of CMA writing to CH in the conventional method (in multi-processor configuration). 0°~100. -1...Central processing unit, l...Common data channel device, 2o-102. ,...Individual storage device, 3...System bus, 4゜~104□1...10 devices, 5...IO interface bus, 6...Common storage device, 0...Main memory section , 1...Program memory ROM. 2... System bus interface control unit, 3...
MPU bus, 0... Local MPU, 1... ROM/RAM section, 2... System bus interface control section, 3...
Adapter section, 4... IO interface bus control section, 5... Local MPU bus, 201.202.203, Internal registers, 212.213.214, Internal registers, 216.232... Comparator, 233...IDtf'l information register 204...Central processing unit 5...Common data chain

Claims (1)

[Claims] (1) Common in a multiprocessor system configured by n central processing units (CPUs) each having an individual memory device (IM) and a common data channel device (CH) connected to a common bus. In the data channel device activation method, the software of the central processing unit is configured to activate the individual storage device (I) of the central processing unit when the common data channel device is activated.
M) When issuing an instruction to write the start command address (CMA) of the channel program consisting of the combination of channel device control words (CCW) prepared above to the corresponding register in the common data channel device, the central processing unit (CPU) A common bus control circuit included in the central processing unit inputs the activation source central processing unit number (originating I
D) and sends it to the common bus, and the common data channel device (CH) receives the activation source central processing unit number (caller ID) and the leading command address (CMA) of the channel program from the common bus. A common data channel device startup method in a multiprocessor system, characterized in that the channel device control word (CCW) on an individual memory (IM) of the central processing unit is read using the central processing unit. (2) The software of the central processing unit stores the register corresponding to the first command address (CMA) of the channel program in the format of "terminating common data channel device number (terminating ID) + register address within the destination common data channel device". The common bus control circuit included in the destination common data channel device is specified by
The terminating common data channel installation number (terminating ID) received from the common bus is replaced with the activation source central processing unit number (originating ID) received from the common bus, and sent to the internal bus of the subordinate common data channel device. 2. A common data channel device activation method in a multiprocessor system as claimed in claim 1. (3) In a multiprocessor system configured by n central processing units (CPUs) each having an individual memory device (IM), a common memory device (CM), and a common data channel device (CH) connected to a common bus. In the common data channel device activation method, the common data channel device is provided with a "common storage device number (CM-ID)" and a "common storage device (CM)/individual storage device (IM) boundary address" in advance.
and when the software of the central processing unit starts up the common data channel device, the software of the central processing unit controls the channel device prepared on the individual storage device (IM) or the common storage device (CM) included in the central processing unit. When an instruction is issued to write the first command address (CMA) of a channel program consisting of a combination of words (CCW) to a corresponding register in the common data channel device, the common bus control circuit included in the central processing unit Adding an activation source central processing unit number (caller ID) of the activation source central processing unit to the start command address (CMA) of the channel program received from the processing unit internal bus, and sending it to the common bus; When reading the channel device control word (CCW), the device reads the common memory (CM).
- Based on the individual memory (IM) boundary address, determine whether the first command address (CMA) of the channel program received from the common bus is on the common memory (CM) or the individual memory (IM), and check the determination result. Adding either the common storage device number (CM-ID) or the activation source central processing unit number (originating ID) to the leading command address (CMA) of the channel program in accordance with the above, and transmitting it to the common bus. A common data channel device startup method in a multiprocessor system characterized by: (4) The software of the central processing unit stores the register corresponding to the first command address (CMA) of the channel program in the format of "terminating common data channel device number (terminating ID) + register address within the common data channel device". The common bus control circuit included in the terminating common data channel device converts the terminating common data channel device number (terminating ID) received from the common bus into the activation source central processing unit number (originating ID) received from the common bus. 4. The method for activating a common data channel device in a multiprocessor system according to claim 3, wherein the common data channel device is sent to a bus inside a subordinate common data channel device.