JPH0312465U - - Google Patents
Info
- Publication number
- JPH0312465U JPH0312465U JP7298789U JP7298789U JPH0312465U JP H0312465 U JPH0312465 U JP H0312465U JP 7298789 U JP7298789 U JP 7298789U JP 7298789 U JP7298789 U JP 7298789U JP H0312465 U JPH0312465 U JP H0312465U
- Authority
- JP
- Japan
- Prior art keywords
- layer
- power
- ground
- housing
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Description
第１図は、本考案の多層基板の構成を示す断面
図、第２図は本考案の実施例を示す内層のアース
層または電源層のパターン図、第３図は従来のデ
ジタル基板とアナログ基板のシールド方法の一例
を示す断面図である。
１……４層基板、２……部品層、３……内層（
アース層または電源層）、４……内層（電源層ま
たはアース層）、５……半田層、６……クロツク
信号パターン、７……部品、８……信号パターン
、９……スルーホール、１０……デジタル基板、
１１……アナログ基板、１２……シールド板、１
３……外筐体。
Figure 1 is a cross-sectional view showing the structure of the multilayer board of the present invention, Figure 2 is a pattern diagram of the inner layer ground layer or power layer showing an embodiment of the present invention, and Figure 3 is a conventional digital board and analog board. FIG. 2 is a cross-sectional view showing an example of a shielding method. 1... 4-layer board, 2... component layer, 3... inner layer (
4...Inner layer (power layer or ground layer), 5...Solder layer, 6...Clock signal pattern, 7...Component, 8...Signal pattern, 9...Through hole, 10 ...digital board,
11... Analog board, 12... Shield plate, 1
3...Outer casing.
Claims (1)
アース層および電源層を備え、筐体内に実装され
る多層プリント基板において、前記アース層また
は電源層のいずれかの層の一部に信号用のパター
ンを当該層のパターンで囲むように配設するとと
もに、他の電源層またはアース層を、前記筐体内
に実装される他の基板または電子ユニツトの側に
設けたことを特徴とする多層プリント基板。 In a multilayer printed circuit board that is mounted in a housing and has at least one ground layer and one power layer on the inner layer in addition to a component layer and a solder layer, a part of either the ground layer or the power layer A signal pattern is arranged so as to be surrounded by the pattern of the layer, and another power layer or ground layer is provided on the side of another board or electronic unit mounted in the housing. Multilayer printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7298789U JPH0312465U (en) | 1989-06-23 | 1989-06-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7298789U JPH0312465U (en) | 1989-06-23 | 1989-06-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0312465U true JPH0312465U (en) | 1991-02-07 |
Family
ID=31611416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7298789U Pending JPH0312465U (en) | 1989-06-23 | 1989-06-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0312465U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0381498U (en) * | 1989-12-11 | 1991-08-20 |
-
1989
- 1989-06-23 JP JP7298789U patent/JPH0312465U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0381498U (en) * | 1989-12-11 | 1991-08-20 |