JPH0312448U - - Google Patents
Info
- Publication number
- JPH0312448U JPH0312448U JP7376089U JP7376089U JPH0312448U JP H0312448 U JPH0312448 U JP H0312448U JP 7376089 U JP7376089 U JP 7376089U JP 7376089 U JP7376089 U JP 7376089U JP H0312448 U JPH0312448 U JP H0312448U
- Authority
- JP
- Japan
- Prior art keywords
- island
- semiconductor chip
- lead frame
- fixed
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7376089U JPH0312448U (US07179912-20070220-C00144.png) | 1989-06-22 | 1989-06-22 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7376089U JPH0312448U (US07179912-20070220-C00144.png) | 1989-06-22 | 1989-06-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0312448U true JPH0312448U (US07179912-20070220-C00144.png) | 1991-02-07 |
Family
ID=31612851
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7376089U Pending JPH0312448U (US07179912-20070220-C00144.png) | 1989-06-22 | 1989-06-22 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0312448U (US07179912-20070220-C00144.png) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006196615A (ja) * | 2005-01-12 | 2006-07-27 | Sumitomo Metal Electronics Devices Inc | 半導体素子搭載用基板 |
JP2009049072A (ja) * | 2007-08-15 | 2009-03-05 | Panasonic Corp | リードフレーム、半導体装置、リードフレームの製造方法、および半導体装置の製造方法 |
-
1989
- 1989-06-22 JP JP7376089U patent/JPH0312448U/ja active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006196615A (ja) * | 2005-01-12 | 2006-07-27 | Sumitomo Metal Electronics Devices Inc | 半導体素子搭載用基板 |
JP4523425B2 (ja) * | 2005-01-12 | 2010-08-11 | 株式会社住友金属エレクトロデバイス | 半導体素子搭載用基板 |
JP2009049072A (ja) * | 2007-08-15 | 2009-03-05 | Panasonic Corp | リードフレーム、半導体装置、リードフレームの製造方法、および半導体装置の製造方法 |