JPH03120699A - Logical integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the destruction of the content of EEPROM owing to external noise or the like by containing a first latch circuit, a second latch circuit which sets the inputs of the 1st latch circuit to be the same and whose values to be held become mutually inverted values and an errorneous writing prevention circuit which logically synthesizes the outputs of two latch circuits. CONSTITUTION:The circuit consists of the latch circuit 3a which inputs a signal, the inverse of WR, and outputs the signal to a node (d), the latch circuit 3b which sets the value that an inverter 1 inverts the signal, the inverse of WR, to be the input and outputs the signal to the node (b) and 2 NAND 5 which sets the signals of the output node (c) and the node (d) of the inverter 2 setting the signal of the node (b) to be the input to be the inputs and outputs a control signal, the inverse of WR'. Thus, the control signal of writing/deletion from ROM (EEPROM), etc. to which writing is possible is prevented from coming to be active owing to external noise, noise occurring in an internal part and the fluctuation of a power voltage and the destruction of the content in EEPROM can be prevented.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to logic integrated circuits.

[Conventional technology]

Conventionally, electrically erasable and writable ROM (hereinafter referred to as E
It is important to prevent erroneous writing to EPROMs.

Signal W input through a port etc. as in the example shown in Figure 2
π (for example, a write signal) is taken into latch circuit 0 and circuit 1 at timing φ (read),
It was held and output as Wπ' as an internal control signal.

[Problem to be solved by the invention]

In the case of a normal microcomputer, the above-mentioned conventional logic integrated circuit inputs signals such as writing, erasing, and reading from the port to the EEFROM, and the above-mentioned latch circuit holds and
It accessed and controlled the EEFROM.

At this time, there is a risk that the stored contents may be destroyed due to external noise, internally generated noise, fluctuations in power supply voltage, etc. For example, when Wπ = 1, that is, when writing is prohibited, the stored value changes to Wπ = 0. There was something that happened.

In particular, when the contents of the latch circuit that holds the control signal of the EEFROM changes, the writing or erasing mode is activated, which causes the contents of the EEFROM to be destroyed.

[Means to solve the problem]

The logic integrated circuit of the present invention includes a first latch circuit and a second latch circuit whose inputs are the same and whose values are inverted from each other, and the outputs of the two latch circuits are logically synthesized. It is configured to include an erroneous write prevention circuit.

〔Example〕

FIG. 1 shows an embodiment of the present invention.

The logic integrated circuit includes a latch circuit 3a that inputs a signal Wπ and outputs a signal to a node d, a latch circuit 3b that inputs a value obtained by inverting a signal WR by an inverter 1, and outputs a signal to each node, and a λ node. Inverter 2 inputs the signal of
It is composed of a 2NAND5 which inputs the signals of the output node C and the node d, and outputs the control signal Wπ'.

First, if the latch circuits 3a and 3b have the same configuration as the conventional latch circuit 3c shown in FIG.
0" is input, the latch circuit 3a holds "1" and the latch circuit 3b holds "0", and the signals at nodes C and d become "l" and the output signal Wπ of 2NAND5.
' becomes "0".

Similarly, when "1" is input to Wπ, "0" is held in the latch circuit 3a, "1" is held in the latch circuit 3b, the signals at nodes C and d become "0", and the output signal of 2NAND5 is Set Wπ' to "1".

The operations explained above are shown in Table 1.

Table 1 When the latch circuit 3a holds "0" and the latch circuit 3b holds "1", that is, writing is prohibited, external noise or internally generated noise may cause fluctuations in the power supply voltage. When the latch circuits 3a and 3b are affected by the change, the latch circuits 3a and 3b having the same configuration should change in the direction of becoming the same value.

In this case, the output of the GL signal Wπ' is 2N
The value of AND5 is "1" as shown in Table 2, that is, the state is set to prohibit writing, so there is no write state.

Table 2 [Effects of the Invention] As explained above, the present invention prevents control signals such as writing and erasing of EEFROM from becoming active due to external noise, internally generated noise, fluctuations in power supply voltage, etc. This has the effect of preventing the contents from being destroyed.

10,000 diagram

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional logic integrated circuit. 1.2...Inverter%3&~3C...
・Latch circuit, 5...NAND, 10...
...NOR, 8, 11...Transfer.

Claims (1)

[Claims] It includes a first latch circuit and a second latch circuit in which the inputs of the latch circuit are the same and the values held are mutually inverted values, and includes an erroneous write prevention circuit that logically synthesizes the outputs of the two latch circuits. A logic integrated circuit featuring: