JPH03120125U

JPH03120125U -

Info

Publication number: JPH03120125U
Application number: JP2946690U
Authority: JP
Priority date: 1990-03-22
Filing date: 1990-03-22
Publication date: 1991-12-10

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示す装置の構成
図、第２図は従来の装置を示す構成図である。図において、１はシフトクロツク発生器、３_１〜３_３はフリツプフロツプ、５はクロツク計数回
路、７はフイードバツク論理回路である。図中、
同一符号は同一または相当部分を示す。 FIG. 1 is a block diagram of an apparatus showing an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional apparatus. In the figure, 1 is a shift clock generator, 3 ₁ -3 ₃ is a flip-flop, 5 is a clock counting circuit, and 7 is a feedback logic circuit. In the figure,
The same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

a clock generation circuit that generates a clock signal;
After the first stage, the output of each previous stage is connected to the input of the next stage, and the clock signal of the clock generation circuit is transmitted to the n-stage flip-flops (n is a positive integer) commonly connected to the clock terminal, and the n-stage flip-flops connected to the clock terminal in common. The clock signal is input to a maximum length period sequence generator having a feedback logic circuit having an algorithm for generating a feedback signal to be supplied to the first stage flip-flop by inputting each output signal and performing a linear operation on the input signal. A clock counting circuit for counting the number of clocks is provided, and each time the counting output of the clock counting circuit is inputted, the feedback logic circuit switches among a plurality of primitive polynomials, and the algorithm for generating the feedback signal is switched accordingly. Features a maximum long period sequence generator.