JPH0311937Y2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a variable gain amplifier, and more particularly to a variable gain amplifier with an attenuator function.

BACKGROUND ART A conventional example of a variable gain amplifier device is shown in FIG. This device uses an UP command switch 1, a DOWN command switch 2, and an ATT command to command operations.
A command switch 3 is provided. These switches 1 to 3 are key switches that are turned on only when a key is operated. One end of each of the switches 1 to 3 is grounded, and the other end is supplied with a voltage V _H via a resistor 4, 5 or 6. The other end of each of the switches 1 to 3 serves as a command output end, and a U/D (up/down) counter 7 is connected to the command output ends of the up command switch 1 and the down command switch 2. Further, the logical product of the levels at each command output terminal of the up command switch 1 and the down command switch 2 is determined by the NAND circuit 8. On the other hand, the clock pulse generator 9
The clock pulse output from the AND circuit 10
The AND circuit 10 sends a clock pulse to the clock input terminal CK of the U/D counter 7 only when a high level signal is supplied from the NAND circuit 8.
Relay supply to.

The U/D counter 7 outputs a digital signal representing the counted value of clock pulses, ie a first count signal, from the count output CO. A digital subtracter 12 is connected to the count output terminal CO. The subtracter 12 subtracts a predetermined value from the count value of the counter 7 and outputs a digital signal representing the subtraction result value, that is, a second count signal. The predetermined value is a numerical value expressed by the digital signal supplied from the signal generator 13 to the subtracter 12, and corresponds to the gain of the VCA 21 of 20 dB. In addition, NAND circuit 8
Alternatively, the output terminal of the clock pulse generator 9 may be directly connected to the clock input terminal CK of the U/D counter 7 without providing the AND circuit 10.

Also, the command output terminal of the ATT command switch 3 has a JK
- A flip-flop 14 is connected. Input terminals J and K of flip-flop 14, reset terminal
A voltage V _H is supplied to CL via a resistor 11, so that the flip-flop 14 performs binary operation. Output terminal Q of flip-flop 14
A selection circuit 15 is connected to
Consists of AND circuits 16, 17, an inverter 18, and an OR circuit 19, depending on the level of the output terminal Q
Selectively D/A (digital/analog) one of the output signals of the D counter 7 and the subtracter 12
It is relayed and supplied to the converter 20. That is, the output terminal Q
When the level of U/D counter 7 is low level
The output signal is relayed to the D/A converter 20,
When the level of output terminal Q is high level, subtracter 1
2 output signals are relayed and supplied to the D/A converter 20.

The output signal of the D/A converter 20 is supplied to a VCA (voltage controlled amplifier) 21.

In such a configuration, when the up command switch 1 is turned on, the level of the command output terminal changes to voltage.
From a high level due to V _H to a low level equal to ground potential. Due to this low level, the U/D counter 7 enters the up-counting state and the NAND
The output level of the circuit 8 becomes high level, and a clock pulse is supplied from the clock pulse generator 9 to the U/D counter 7 via the AND circuit 10.
The U/D counter 7 counts up the supplied clock pulses and supplies a digital signal representing the counted value to the selection circuit 15. At this time, if the level supplied from the output terminal Q of the flip-flop 14 to the selection circuit 15 is low level, the digital signal from the U/D counter 7 is supplied to the D/A converter 20 via the selection circuit 15. . D/A converter 2
0 supplies a voltage according to the numerical value represented by the digital signal to the VCA21, and according to the voltage level
This determines the gain of VCA21. U/D counter 7 only during the ON operation period of up command switch 1.
continues to count up, and as the count increases, the output voltage of the D/A converter 20 increases and VCA2 increases.
The gain of 1 increases.

Also, if you turn on the down command switch 2,
Low level signal from down command switch 2 is U/D
Since the signal is supplied to the counter 7, the U/D counter 7 enters a down-counting state. At the same time, a high level signal is supplied from the NAND circuit 8 to the AND circuit 10 in response to the low level signal, so that a clock pulse is supplied to the U/D counter 7 via the AND circuit 10. The U/D counter 7 counts down the clock pulses and outputs a digital signal representing the counted value, and the down counting continues only while the down command switch 2 is turned on. When a digital signal is supplied from the U/D counter 7 to the D/A converter 20 via the selection circuit 15, the D/A converter 20
The output voltage of the VCA 21 decreases, and the gain of the VCA 21 decreases.

Next, when you turn on the ATT command switch 3,
A low level signal is supplied from the ATT command switch 3 to the flip-flop 14, and the flip-flop 1
The level of the output terminal Q of 4 is reversed from low level to high level, and even if the ON operation of the ATT command switch 3 is stopped, the high level is maintained and outputted from the output terminal Q.
In response to this high level, the selection circuit 15 selects the subtracter 12.
The digital signal output from the D/A converter 2
Relay supply to 0. Since the subtracter 12 outputs a digital signal representing a value obtained by subtracting a predetermined value corresponding to the gain of 20 dB of the VCA 21 from the count value of the U/D counter 7, the output voltage of the D/A converter 20 is The voltage is lowered by a predetermined voltage compared to the case where the output digital signal is supplied. Therefore, the gain of the VCA 21 is also reduced by 20 dB, and the attenuator is activated. When the ATT command switch 3 is turned on again, a low level signal is supplied from the ATT command switch 3 to the flip-flop 14, and the level of the output terminal Q of the flip-flop 14 is inverted from high level to low level. Therefore, the selection circuit 15 supplies the digital signal output from the U/D counter 7 to the D/A converter 20, so that the gain of the VCA 21 also increases by 20 dB and returns to its original state, making the attenuator inoperative.

In such a conventional variable gain amplifier, if the up command switch 1 is turned on while the attenuator is operating, the gain of the VCA 21 will increase and may even exceed the gain level immediately before the attenuator starts operating. In this case, even when the attenuator is in operation, it may be impossible for the user to determine from the sound output whether or not the attenuator is in operation. Also a single ATT
The command switch 3 generates an attenuator operation command and an attenuator operation stop command, so even though the attenuator is activated, it is assumed that the attenuator is not activated and attempts to activate the attenuator.
When the ATT command switch 3 was operated, the gain of the VCA 21 was increased due to the command to stop the attenuator operation, and an unexpected loud sound was sometimes output.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a variable gain amplification device that can avoid problems such as outputting a loud sound even if the attenuator is operated erroneously by misunderstanding that the attenuator is not operating.

The variable gain amplification device of the present invention includes a counter means that counts up in response to a gain increase command and counts down in response to a gain decrease command, and outputs a first count signal indicating the count value of the counter means and outputs a first count signal indicating the count value of the counter means and in response to an attenuator operation command. a switching means for stopping the output of the first counting signal and outputting a second counting signal indicating a value obtained by subtracting a predetermined value from the counted value of the counter means; and an amplifying means for obtaining a gain according to the output signal of the switching means. A variable gain amplification device comprising: a switching means that stops outputting the second count signal and outputs the first count signal in response to a gain increase command or a gain decrease command when outputting the second count signal; It is a feature.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIG. 2.

In the variable gain amplifier according to the present invention shown in FIG. 2, the same parts as those in the device shown in FIG. An AND circuit 23 for calculating the product is provided.
The output terminal of the AND circuit 23 is the flip-flop 14
The voltage _VH is supplied only to the input terminals J and K of the flip-flop 14 through the resistor 11. The rest of the structure of the variable gain amplifier according to the present invention is the same as that of the apparatus shown in FIG.

In the variable gain amplifier of the present invention having such a configuration, when the attenuator is in operation, a high level signal is supplied from the output terminal Q of the flip-flop 14 to the selection circuit 15, and the selection circuit 15 supplies the signal to the subtracter 1.
2 output signals are relayed and supplied to the D/A converter 20. When the up command switch 1 is turned on when the attenuator is activated, the level at the command output terminal of the up command switch 1 becomes low level, and the U/D counter 7 counts up clock pulses in accordance with the low level. The operation up to this point is similar to the conventional device shown in FIG.

On the other hand, the output level of the AND circuit 23 is inverted from a high level to a low level in response to a low level signal from the command output terminal of the up command switch 1, and this low level resets the flip-flop 14, and the output terminal Q of the flip-flop 14 is reset. The level becomes low. In response to the low level signal from the output terminal Q of the flip-flop 14, the selection circuit 15 relays and supplies the output signal of the U/D counter 7 to the D/A converter 20.
The relay of the output signal of No. 2 to the D/A converter 20 is stopped. Therefore, the attenuator operating state is released and the VCA is activated in response to the operation of the up command switch 1.
21 gain increases. That is, the attenuator is returned to the inoperative state without turning on the ATT command switch 3.

Further, even if the down command switch 1 is turned on when the attenuator is operating, the attenuator operating state is canceled by the same operation as described above.

The other operations of the variable gain amplifier according to the present invention are the same as those of the apparatus shown in FIG. 1, and therefore will not be described here.

FIG. 3 shows the U/D counter 7, subtracter 12, and signal generator 1 of the variable gain amplifier according to the present invention.
3. The operating procedure of the microcomputer when the flip-flop 14, selection circuit 15, etc. are replaced with a microcomputer is shown in a flow diagram. In this procedure, first, set the volume counter count value VRC to the initial value and set the flag
Initialization is performed by setting F ₁ and F ₂ to "0" (step 51). The flag _F1 is a flag for indicating the attenuator operating state, and the flag _F2 is a flag for indicating that the ATT command switch 3 is turned off after being turned on. Next, the on/off states of the UP command switch 1, the DOWN command switch 2, and the ATT command switch 3 are read based on their respective output levels (step 52). Then, it is determined whether or not the up command switch 1 is on (step 53), and if the up command switch 1 is on,
The count value VRC of the volume counter is counted up by a predetermined value A (step 54). after that,
Flag _F2 is set to “0” (step 55).
Furthermore, the flag _F1 is set to "0" (step 56), the output value VRO is made equal to the count value VRC (step 57), and the output value VRO is newly supplied to the D/A converter 20 (step 58). ). In this way, step 52 is executed again. On the other hand, if the up command switch 1 is off in step 53, it is determined whether the down command switch 2 is on (step 59). Down command switch 2
If is on, the count value of the volume counter
VRC is counted down by a predetermined value A (step 60), and step 55 is executed. If the down command switch 2 is off, it is determined whether the ATT command switch 3 is on (step 6).
1). If ATT command switch 3 is off, the flag
_F2 is set to "0" (step 62) and step 52 is executed. If the ATT command switch 3 is on, it is determined whether the flag _F1 is equal to "1", that is, it is determined whether the attenuator is already in the operating state (step 63).
If F ₁ = 0, it is assumed that the attenuator has been in an inoperative state until now, and flags F ₁ and F ₂ are each set to "1" (step 64), and the count value VRC is set to "1".
A predetermined value B corresponding to 20 dB of the gain of the VCA 21 is subtracted from the subtracted value, and the output value VRO is made equal to the subtraction result value (step 65). Thereafter, step 58 is executed and the attenuator is activated. If F ₁ =1 in step 63, the attenuator is already in operation, so it is determined whether the flag F ₂ is equal to "0", that is, after the ATT command switch 3 is turned on, it is turned off once and then turned on. A determination is made as to whether the
6). If F ₂ = 1, then step 64 is executed.
It is determined that the ATT command switch 3 continues to be in the on state, and step 65 is executed to continue the attenuator operating state. If F ₂ =0, it is assumed that the ATT command switch 3 was once turned off and then turned on again to release the attenuator operating state, and step 56 is executed to bring the attenuator into the inactive state.

Effects of the Invention As described above, in the variable gain amplifier of the present invention, since the attenuator operating state is canceled in response to the gain increase command or gain decrease command, no gain change occurs when the attenuator is operated. Therefore, it is possible to prevent an erroneous operation when the attenuator is activated by misunderstanding that the attenuator is not activated, and therefore it is possible to avoid unexpected loud noises.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional example of a variable gain amplifier, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a flow diagram showing the operation of another embodiment of the present invention. Explanation of the symbols of the main parts, 1... Up command switch, 2... Down command switch, 3... ATT
Command switch, 7...U/D counter, 12...
Subtractor, 13... Signal generator, 15... Selection circuit, 21... VCA.

Claims (1)

[Scope of utility model registration request] counter means for counting up in response to a gain increase command and counting down in response to a gain decrease command; outputting a first count signal indicating a count value of the counter means; outputting the first count signal in response to an attenuator operation command; a variable gain amplification device comprising: switching means for stopping the count value of the counter means and outputting a second count signal indicating a value subtracted by a predetermined value from the count value of the counter means; and an amplification means for obtaining a gain according to the output signal of the switching means. In the apparatus, the switching means stops outputting the second count signal and outputs the first count signal in response to the gain increase command or gain decrease command when outputting the second count signal. Variable gain amplifier with special features.