JPH0311681B2 - - Google Patents

Description

[Detailed description of the invention]

(Technical field) The present invention is an FM demodulation device that uses digital signal processing to suppress DC fluctuations caused by offset in a signal that is demodulated from an analog frequency modulated wave (FM wave) using digital signal processing. Related to automatic DC level control circuit. (Prior Art) FIG. 1 shows a conventional frequency discriminator used for demodulating frequency modulated waves. In FIG. 1, the frequency modulated wave passes through an LC parallel resonant circuit tuned to its center frequency ₀ , and a circuit tuned to a tuning frequency ₁ higher than the center frequency ₀ ;
It is coupled via a mutual inductance M to a circuit tuned to a low tuning frequency ₂ . Since the polarity of each output voltage is reversed by the diode D ₁ D ₂ , the detection characteristic is expressed as the sum of the two, as shown in FIG. 2. Therefore, when a frequency modulated wave higher than the center frequency ₀ is input, a positive voltage is generated, and when a frequency modulated wave lower than the center frequency ₀ is input, a negative voltage is generated, and the frequency modulated wave can be demodulated. When an offset of Δ is added to the center frequency ₀ , the center frequency becomes ₀ + Δ, and as can be seen from FIG. 2, a DC component is generated. Conventionally, to remove DC fluctuations caused by this offset, a capacitor _CO with an impedance of about 100 kΩ was added after the detector at 30 Hz. However, since the demodulator and subsequent baseband processing circuits and audio signal processing circuits undergo digital signal processing, DC fluctuations due to offset cannot be removed by capacitors. (Objective of the Invention) The present invention solves the DC fluctuation based on the offset of the demodulated signal of the frequency modulated wave subjected to digital signal processing.
This is a simple circuit that can be suppressed in a short time, and will be explained in detail below. (Structure of the Invention) FIG. 3 shows a block diagram of an FM demodulator and an automatic DC level control circuit according to a first embodiment of the invention. In Figure 3, the area within the dotted line frame A is
This figure shows an FM demodulator, where 5 is an input terminal to which a frequency modulated wave is input, 6 is a clock terminal to which a clock frequency is input, 7 is a sampling terminal to which a sampling frequency is input, and 8 is a terminal for comparison with a predetermined threshold value. 9 is a reset pulse generator, 10 is a counter A, 11 is a register A, 12 is a register B, 13 is a register C, 14
is an arithmetic circuit, and in this embodiment, a read-only memory is used. 15 is a shift register, and 16 is a differential circuit. The area within the dotted line frame B is the automatic DC level control circuit that is the object of the present invention, and is comprised of the following components. 18 is an adder circuit, 19 is a comparison circuit A, 20 is a comparison circuit C, 21 is an exclusive OR circuit (hereinafter referred to as EX-OR circuit), 22
is an AND circuit, 23 is a counter B, 24 is an OR circuit, 25 is an input terminal for the upper limit value of the demodulated signal, 26 is an input terminal for the lower limit value of the demodulated signal, 27 is an input terminal for the DC value of the demodulated signal, 28 is an inverter , 29 are output terminals. Next, the operation of the embodiment shown in FIG. 3 will be explained. The analog frequency modulated wave is inputted from the input terminal 5 and inputted to the gate circuit. In this gate circuit, the input frequency modulated wave is converted into a rectangular wave. In response to the rising pulse of this rectangular wave, the reset pulse generating circuit 9 generates a reset pulse. This reset pulse causes counter 10 and register B1 to
2 is reset and the counter 10 starts counting from the beginning. That is, the counter 10 receives the clock frequency input from the clock terminal 6 and counts up. Also, at the timing of the clock frequency, the count value of counter 10 is changed to register A.
11. The rectangular pulse output from the gate circuit 8 is sequentially transferred to the register C13, but the rectangular pulse is transferred to the register A
11, and the register A11 is reset at the falling edge of the rectangular pulse, and until it is reset, the count value is stored in the register C as the counter output value at the high level of the rectangular input frequency modulated wave.
13 and is updated and stored. On the other hand, the count value output of the counter 10 is transferred to the register B12 at the timing of the clock frequency, but the sampling frequency is input from the sampling terminal 7 to the set/reset terminal of the register B12, and the register B12 is reset at the rising edge of the sampling frequency. The count value output of the counter 10 is updated and stored in the register B12 until the time is reached. Next, each count value stored in the register C13 and the register B12 at the time of sampling is input to the arithmetic circuit 14, and a predetermined arithmetic operation is performed. Next, the contents of the calculation in the calculation circuit 14 will be explained using FIG. 5. In FIG. 4, (a) is a rectangular input frequency modulated wave converted into a rectangular pulse by the gate circuit 40, and the high level and low level of the rectangular pulse are alternately repeated. (b) shows the instantaneous phase of this rectangular input frequency modulated wave, the vertical axis shows the phase θ(t), and the time t ₀ ,
θ(t)=0or2π at t ₂ and t ₄ , θ(t)=π at time t ₁ and t ₃
It is. Furthermore, time points t ₀ , t ₂ , and t ₄ indicate rising points of the rectangular input frequency modulated wave, and t ₁ and t ₃ indicate falling points of the rectangular input frequency modulated wave. The horizontal direction of each of these waveforms (a) and (b) shows the time axis, and the timings correspond to each other. Time points T ₀ , T ₁ , and T ₂ indicate sampling times. If the center frequency of the frequency modulated wave is sufficiently higher than that of the modulated wave, it is considered that the time (t ₁ - t ₀ ) and the time (t ₂ - _{t 1} ) are approximately equal. Therefore, t ₀ and t ₁
The difference in the instantaneous phase of the input frequency modulated wave at and is π
becomes. That is, the counter 10 from t ₀ to t ₁
The output is 2 ^N ≡π ……(1). Here, N is the number of bits in the counter.
Therefore, the predicted instantaneous phase at sampling time T ₁ is θ(T ₁ )=π/t ₁ −t ₀ (T ₁ −t ₀ ) (2). Also, as at sampling time T ₂ , the rectangular input
When the FM signal is at a high level, the instantaneous phase is calculated using the previous counter output. The relationship is shown in equation (3). θ(T ₁ )=π/t ₃ −t ₂ (T ₂ −t ₄ ) ……(3) In the arithmetic circuit in this embodiment, the calculations of equations (2) and (3) are performed separately in advance. and store the calculation result in read-only memory, and then write (t ₁ − t ₀ ) or (t ₃ −
By setting t ₂ ) as the first address input and (T ₁ - t ₀ ) or (T ₂ - T ₄ ) as the second address input, the operation result output of equations (2) and (3) can be obtained. However, other calculation means may be used. In this way, the arithmetic circuit 14 calculates the instantaneous phase at each sampling point. Next, the input frequency modulated wave is detected using the shift register 15 and the difference circuit 16. First, the input frequency modulated wave is expressed by equation (4),
The rectangular input frequency modulated wave is expressed by equation (5). g _i (t)=A _c cos (2π _c +φ(t)) ……(4) g _i (t)=rect(2π _c +φ(t)) ……(5) φ(t)=ΔF/ _n sin(2π _n t) ...(6) Here, A _c is the amplitude of the input frequency modulated wave, _c is the center frequency of the frequency modulated wave, _n is the frequency of the modulated wave,
ΔF indicates the maximum frequency deviation. Therefore, the instantaneous phase determined by equation (2) becomes θ(kT)=2π _c kT+φ(kT) (7) at time T ₁ =kT (k is any integer). Therefore, the instantaneous phase delayed by n bits by the shift register 15 is θ((k-n)T)=2π _c (k-n)T +φ((k-n)T) (8). The instantaneous phase obtained by equations (7) and (8) is transferred to the differential circuit 1.
If we calculate the difference in 6, we get equation (9). d(kT)=2nπ _c T+nTdφ(t)/dt| _t=kT ...(9) Therefore, equation (9) is obtained by equation (10) using equation (6). d(kT)=2nπ _c T +2nπΔTcos (2π _n kT) (10) As is clear from equation (10), the input frequency modulated wave is demodulated. The demodulated signal obtained here changes DC-like if there is a carrier offset. The FM signal with carrier offset is g _i (t) = A _C cos (2π ( _c + Δ) t + φ (t))
...(11) The detection output at this time is t=kT(T=1/ _s ,k
is an arbitrary integer) is expressed by equation (12). d(kT) = 2nπ [c/s+Δ/s] +2nπΔF/scos2π _n t | _t=kT ...(12) Here, n is the number of delay bits of the shift register, _C is the center frequency of the frequency modulated wave, and _S is the sampling frequency. , Δ is the carrier offset frequency, ΔF is the maximum frequency deviation, and _n modulation signal. From equation (3), if the carrier offset frequency ±Δ changes, the DC component 2nπ [c/s + Δ/s] changes by ±2.
nπΔ/s changes. For example, n = 16 bits, _S = 200kHz,
When Δf=2kHz, it changes by ±2nπΔ/s=±1.005. FIG. 5 shows the results of simulation up to the output of the arithmetic circuit 14 according to the block diagram of FIG. Note that the vertical axis in FIG. 5 represents the output of the arithmetic circuit 14.
It is shown after DA conversion, and the horizontal axis is time. Here, the horizontal axis shows time and the vertical axis shows output. The center frequency of the frequency modulated wave is 455kHz, the counter clock frequency is 25.6MHz, the sampling frequency is 200kHz, and the delay of the system register 312 is
16 bits, modulation frequency is 3kHz, carrier offset frequency Δ is ±2kHz, maximum frequency deviation ΔF is
It is 2.5kHz. Therefore, the center frequency of the frequency modulated wave is 457 kHz at the maximum and 453 kHz at the minimum, and the DC level at that time changes by approximately ±1. This is similar to the result of the previous study. The center frequency of the frequency modulated wave is
From equation (12), the maximum value at 455kHz is 2π(nc/s-m)+2nπΔF/s=3.77(13
) From equation (12), the minimum value is 2π(nc/s−m)+2nπΔF/s=1.27(14
) get. Here, m=36. m is an arbitrary constant for setting the DC center value to take a value between 0 and 2π. Here, the level adjustment value X ₀ of the DC value of the demodulated signal is input from the level adjustment value input terminal 27, and is set in the counter B23 as an initial value. Further, the value obtained by adding the level adjustment value X ₀ to the maximum value 3.77 is inputted from the upper limit value input terminal 25 to the comparator circuit A 19 as the upper limit value (3.77+X ₀ ), and the value obtained by adding the level adjustment value
The value obtained by adding the level adjustment value X ₀ to 1.27 is input from the lower limit value input terminal 26 to the comparison circuit B20 as the lower limit value (1.27+X ₀ ). In this circuit, immediately after the start of operation, the differential circuit 1
The demodulated signal input from 6 is added to the level adjustment value X ₀ initially set in counter B 23 and addition circuit 18
is added. Hereinafter, the sum of the output of the counter and the demodulated signal will be referred to as a corrected demodulated signal. This corrected demodulated signal is output from the output terminal 28. At the same time, the signal is also input to the comparator circuit A19 and the comparator circuit B20, and is compared with the upper limit value and the lower limit value. (a) Now, when a corrected demodulated signal exceeding the upper limit due to the carrier offset is input to each comparison circuit, the comparison outputs of the comparison circuits A19 and 20 become low level. As a result, EX-OR circuit 21
becomes a low level, and the output of the AND circuit 22 becomes a low level. When the output of the EX-OR circuit is low level, the sampling frequency input via the inverter is changed to the OR circuit 24.
It is input as a count pulse to the counter B22 via. In the counter B23, only while the output of the AND circuit 22 is at a low level, the counter B23 starts counting based on the count pulse with the level adjustment value _X0 as an initial value. At this time, the count is counted down by a fixed correction value C from the set value X of the counter B23. This count output is added to the adder circuit 18, and the adder circuit 18
, it is added to the next demodulated signal input from the difference circuit 16, and then a new corrected demodulated signal is output. This process is repeated until the corrected demodulated signal becomes below the upper limit value, during which time the counter B2
3 is sequentially counted down by a fixed correction value C, and the counter output changes. When the corrected demodulated signal becomes below the upper limit value, at that point the comparator circuit A
19 comparison output is high level, comparison circuit B20
The comparison output becomes low level, and the output of EX-OR circuit 21 becomes high level. Therefore, the OR circuit 24 outputs a constant high level and is in a non-pulse output state, the counter B23 does not count, and the counter output is fixed to the value at that point, and the demodulated signal input to the adder circuit from now on is fixed to this value. is added to the calculated counter value and output as a corrected demodulated signal. (b) On the other hand, when the corrected demodulated signal is smaller than the lower limit value, the comparison output of the comparison circuit A19 is at a high level, the comparison output of the comparison circuit B20 is at a high level, and the output of the AND circuit 22 is at a high level.
The output of the EX-OR circuit 21 becomes low level.
As a result, the counter B23 is connected to the inverter 28,
Upon receiving the count pulse of the sampling frequency input via the OR circuit 24, the count B2
The count is increased by a fixed correction value C from the set value X of 3. The count output of this counter B23 is added to the demodulated signal in the adder circuit 18,
It is output as a corrected demodulated signal. This process is repeated until the corrected demodulated signal exceeds the lower limit value. While this process is repeated, the set value X of the counter is repeatedly counted up by a fixed correction value C. (c) Also, when the corrected demodulated signal input to the comparator circuit A19 and the comparator circuit B20 has a value between the upper limit value and the lower limit value, the output of the EX-OR circuit 21 becomes high level and the OR circuit 24 remains constant. When the high-level output is made, a non-pulse output state is entered, and no count pulse is input to the counter B23. Therefore, the counter B23 at this time outputs the counter setting value X itself at that time.This output and the demodulated signal from the difference circuit 16 are added by the adder circuit 18 and output as a corrected demodulated signal. In each operating state shown in (a), (b), and (c) above, the explanation focused on the period immediately after the start of operation, but even during normal operation, the corrected demodulated signal is always compared with its upper and lower limits. If the output level falls outside the range between the upper limit value and the lower limit value, the output level is controlled as in (a) or (b) above. Here, the output relationship of each part is shown in Table 1 below.

[Table] Through the above operations, DC level fluctuations due to carrier offset can be suppressed. In the first embodiment, in FIG.
23 and the adder circuit 18 are directly connected, but a differential circuit is inserted between the counter B23 and the adder circuit 18, and the level adjustment value X0 is input as one input, and the level adjustment value X ₀ is input as the other input. It is also possible to calculate the difference with the output and input it to the adder circuit 18. If this is done, the DC level of the demodulated signal will be the center value of the maximum value and the minimum value (3.77+1.27)/2=2.52, and the demodulated signal will have the same characteristics as F _c =455kHz in FIG. 5. Although the first embodiment uses the comparator circuit A19 and the comparator circuit B20 in FIG. 3, the same operation can be achieved even if a read-only memory is used. (Effects of the Invention) As explained above, according to the present invention, it is possible to suppress DC level fluctuations due to carrier offset using a simple digital signal processing technique. All ICs in the demodulation section can be directly connected via
It becomes possible to

[Brief explanation of drawings]

Fig. 1 is a circuit configuration diagram of a conventional frequency discriminator, Fig. 2 is a detection characteristic diagram of the frequency discriminator, Fig. 3 is a diagram showing the first embodiment of the present invention, and Fig. 4 is a diagram showing the detection characteristics of the frequency discriminator. FIG. 5 is a diagram showing the operating principle of the first embodiment, and FIG. 5 is a diagram showing simulation results of the demodulator of the present invention. 18... Addition circuit, 19... Comparison circuit A, 20
... Comparison circuit B, 21 ... EX-OR circuit, 22
...AND circuit, 23...Counter B, 24...
OR circuit, 28...inverter.

Claims (1)

[Scope of Claims] 1. An adder circuit that adds a demodulated signal of a frequency modulated wave that is input after digital signal processing and an output of a counter to output a corrected demodulated signal F; The first comparison output outputs the first comparison output when F>( _{X 0 +} α) and the second comparison output when F≦(X ₀ +α). A comparison circuit compares the corrected demodulated signal F with a predetermined lower limit value (X ₀ +β), and when F≧(X ₀ +β), the first comparison output is set as F<(X ₀ +β). In the case of , a second comparator circuit outputs a second comparison output, and a value X is stored and the level adjustment value X ₀ is set as the initial value, If it is the first comparison output, it is counted down by a predetermined correction value C from the stored value An automatic DC level control circuit for FM demodulation, comprising: the counter that counts up and outputs a predetermined correction value C;