JPH03116033U - - Google Patents

Info

Publication number
JPH03116033U
JPH03116033U JP1990025560U JP2556090U JPH03116033U JP H03116033 U JPH03116033 U JP H03116033U JP 1990025560 U JP1990025560 U JP 1990025560U JP 2556090 U JP2556090 U JP 2556090U JP H03116033 U JPH03116033 U JP H03116033U
Authority
JP
Japan
Prior art keywords
chip
circuit board
cap
confirming
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990025560U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990025560U priority Critical patent/JPH03116033U/ja
Publication of JPH03116033U publication Critical patent/JPH03116033U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図aは、この考案の一実施例に係る半導体
装置の実装構造を側方より見た図、第1図bは、
同半導体装置の実装構造を上方から見た図、第2
図a、第2図b及び第2図cは、それぞれ順に同
半導体装置の実装構造の実装工程を説明する図、
第3図a及び第3図bは、それぞれ従来の半導体
装置の実装構造を説明する図である。 1……チツプ、1a……パツド、2……バンプ
、3……キヤツプ、3a……脚部、4……シリコ
ンゴム、5……接着剤、6……樹脂、A……配線
パターン、B……回路基板。
FIG. 1a is a side view of the mounting structure of a semiconductor device according to an embodiment of this invention, and FIG. 1b is a
A diagram of the mounting structure of the semiconductor device viewed from above, No. 2
Figure a, Figure 2 b, and Figure 2 c are diagrams illustrating the mounting process of the mounting structure of the semiconductor device, respectively;
FIGS. 3a and 3b are diagrams each illustrating a mounting structure of a conventional semiconductor device. 1... Chip, 1a... Pad, 2... Bump, 3... Cap, 3a... Leg, 4... Silicone rubber, 5... Adhesive, 6... Resin, A... Wiring pattern, B ...Circuit board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 回路基板上に搭載されるチツプと、このチツプ
のパツド上に形成され、前記回路基板上の配線パ
ターンに圧接されるバンプと、前記チツプを覆い
、その脚部が前記回路基板に接着されるキヤツプ
と、このキヤツプに設けられ、前記チツプの背面
を押圧して、前記バンプと配線パターンとの圧接
状態を保持する弾性体と、前記チツプの動作確認
後、このチツプと前記回路基板との間に充填され
る樹脂とよりなる半導体装置の実装構造。
A chip mounted on a circuit board, a bump formed on a pad of this chip and pressed into contact with a wiring pattern on the circuit board, and a cap that covers the chip and whose legs are bonded to the circuit board. Then, after confirming the operation of the chip, an elastic body is provided on the cap and presses the back side of the chip to maintain the pressure contact state between the bump and the wiring pattern, and after confirming the operation of the chip, an elastic body is installed between the chip and the circuit board. A semiconductor device mounting structure consisting of filled resin.
JP1990025560U 1990-03-13 1990-03-13 Pending JPH03116033U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990025560U JPH03116033U (en) 1990-03-13 1990-03-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990025560U JPH03116033U (en) 1990-03-13 1990-03-13

Publications (1)

Publication Number Publication Date
JPH03116033U true JPH03116033U (en) 1991-12-02

Family

ID=31528492

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990025560U Pending JPH03116033U (en) 1990-03-13 1990-03-13

Country Status (1)

Country Link
JP (1) JPH03116033U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01160028A (en) * 1987-12-17 1989-06-22 Matsushita Electric Ind Co Ltd Method of connecting electrode
JPH01192125A (en) * 1988-01-27 1989-08-02 Sharp Corp Mounting structure of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01160028A (en) * 1987-12-17 1989-06-22 Matsushita Electric Ind Co Ltd Method of connecting electrode
JPH01192125A (en) * 1988-01-27 1989-08-02 Sharp Corp Mounting structure of semiconductor device

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