JPH0311436B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for generating test pattern data for testing logic circuits.

Generally, testers for LSI and printed circuit board units require three types of logic patterns. The first pattern is a data pattern consisting of an expected value pattern that compares the logical pattern input to the test object and the output obtained from the input result.
The second pattern is a mask pattern that specifies prohibition of comparison, and the third pattern is an I/O pattern that turns on/off the input pattern driver connected to the bidirectional terminal of the device under test.

Regarding the above three types of pattern generation, for example, if the terminal of the device under test is bidirectional, that is, it can be either input or output, the terminal of the device under test will be in the output state when the I/O pattern and the data pattern change simultaneously. In addition, turn on the test machine driver,
In other words, it becomes an output state, which may have an adverse effect on both, leading to damage to the output circuit element. The state in which both of the above are outputs is due to the response time of the device under test.This is because the test pattern data is divided and operated in two cycles, and the data pattern is changed in the first cycle to output the output terminal of the device under test. This can be prevented by turning off, ie, making it an input terminal, changing the I/O pattern in the next cycle, and switching the tester driver on, ie, making it an output terminal.

Regarding the mask pattern, it is common to change the data pattern multiple times under these conditions for one mask pattern setting to test the logic function of the device under test. As described above, depending on the test conditions, it is not necessary to change the three types of patterns at the same time. However, in order to shorten the test time, it is desirable to change a plurality of patterns simultaneously as long as the test conditions permit.

In actual testing, these patterns are continuous, so it is necessary to switch the pattern to be changed every cycle.

Normally, such pattern generation is performed by storing the three types of patterns described above in separate memories and reading them independently. However, this method has the disadvantage that if any memory overflows, the number of patterns that can be stored is limited, resulting in poor memory usage efficiency.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern generator which solves the above-mentioned problems and is fast and has good memory utilization efficiency.

A feature of the present invention is that in an apparatus for generating test pattern data for a tester for testing logic circuits, three
means for storing two types of test pattern data in the same memory; means for reading and outputting two types of test pattern data stored in said means within one cycle; and means for reading and outputting two types of test pattern data stored in said means in one cycle; The present invention is comprised of a means for reading and outputting one type of test pattern data and a means for switching between the two reading and outputting means, and the purpose is to switch the means for reading and outputting test pattern data in real time as necessary.

A detailed explanation of the present invention will be given below using examples.

FIG. 1 shows an embodiment of the invention.

A clock output terminal 2 and a control output terminal 3 of the microcontrol circuit 1 are input to a clock input terminal 5 and a control input terminal 6 of an address control circuit 4, respectively. Address output terminal 7 of address control circuit 4 enters address terminals 10 and 11 of pattern memory 8 and control memory 9, respectively. control memory 9
A data output terminal 12 of the microcontroller 1 is connected to a data input terminal 13 of the microcontroller 1 . The data output 14 of the pattern memory 8 is a register Ri,
Data input terminals 15 and 1 for RM and RD, respectively
6 and 17. Registers Ri, RM, RD
The output of i/
o pattern data, mask pattern data, and data pattern data. Further, the clock outputs of the microcontroller 1, CLKi, CLKM, and CLKD, are connected to the registers Ri, RM, and RD. The clock output CLOCK1 of microcontrol circuit 1 is connected to registers Ri', RM',
Connected to RD′. The microcontrol circuit 1 analyzes the data read from the control memory 9 and generates a memory addressing control signal and a clock signal for setting pattern data in each register.

Address control circuit 4 determines a memory address in accordance with the control signal sent from microcontrol circuit 1 and clock ADCL. Registers Ri, RM, and RD are connected to clocks CLKi, CLKM, and CLKM, which generate the I/O pattern, mask pattern, and data pattern output from the pattern memory 8 from the microcontroller circuit 1, respectively.
Import by CLKD. Register Ri′, RM′,
RD′ is a timing register for outputting pattern data at the same timing.
CLOCK1 takes in the data stored in registers Ri, RM, and RD and outputs them at the same time.

The data stored in the pattern memory is
Identification information as to whether it corresponds to an o pattern, mask pattern, or data pattern, and switching control information as to whether the memory is accessed once or twice per cycle are stored in a control memory that corresponds one-to-one to the pattern memory. has been done.

Pattern generation is performed by sequentially reading pattern data stored in pattern memory 8. When changing two types of patterns at the same time, this is done by accessing the memory twice during one cycle, and the operation is specified by data stored in the control memory 9.

FIG. 2 shows the memory configuration of the pattern memory 8 and control memory 9. control memory 9
includes identification of patterns and simultaneous changes in patterns;
One bit is defined for each single change control. When bit i is "1", the contents of pattern memory 9 are the I/O pattern, when bit M is "1", the contents of pattern memory are the mask pattern, and when both bits i and M are "0", the contents of pattern memory 9 are the I/O pattern. Indicates that it is a data pattern. Further, when bit C is "1", it indicates that the next pattern following that pattern is also read out within the same clock.

FIG. 3 shows the pattern memory 8 shown in FIG.
A timing chart when reading the contents of the control memory 9 is shown. In FIG. 2, patterns P1, P3, and P5 are data patterns because both bit M and bit i are "0". The contents read from pattern memory 8 are stored in register RD.
The signal is set to , and further outputted via register RD'. Pattern P2 is an I/O pattern, pattern P
4 is a mask pattern which, like the data pattern, is set in registers Ri and RM, respectively, and further outputted via registers Ri' and RM'. A microcontroller circuit 1 is used to store the contents of the memory in the registers RD, Ri, and RM.
The clocks CLKD, CLKi, CLKM output from
is used. In pattern P4, since bit C is "1", pattern P5 is also read within the same period and output at the same time. First, pattern P4 is read out in the first half of the pattern period and set in register RM. Next, pattern 5 is read out and set in register RD. Finally, the contents of registers RD and RM are transferred by clock CLOCK1, and the mask pattern and data pattern are output at the same time.

In the memory configuration shown in FIG. 2, the order of patterns P1 to P5 is data pattern, I/O pattern, data pattern, mask pattern, and data pattern, but the order varies depending on the test object. The number of patterns is also different. Furthermore, although bit C is 1 in pattern P4, it varies depending on the test object as described above.

FIG. 4 shows a circuit diagram of the microcontrol circuit 1. The clock terminal 20 is connected to delay circuits 21 and 22.
Enter AND gate 23 and OR gate 24. The output 25 of the delay circuit 21 is output as CLOCK1. The output of the delay circuit 22 is an AND gate 26,2
Enter 7. Bit C is connected to the other input of AND gate 23 via the other inputs 28, 29 of AND gates 26, 27 and an inverter 30. Bit M enters AND gates 33 and 34 via AND gate 31 and inverter 32. Bit i is connected to the other input of AND gate 34 and inverter 35
inputs to the other inputs of AND gates 33 and 31, respectively. The outputs of AND gates 27 and 23 are connected to inputs 40 and 41 of OR gate 39, respectively. The outputs of AND gates 33, 34, 31 are connected to the inputs of AND gates 36, 37, 38, respectively, and the output of OR gate 39 is input to the other input of AND gates 36, 37, 38. OR gate 24, and gates 36, 37, 38 are
Output as ADCL, CLKD, CLKi, and CLKM, respectively.

Figure 5 shows clocks CLOCK, CLOCK1,
FIG. 3 is a diagram showing the timing of CLOCK2. The delay circuit 21 is a fixed delay A of the clock CLOCK1.
The delay circuit 22 is a delay circuit that generates a fixed delay B of the clock CLOCK2. Bit C
When is 0, AND gate 23, OR gate 39
The clock CLOCK is connected to AND gate 36 through
Enter 37 and 38. The AND gate 36,3
Whether or not 7, 38 outputs the clock CLOCK is determined by bits M, i. When bit M is “1” and bit i is “0”, the AND gate 31
The output of is "1", and the AND gate 38 outputs the clock CLOCK as CLKM. Bit M
is "0" and bit i is "1", the output of the AND gate 34 becomes "1", and the AND gate 37 outputs the clock CLOCK as CLKi.
When bit M and bit i are both "0", the output of AND gate 33 becomes "1", and AND gate 3
6 outputs the clock CLOCK as CLKD.
When bit C is 1, AND gate 23 is turned off and AND gate 27 is turned on. That is, the clock CLOCK2 enters the AND gates 36, 37, and 38 via the OR gate 39. The output condition of the AND gates 36, 37, 38 is the bit C.
It is the same as when is 0, but only the clock is different. That is, clock 2 is output. Regarding the address clock ADCL, when bit C is 0, the output of the AND gate 26 is "0", so the clock
Only CLOCK is output to ADCL. When bit C is 1, clock CLOCK and clock CLOCK2
are output together. That is, two pulses are output during one cycle.

Detailed explanations have been given above using examples of the present invention. As is clear from the above description, the present invention solves the conventional problems, and by using the present invention, it is possible to obtain a pattern generator that is fast and has good memory efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a memory configuration, FIG. 3 is a diagram showing a time chart, FIG. 4 is a circuit diagram of a microcontrol circuit, and FIG. 5 is a clock diagram. FIG. 1...Micro control, 4...Address control, 8, 9...Memory, Ri, RM,
RD, Ri′, RM′, RD′...Register.

Claims (1)

[Scope of Claims] 1. In an apparatus for generating test pattern data consisting of I/O pattern data, mask pattern data, and data pattern data of a tester for testing a logic circuit, /o A first storage means for sequentially storing one piece of data of pattern data, mask pattern data, and data pattern data, and a bit indicating whether the type data of the one piece of data to be stored and the following data are also changed at the same time. a second storage means that is stored in the corresponding first memory and stores it at the same address as the address; address generation means for sequentially generating addresses; and when a clock signal is applied, the address is incremented to read out the one data, the type data and the bit corresponding to the data, and store the one data. At the same time, when the bit indicates that the following data is also changed at the same time,
1. A pattern generator comprising a control means for incrementing an address and reading and outputting subsequent data.