JPS586478A - Pattern generator - Google Patents

Abstract

PURPOSE:To obtain a pattern generator having a high-speed operation and high using efficiency of a memory, by storing three types of test pattern data in the same memory and reading and delivering two types of test pattern data within a cycle. CONSTITUTION:The generation of patterns is carried out by reading out successively the pattern data stored in a pattern memory. The two types of patterns are varied at one time by having two accesses in a cycle, and this operation is designated by the data stored in a control memory. A bit is defined to the control memory to control the discrimination of patterns and the simultaneous change and a single change of patterns respectively. The contents of the pattern memory bits an i/o pattern and a mask pattern when the bit (i) is 1 and when the bit M is 1 respectively. The data pattern is read out when M is 0, and the next pattern is read out with the same clock when the bit C is 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for generating test pattern data for testing logic circuits.

Three types of logic patterns are required for general KLsx and printed board unit testers. The quantity t/ of t$1 is the data turn consisting of nine turns of the expected value, which compares the logic input to the test object with the output obtained from the input result. I lean is a mask pattern or turn that specifies prohibition of comparison, and the third/arm turn is a tlo pattern that turns on/off the input/arm turn driver connected to the bidirectional terminal of the test object.

Regarding the occurrence of the above three types of glossy turns, for example, if the terminals of the device under test are bidirectional, that is, the terminals of the device under test are bidirectional, that is, the output state is 9 when the i10 pattern and the data pattern change at the same time. 11, the driver of the testing machine is also turned on, that is, becomes the output state, which may have an adverse effect on both, leading to damage to the output circuit elements.The state where both of the above outputs are the result of the response time of the test object This is because the test arm turn data is divided and operated in two cycles, and in the first cycle, the data/mother turn is changed and the output terminal of the test object is turned off, that is, it is turned into an input terminal, and the next cycle i/1)
This can be prevented by changing the 4th turn and turning on the tester driver, that is, switching it to the output terminal.

Regarding the mask pattern, it is common to change the data pattern multiple times under these conditions for one mask pattern setting to test the logic function of the device under test. In this way, depending on the test conditions, 311
It is not necessary to change the Noreens of type 1 at the same time. However, in order to shorten the test time, it is desirable to change a plurality of mother turns at the same time as long as the test conditions permit.

In the actual test, these 79 turns are continuous, so it is necessary to switch the turn to be changed every cycle.

Normally, such non-turn occurrence occurs due to the above three types of /4'
This is done by storing each turn in a separate memory and reading it out independently. However, this method has the disadvantage that if any memory overflows, the number of parable turns that can be stored is limited, resulting in poor memory usage efficiency.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern generator which solves the above-mentioned problems and is fast and has good memory utilization efficiency.

The feature of the present invention is the test No. 4 of a tester for testing logic circuits.
In a device that generates turn data, there is a means for storing three types of test four turn data in the same memory, and a means for reading and outputting two types of test four turn data stored in the means within one cycle. A means for reading and outputting one type of data stored in the storage means in one cycle, and a means for switching between the two reading and outputting means, and a means for reading and outputting test/1-turn data in real time as necessary. The purpose of this invention is to switch the reading/output means.Detailed explanation will be given below using embodiments of the present invention.

FIG. 1 shows an embodiment of the invention.

The clock output terminal 2 and the control output terminal 3 of the microcontroller circuit 1 are respectively input to the clock input terminal 5 and the control output terminal 6 of the address control circuit 4. The address output terminal 7 of the address control circuit 4 enters the addresses 10 and 11 of the memory 8 and control memory 9, respectively. A data output terminal 12 of the control memory is connected to a data input terminal 13 of the microcontrol circuit 1. /# Data output 11j of turn memory 8: L' sister R1, RM.

It is connected to respective data input terminals 15, 16 and 17 of RD. The outputs of registers R1, RM, and RD are output as i/@/# turn data, mask gloss turn data, and data nona turn data via registers R1', RM, and RD'. In addition, register R1゜RM, RD has a microcontrol circuit, clock output of 1, eL
Kt, CLKM, and CLKD are connected.

Microcontrol circuit 1 clock output CLOCK
1 is connected to registers Rt' and RVtRD'. Microcontroller 1j21 Path 1 C: Analyzes the data read from the control memory 9, and generates a clock signal for setting memory addressing control signals and arm turn data in each register.

Address control circuit 4 determines a memory address according to the control signal and clock ADCL sent from microcontrol circuit 1. Register R1, RM,
RD is the mother turn of i10 respectively.

Mask pattern, data pattern control circuit 1
The black lines generated from CLKl and CLKM.

Read from CLKD4C, register Ri', RM
', RD' are timing registers for outputting normal data at the same time.
, 1, the data stored in the registers R1, RM, and RD are taken in and output simultaneously.

Non-turn generation is performed by successively reading nine turn data stored in the pattern memory 8.

When changing two types of patterns at the same time, this is done by accessing the memory twice during one cycle, and the operation is specified by data stored in the control memory 9.

FIG. 2 shows the pattern memory 8. The memory configuration of control memory 9 is shown. One bit is defined in the control memory 9 for pattern identification and control of simultaneous and individual changes of patterns. Bit l is @″1
”, the contents of the turn memory 9 are the fi i10 pattern, if bit M is “1”, the contents of the pattern memory are the mask two turns, and if both bit % and M are “0”, the data is the turn of the data fi i10. In addition, if bit C is m1'', it indicates that the next 79 turns following that pattern will also be read within the same clock. In FIG. 2, which shows a one-minute chart when the contents of the control memory 9 are read, the main turns Pi, P3.
P5 is a data pattern because the bits, pits M, and pits t are all MO''.The contents read from the 4/memory 8 are set in the register RD, and further outputted via the register R.

The /9 turn P2 is a mask no turn, and the /9 turn P4 is a mask no turn, which are set in the registers R1 and RM, respectively, and are further outputted via the registers gt' and gV, similarly to the data pattern described above. the register RD,
To store the contents of the memory in R1 and RM, the TAL and CL output from the microcontroller circuit 1 are used, respectively.
KD', CLKl, CLKM are used. At turn P4, bit C is 1'', so
Pattern P5 is also read within the same cycle and output at the same time. First, in the first half of the arm turn cycle, Noreen P4 is read out and set in register RM.
is read and set in register RD. Finally, the contents of the registers RD and RM are transferred by the clock CLOCK I K, and the mask pattern and data pattern are simultaneously output.

In the memory configuration shown in FIG.
The order of P5 is data pattern, i10 pattern.

These are the data pattern, the mask pattern turn, and the data pattern pattern, but the order differs depending on the test object, and the number of turns also differs. Furthermore, bit C#'i pattern P4
1, but as above, it varies depending on the test object.

FIG. 4 shows a circuit diagram of the 71 black control circuit 1.
Clock terminal 20 is connected to delay circuit 21, 22 AND? −
) 23, or f-) Enter 24. The output 25 of the delay circuit 21 is output as CLOCK1.

Is the output of the delay circuit 22 an AND? -) Enter 26.27.

Bit C is the other input 28 of andff-) 26.27
．． 29 and Inno-Yu 30 through andr-) 2
is connected to the other input of 3. Bit M is ande −
) 31 and Innogu Ichiyo 32 and dirt 33
, 34. Bit 1 is input to ANDr-) 33 via AND gate 3.4 as well as input and innoyata 35.
．． 31 respectively to the other input. Andr-)23
．． Is each output of 27 or? -) Connected to 35. Andr-) 33°34.31 output is andf-
) 36, 37° and 28 inputs, respectively. Andr-) 27.23 is OR gate 390 input, 40.4
1 respectively, and the output of OR p-) 39 goes into the other input of each of AND f-) 36, 37, and 38. andf-)24,36.37°38 is ADCL
, CLKD, CLKi, and CLKM, respectively.

Figure 5 shows black, CLOCK, CLOCK 1,
FIG. 3 is a diagram showing the timing of CLOCK 2. The delay circuit 21 has a fixed delay A of CLOCK 1,
The delay circuit 22 is a fixed delay 1 of CLOCK 2.
This is a delay circuit that generates B. When bit C is 0,
ANDGATE 23. Or? -) 39, the clock CLOCK enters 7 Y) r'-) 36, 37.38.

The above and r-) 36, 37.38 is the above black.

Whether or not to output CLOCK is determined by bits M and l. When bit M is ``11 bits'' and bit 1 is ``0'', the output of 31 is @ ``1'', and the AND dart 38 is black, and e bit M outputs CLOCK as CI and KM. If is ``Om10m1pi'l'', then andr-) If the output of 34 is @l'', andr-
)37>(Rio y ri CLOCK wo CL K i
(!: Shite output. Pit M1 pit amount are both 0#
When the output is ``1'', the AND gate 36 outputs CLOCK as CLKD.

When bit C is 1, AND dart 23 is turned off, and AND r-) 27 is turned ON. That is, clock C
LOCK 2 through orr-) 39 andr-
) Enter 36, 37.38. Said AND gate 36.3
The output conditions for 7.38 are the same as when bit C is 00, but only the clock is different. That is, clock 2 is output. For address clock and ADCL, bit C
When bit C is 0, the output of the AND/DART 26 is ``0#'', so only the clock CLOCK is output to ADCL.
CK 2 is output together. That is, 2 times during one period.
One Noculus is output.

The detailed explanation has been given above using the embodiments of the present invention.

As is clear from the above explanation, the present invention solves the conventional problems, and by using the present invention, it is possible to obtain a high-speed and memory-efficient middle turn generator. It is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the memory configuration, and FIG. 3 is a diagram showing the first whipyard.
FIG. 4 is a circuit diagram of the microcontrol circuit, and FIG. 5 is a diagram showing a clock. 1... Micro control, 4... Address control, 8, 9... Memory 1. R1, RM, RD. Ri', RM', RD'--Registers. Patent applicant: Fujitsu Limited
γ-68′y-n spear 2 diagram

Claims (1)

[Claims] A device for generating test turn data for a tester for testing logic circuits includes means for storing three types of test turn data, and two types of test turn data stored in the means for generating test turn data in one cycle. It consists of means for reading and outputting the data stored in the storage means, means for reading and outputting one type of data stored in the storage means in one cycle, and means for switching between the two reading and outputting means, in real time as necessary. Reading of test pattern data] A nonaturf generator characterized by switching the output means.