JPH03113898A - Fixed storage device - Google Patents

Fixed storage device

Info

Publication number
JPH03113898A
JPH03113898A JP1251499A JP25149989A JPH03113898A JP H03113898 A JPH03113898 A JP H03113898A JP 1251499 A JP1251499 A JP 1251499A JP 25149989 A JP25149989 A JP 25149989A JP H03113898 A JPH03113898 A JP H03113898A
Authority
JP
Japan
Prior art keywords
address
key
readout
stored
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1251499A
Other languages
Japanese (ja)
Inventor
Hiroto Ikeda
池田 弘人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1251499A priority Critical patent/JPH03113898A/en
Publication of JPH03113898A publication Critical patent/JPH03113898A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To enable the regulation control for readout requirement in a specific region by storing the address information as a key inputted from outside in the previously arbitrarily decided sequence for the specific region, then allowing the succeeding address to be the address executing the regulation control for the readout requirement. CONSTITUTION:An electrically writable memory cell 10 constituted of 2<m> word X1 bit in provided and plural pieces of address information are inputted as the key in the previously arbitrarily decided sequence, and the input is stored at a key register 20. Next in the region of the address form (n+1) to (2<m>-1) of successively inputted memory cell 10, the arbitrary plural group of address having data are stored at the key register 20 as the address to regulate the readout. And for the readout requirement to the address of the memory cell 10 in the region, after receiving the address information inputting in the order of the memory contents are readout. In such a manner, in the region of the address from (n+1) to (2<m>-1) the regulation control for the readout requirement of the memory cell is attained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は固定記憶装置に関し、特に特定の領域内の記憶
セルへの読出し要求に対して規制制御を行う固定記憶装
置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fixed memory device, and more particularly to a fixed memory device that performs regulatory control on read requests to memory cells within a specific area.

〔従来の技術〕[Conventional technology]

従来の固定記憶装置は、全領域について任意のアドレス
の内容を、随時読出すことが可能であった。
In conventional fixed storage devices, it was possible to read the contents of any address in the entire area at any time.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の固定記憶装置は、全領域について任意の
アドレスの内容を、随時読出すことが可能となっている
ので、書込んだ記憶内容に対する機密保護が図れないと
いう問題点がある。
The above-mentioned conventional fixed storage device has the problem that the contents of the entire area at any address can be read out at any time, so that the written storage contents cannot be kept confidential.

本発明の目的は、特定の領域内の任意のアドレスへの読
出し要求に対しては、外部から予め任意に定めた順序で
入力するアドレス情報をキーとして記憶し次に続くアド
レスに記憶したデータの読出し要求に対して規制制御を
行うキーとして使用することができる固定記憶装置を提
供することにある。
An object of the present invention is to store address information input from the outside in a predetermined order as a key in response to a read request to an arbitrary address within a specific area, and to read data stored at the next address. It is an object of the present invention to provide a fixed storage device that can be used as a key for regulating and controlling read requests.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の固定記憶装置は、2mワード×lピツ)−(m
およびlは自然数)構成の電気的に書込み可能な固定記
憶装置において、外部から予め任意に定めた順序で入力
するアドレス情報をキーとして記憶し次に続く前記固定
記憶装置の記憶セルのアドレスn+1から2”−1まで
(nは0 <n <2m−1を満足する自然数)の領域
内の任意のアドレスに記憶したデータの読出しを規制す
る際のキーとして使用する機能を持つキーレジスタを設
け、前記記憶セルのアドレスn+1から2−一1までの
領域内の記憶セルのアドレスへの読出し要求に対しては
前記キーレジスタに記憶されている前記予め任意に定め
た順序で入力するアドレス情報を受信後指定されたアド
レスの記憶内容を読出す構成である。
The fixed storage device of the present invention has 2 m words x 1 bits) - (m
and l is a natural number), address information input from the outside in an arbitrary predetermined order is stored as a key, and from address n+1 of the next memory cell of the fixed memory device. 2"-1 (n is a natural number satisfying 0 < n < 2m-1), a key register having a function to be used as a key for regulating reading of data stored at an arbitrary address within the area is provided, In response to a read request to an address of a memory cell in the area from address n+1 to 2-1 of the memory cell, address information stored in the key register and input in the predetermined order is received. The configuration is such that the stored contents at the specified address are read out.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

固定記憶装置1は、2mワード×lビット構成の電気的
に書込み可能な記憶セル10を有し、信号線100〜l
OO+ (m−1)でmビットのアドレスの指定を受け
、データ入出力線300〜300+ (1−1)でlビ
ットのデータを入出力する。信号線100〜100+<
m−1)には、記憶セル10と共に、予め任意に定めた
順序で入力するアドレス情報をキーとして記憶し、次に
続く領域内の任意のアドレスに記憶したデータの読出し
を規制する際のキーとして使用する機能を持つキーレジ
スタ20および、読出しゲート40を制御する読出しゲ
ート制御部30が接続している。
The fixed memory device 1 has an electrically writable memory cell 10 having a configuration of 2 m words x l bits, and has signal lines 100 to l bits.
It receives an m-bit address designation through OO+ (m-1), and inputs and outputs l-bit data through data input/output lines 300 to 300+ (1-1). Signal line 100~100+<
m-1), together with the memory cell 10, stores address information input in an arbitrary predetermined order as a key, and is used to control reading of data stored at an arbitrary address in the next area. A key register 20 having a function of being used as a key register and a read gate control unit 30 that controls a read gate 40 are connected.

キーレジスタ20は、書込みを制御する信号を入力する
キーレジスタ書込み制御線200と接続し、読出しゲー
ト制御部30に対する特定領域へのアクセスを許可する
信号を出力するアクセス許可信号線201と接続してい
る。読出しゲート制御部30は、読出しゲート40を制
御する信号を出力する読出しゲート制御信号線202を
持つ。
The key register 20 is connected to a key register write control line 200 that inputs a signal to control writing, and to an access permission signal line 201 that outputs a signal that allows the read gate control unit 30 to access a specific area. There is. The read gate control section 30 has a read gate control signal line 202 that outputs a signal for controlling the read gate 40.

記憶セル10は、データ入出力線300〜300+<1
−1)で受信したデータを書込むための制御信号を受信
するプログラム制御線203と接続する。  次に動作
について説明する。
The memory cell 10 has data input/output lines 300 to 300+<1
-1) is connected to the program control line 203 that receives the control signal for writing the data received. Next, the operation will be explained.

データを記憶セル10に書込む場合は、信号線100〜
100−100−)−(で選択されたアドレスに、デー
タ入出力線300〜300+ (1−1)で与えたデー
タを、プログラム制御線203から制御信号を入力して
書込む。
When writing data to the memory cell 10, the signal lines 100-
The data given by the data input/output lines 300 to 300+ (1-1) is written to the address selected by 100-100-)-(by inputting a control signal from the program control line 203.

データの読出しを規制する場合は、最初に、信号線10
0〜100+(m−1)から複数のアドレス情報を、予
め任意に定めた順序でキーとして入力する。この入力を
キーレジスタ20で記憶する。次に、続けて入力されて
くる記憶セルのアドレスn+1から2m−1までの領域
内にデータを持つ任意のアドレスの複数組を、以後読出
しを規制するアドレスとしてキーレジスタ書込み制御線
200の制御の下にキーレジスタ20に記憶する。
When restricting data reading, first the signal line 10
A plurality of address information from 0 to 100+(m-1) is input as a key in an arbitrary predetermined order. This input is stored in the key register 20. Next, a plurality of sets of arbitrary addresses having data in the area from address n+1 to 2m-1 of the memory cells that are successively inputted are used as addresses for regulating readout from now on, and are controlled by the key register write control line 200. It is stored in the key register 20 below.

この状態で、読出しゲート制御部3oは、信号線100
〜100+(m−1)で選択されたアドレスを監視し、
検出したアドレスが0≦に≦n(但し、nは予め決めら
れたアドレス値でoくn<2”’−1の関係にあるもの
とする)を満たす場合には、読出しゲート4oをイネー
ブルにする。
In this state, the read gate control unit 3o controls the signal line 100
~100+(m-1) selected addresses are monitored,
If the detected address satisfies 0≦≦n (where n is a predetermined address value and satisfies the relationship n<2'''-1), the read gate 4o is enabled. do.

又、アドレスがn+1≦に≦2−−1までの領域内にあ
る場合には、アクセス許可信号線201が「真」である
場合にのみ読出しゲート制御信号線202を「真」にし
て、読出しゲート4oをイネーブルにする。
Furthermore, if the address is within the range from n+1≦ to ≦2−-1, the read gate control signal line 202 is set to “true” only when the access permission signal line 201 is “true”, and the readout is performed. Enable gate 4o.

キーレジスタ20で予め任意に定めた順序で記憶した複
数のアドレス情報と、アドレスn+1から2w″−1ま
での領域内の任意のアドレスの複数組とは、装置の電源
を切断しても消去されず、電源投入により再度機能を回
復する。
A plurality of address information stored in a predetermined order in the key register 20 and a plurality of sets of arbitrary addresses in the area from address n+1 to 2w''-1 are erased even when the power to the device is turned off. The function will be restored again by turning on the power.

外部からこの読出しを規制する任意のアドレスから記憶
内容を読出すには、まず先に予め任意に定めた順序で記
憶した複数のアドレス情報を入力し、その後読出しを規
制するアドレスを指定することによって、この信号を受
信したキーレジスタ20がアクセス許可信号線201に
特定領域へのアクセスを許可する信号「真」を出力する
。この「真」を受けた読出しゲート制御部30は、読出
しゲート制御信号線202を「真」にして、読出しゲー
ト40から記憶内容を読出す。
To read the stored contents from an arbitrary address that restricts reading from the outside, first input multiple address information stored in an arbitrary predetermined order, and then specify the address that restricts reading. , upon receiving this signal, the key register 20 outputs a “true” signal to the access permission signal line 201 to permit access to the specific area. Upon receiving this "true", the read gate control section 30 sets the read gate control signal line 202 to "true" and reads the stored content from the read gate 40.

なお、予め任意に定めた順序で複数のアドレス情報をキ
ーレジスタ20に記憶させるl#JlIFと、予め任意
に定めた順序で記憶した複数のアドレス情報を受信し、
その後読出しを規制するアドレスを受信したことにより
読出し制御とを行うプログラムは、アドレスが0≦に≦
nの範囲の領域に記憶しておくことができる。
Note that receiving l#JlIF for storing a plurality of address information in the key register 20 in an arbitrary predetermined order and a plurality of address information stored in an arbitrarily predetermined order,
After that, a program that performs read control by receiving an address that restricts reading is configured such that the address is 0≦≦
It can be stored in an area within a range of n.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、特定の領域内の任意の
アドレスへの読出し要求に対しては、外部から予め任意
に定めた順序で入力するアドレス情報をキーとして記憶
し次に続くアドレスを、読出し要求に対して規制制御を
行うアドレスとすることができる効果が有る。
As explained above, in response to a read request to an arbitrary address within a specific area, the present invention stores address information input from the outside in a predetermined order as a key, and reads the next address. , there is an effect that the address can be used as an address to perform regulatory control on read requests.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図である。 1・・・・・・固定記憶装置、10・・・・・・記憶セ
ル、20・・−・・・キーレジスタ、30・・・・・・
読出しゲート制御部、40−−−−−・読出しゲート、
100〜100+ <m=1)・・・・・・信号線、2
00・・・・・−キーレジスタ書込みM御線、201・
・・・・・アクセス許可信号線、202・・・・・−読
出しゲート制御信号線、203・・・・・・プログラム
制御線、300〜300+ (1−1)・・−・・・デ
ータ入出力線。
FIG. 1 is a block diagram of one embodiment of the present invention. 1...Fixed storage device, 10...Storage cell, 20...Key register, 30...
Readout gate control unit, 40--readout gate,
100~100+ <m=1)...Signal line, 2
00...-Key register write M control line, 201.
...Access permission signal line, 202...-Read gate control signal line, 203...Program control line, 300~300+ (1-1)...Data input output line.

Claims (1)

【特許請求の範囲】[Claims]  2^mワード×lビット(mおよびlは自然数)構成
の電気的に書込み可能な固定記憶装置において、外部か
ら予め任意に定めた順序で入力するアドレス情報をキー
として記憶し次に続く前記固定記憶装置の記憶セルのア
ドレスn+1から2^m−1まで(nは0<n<2^m
−1を満足する自然数)の領域内の任意のアドレスに記
憶したデータの読出しを規制する際のキーとして使用す
る機能を持つキーレジスタを設け、前記記憶セルのアド
レスn+1から2^m−1までの領域内の記憶セルのア
ドレスへの読出し要求に対しては前記キーレジスタに記
憶されている前記予め任意に定めた順序で入力するアド
レス情報を受信後指定されたアドレスの記憶内容を読出
すことを特徴とする固定記憶装置。
In an electrically writable fixed storage device having a configuration of 2^m words x l bits (m and l are natural numbers), address information inputted from the outside in an arbitrary predetermined order is stored as a key, and the next fixed address information is stored as a key. Addresses n+1 to 2^m-1 of memory cells of the memory device (n is 0<n<2^m
A key register is provided which has a function to be used as a key for regulating the reading of data stored at an arbitrary address in the area (a natural number satisfying -1), and the key register is used as a key to regulate the reading of data stored at an arbitrary address in the area (a natural number satisfying -1), and the key register is used to control the readout of data stored at an arbitrary address in the area (a natural number satisfying -1). In response to a read request to an address of a memory cell in the area, after receiving the address information stored in the key register and inputted in the predetermined order, the stored contents of the specified address are read out. A fixed storage device characterized by:
JP1251499A 1989-09-26 1989-09-26 Fixed storage device Pending JPH03113898A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1251499A JPH03113898A (en) 1989-09-26 1989-09-26 Fixed storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1251499A JPH03113898A (en) 1989-09-26 1989-09-26 Fixed storage device

Publications (1)

Publication Number Publication Date
JPH03113898A true JPH03113898A (en) 1991-05-15

Family

ID=17223717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1251499A Pending JPH03113898A (en) 1989-09-26 1989-09-26 Fixed storage device

Country Status (1)

Country Link
JP (1) JPH03113898A (en)

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