JPS634358A - Parity bit rewriting circuit - Google Patents

Abstract

PURPOSE:To use effectively a memory element of (n)-word, (m)-bit constitution by providing a ROM for parity data conversion which rewrites only parity bits to be rewritten among plural parity bits. CONSTITUTION:Input data is inputted to memory elements 10-17 for storage and a parity bit generating circuit 5 through a data bus 2. Parity bits generated by the parity bit generating circuit 5 are rewritten in the ROM 7 for parity data conversion as after-rewriting parity bit information 44 through a parity bit signal line 62. When the data is written, a request to write the data is inputted to a control signal generating circuit 4 from outside this system and the control signal generating circuit 4 instructs a read of parity data from a memory element 6 for parity bit storage through a read/write control line 61.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parity bit rewriting circuit, and more particularly to a parity bit rewriting circuit for a memory element for storing parity bits (hereinafter referred to as a parity bit storage memory element). .

[Conventional technology]

In the field of microcomputer control and the like, as the storage capacity of memory increases, memory elements with a large storage capacity per memory element are increasingly used. 1
As the storage capacity per memory element increases, soft errors are more likely to occur, and as a countermeasure to this, there is a growing demand for adding parity bits to stored data, and a parity pinot exchange circuit is also required.

Conventionally, in this type of parity bit rewriting circuit, a memory element for storing a parity bit is stored in one area (a part of a memory element consisting of a plurality of memory cells connected to one word line, the same applies hereinafter). Only one parity bit was memorized.

FIG. 2 is a diagram showing an example of the configuration of a memory system using a conventional parity bit rewriting circuit.

In conventional parity bit rewriting circuits, memory elements for storing data (hereinafter referred to as data storage memory elements)? 0.71. . . , 77, when data is written in one area based on the address designation of the address decoder 78, the address decoder 88 selects a parity bit created by the parity bit creation circuit 89 based on this data. parity bit storage memory elements 80.81. ..., was written in one area in 87.

Parity bit storage memory elements 80, 81°...,
One area in 87 stores only 1 parity bit added to 1 data, so in order to simplify the circuit, parity bit storage memory elements 80, 8
1. For the river 87, a configuration of n (positive integer) words x 1 bit is suitable.

- On the other hand, this parity bit storage memory element 80.81
．． ..., when providing a battery bank amplifier function to a memory system that includes 87, it is necessary to minimize the current consumption during standby period, which is one of the most important electrical characteristics when performing battery back amplifier. In order to
A CMO3 (Complementary Metal Oxide Semiconductor, hereinafter the same) type static RAM (Random Access Memory; hereinafter the same) having characteristics suitable for that purpose is often used as the storage element.

[Problem that the invention seeks to solve]

In the conventional parity bit rewriting circuit described above, it is suitable to use a memory element with a structure of n words x 1 bit as the memory element for storing the parity bit. CMO
S-type static RAM is rare with this configuration, and usually one area consists of 1 byte (
Since a RAM of n words x 8 bits is often used, only one bit in one area of the RAM used as the memory element for storing the parity bit is used to store the parity bit. This has the disadvantage that other bits are not used, resulting in an uneconomical way of using RAM.

In view of the above-mentioned points, an object of the present invention is to effectively utilize a plurality of bits in one area of a memory element for storing parity bits to create a memory element having a configuration of n words x m bits (m≧2). It is an object of the present invention to provide a parity bit rewriting circuit that can be economically used as a memory element for storing parity bits.

[Means for solving problems]

The parity bit rewriting circuit of the present invention has a memory element for storing parity bits in which a plurality of parity bits to be added to a plurality of data are allocated to one area in a configuration of n words x m pinots (m≧2). , parity data that controls reading of parity data (information on one area in which a plurality of parity bits are stored on the parity bit storage memory element; the same applies hereinafter) including the bit to be rewritten from this parity bit storage memory element. The parity data read by the read control circuit and the parity data read control circuit, the position information of the parity bit to be rewritten in the parity data, and the rewritten value of the parity bit to be rewritten are input and rewritten. A ROM for parity data conversion (read-only memory; the same applies hereinafter) that outputs the parity data with only the correct parity focus rewritten, and a R for parity data conversion.
and a parity data write control circuit that controls writing of the parity data output by the OM to the same area on the parity bit storage memory element read by the parity data read control circuit.

[Effect]

In the parity pit rewriting circuit of the present invention, n words×m
A parity bit storage memory element in which a plurality of parity bits are assigned to one area of a memory element with a bit configuration of bits (m≧2) is used, and the bits to be rewritten from this parity bit storage memory element are included. The parity data read control circuit controls the reading of parity data, and the parity data conversion ROM converts the parity data, the position information of the parity bit to be rewritten within the parity data, and the value after rewriting of the parity bit to be rewritten. Parity data is output by rewriting only the parity bits that should be input and rewritten, and the parity data is written to the area on the memory element for parity bit storage that existed before the conversion of the parity data after this conversion. A control circuit controls and rewrites the parity bit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a memory system that uses an embodiment of the parity pit rewriting circuit of the present invention.The memory system that uses the parity pit rewriting circuit of this embodiment is designed to specify the address of data. address bus 1, data bus 2 for transmitting data contents, and memory elements 10, 11, . . . , 17, a control signal generating circuit 4 that controls successive output and writing of parity data on the parity bit storage memory element 6, and a control signal generation circuit 4 that controls whether the parity bit is O or 1 depending on the data value. a parity bit generation circuit 5 that determines a parity bit and generates a parity bit to be added to the data, and a data storage memory element 10.11. ..., 1
7 (the number of bits is 8, which is the number of data storage memory elements), and a parity bit storage memory element 6 that stores parity bits, and parity data including the parity bit to be rewritten. A parity data conversion ROM 7 for conversion, and a parity data write circuit 8 for latching the converted parity data before writing it into the parity pin storage memory element 6.
and data storage memory elements 10, 11, which store data to which parity bits are added. ..., from 17,
Its main parts are composed of: Note that 61 is a read/write control line, 62 is a parity bit signal line, 63 is a converted parity data output control line, 64 is a converted parity data write control line, and 65 is a parity data passing bus.

Referring to FIG. 3, the information stored in parity bit storage memory element 6 is stored in data storage memory elements 10, 11 . . . , a group of parity bits PO, P1 .・、P
7 (PO-Pl) each containing multiple parity bits).

These parity bit groups PQ, P1 . . . . P7 and data storage memory elements 10, 11 . ..., 17 means that, for example, the data stored in the data storage memory element 12 is included in the parity bit group P2, and the third area of the data storage memory element 12 (
The parity bit of the data stored in the 0th area (counting from the 0th area) is associated with the parity bit P22 included in the 3rd area of the parity bit storage memory element 60.

Referring to FIG. 4, the manner in which the parity data is converted in the parity data conversion ROM 7 is that the parity data 41 before conversion is supplied via the parity data passing bus 65, and the parity data 41 is supplied via the address bus l. 3-bit information (00
Rewrite bit position designation information 43 in which 0 indicates the least significant bit of parity data (PO in FIG. 3), and post-rewrite information indicating the value of the parity bit to be rewritten supplied via the parity bit signal line 62. The parity bit information 44 is input to the parity data conversion ROM 7,
The parity bit at the position indicated by the rewrite bit position specification information 43 in the pre-conversion parity data 41 is rewritten to the value of the post-rewrite parity bit information 44, and the generated post-conversion parity data 42 is used as the parity data conversion RO.
The parity data is outputted from M7 via a parity data passing bus 65.

Referring to FIG. 5, the information in the parity data conversion ROM 7 includes pre-conversion parity data 41, rewrite bit position designation information 43, and post-rewrite parity bit information 44.
The pre-conversion parity data 4 is added to the address 51 where
The converted parity data 42 in which the bit at the position indicated by the rewritten bit position designation information 43 of 1 is rewritten to the value of the rewritten parity bit information 44 is stored in correspondence as data content 52.

Next, the operation of the parity bit rewriting circuit configured as described above will be explained.

First, when write data is input to the memory system using the PIR bit rewriting circuit of this embodiment, this data is transmitted to the data storage memory elements 10, 11, . . . , 17 are input to the parity bit generation circuit 5. Here, since the data storage memory element is divided into data storage memory elements 10 to 17,
Data storage memory elements 10, 11 .
. . , 17 is selected by the address decoder 3 that receives information from the address bus 1, and data is written into the area specified by the address from the address bus 1 of the selected data storage memory element. It will be done.

The parity bit created by the parity bit creation circuit 5 is outputted from the parity bit creation circuit 5, and inputted to the parity data conversion ROM 7 as parity bit information 44 after being rewritten through the parity bit signal line 62.

- On the other hand, when writing data, a data write request from outside the memory system is input to the control signal generation circuit 4, and the control signal generation circuit 4 operates in a read/write mode.
It instructs reading of parity data from the parity bit storage memory element 6 via ill'fJA61. The specification of which area of the parity bit storage memory element 6 is to be read is performed by information provided via the address bus 1 from outside the memory system. The read parity data is input to the parity data conversion ROM 7 as pre-conversion parity data 41 via the parity data passing bus 65.

Furthermore, in the parity data conversion ROM 7, 3-bit information indicating the position of the parity focus to be rewritten (this is the same information as information indicating which data storage memory element the data has been written to) is connected to the address bus l. It is input as the rewrite bit position ↑ determination information 43 through the rewrite bit position ↑.

In the example shown in FIGS. 4 and 5, the above three values are that the parity data 41 before conversion is 11001001,
The rewrite bit position designation information 43 is 010, and the post-rewrite parity bit information 44 is 1.

The control signal generation circuit 4 causes the parity data conversion ROM 7 to output the converted parity data 42 to the parity data passing bus 65 via the converted parity data output control line 63 when these 12 bits of information are complete.

To explain this situation using the example shown in FIGS. 4 and 5,
First, the value 110010010101, which is a combination of the pre-conversion parity data 41, the rewritten bit position designation information 43, and the post-rewritten parity bit information 44, is given as the address 51 of the parity data conversion ROM 7.

The correspondence between the address 51 of the parity data conversion ROM 7 and the content 52 of the data stored at that address 51 and to be read is as shown in FIG. 11001
The value 11001101 in which the second pinto (the least significant bit is the 0th bit) indicated by 010 of the rewritten bit position specification information 43 of 001 is rewritten to l indicated by the rewritten parity bit information 44 is the converted parity data 4.
2 from the parity data conversion ROM 7.

The replaced parity data 42 output to the parity data write circuit 8 via the parity data passing bus 65 is
The data is not immediately written into the parity bit storage memory element 6, but after being converted by the control signal generation circuit 4, it is latched into the parity data write circuit 8 via the parity data write control line 4B 64.

Next, the control signal generation circuit 4 generates a read/write control line 61
The parity bit storage memory element 6 is instructed to change from the read state to the write state via the . , When the parity pit storage memory element 6 enters the write state, the control signal generation circuit 4 converts the converted parity data 42 latched into the parity data write circuit 8 via the converted parity data write control line 64 into parity data. The pre-conversion parity data 41 of the parity bit storage memory element 6 is written to the same area as the read area via the pass bus 65, and the rewriting of the parity bit is completed.

Note that this embodiment has been described on the assumption that no next data is written from outside the memory system until the rewriting of the parity bit is completed. However, if the data transfer is fast and this assumption does not apply, the address A latch circuit is inserted between the bus 1 and the data bus 2, and when rewriting the parity bit, the data write is latched by the instruction from the control signal generation circuit 4, and when the rewriting of the parity bit is completed, the control signal generation circuit 4 The parity bit rewriting circuit of the present invention can be applied by writing the next data in response to the rewriting end signal.

〔Effect of the invention〕

As explained above, the present invention provides a parity data conversion ROM for rewriting only the parity bits to be rewritten among a plurality of parity bits, thereby converting the structure of n words x m bits (m≧2). Even the memory device has the advantage that it can be economically used as a memory device for storing parity bits.

Furthermore, since a memory element for storing parity bits having a configuration of n words x m bits (m≧2) can be used, it is possible to use a memory element with the same configuration as a memory element for storing data and a memory element for storing parity bits. It has the effect of being able to.

[Brief explanation of drawings]

1 is a diagram showing the configuration of a memory system using an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a memory system using a conventional parity pit rewriting circuit, and FIG. 3 is a diagram showing the configuration of a memory system using a conventional parity pit rewriting circuit. FIG. 4 is a diagram showing information stored in the parity bit storage memory element of FIG.
FIG. 5 is a diagram showing the correspondence between addresses of data stored in the parity data conversion ROM in FIG. 1 and data contents. In the figure, 1... address bus, 2... data bus, 3... address decoder, 4... control signal generation circuit, 5... parity bit creation circuit, 6... parity pit storage Memory element, 7... ROM for parity data conversion, 8... Parity data writing circuit, 10-17... Memory element for data storage, 61... Read/write control line, 62... Parity bit signal line, 63: Post-conversion parity data output control line, 64: Post-conversion parity data write control line, 65: Parity data passing bus.

Claims (1)

[Claims] A parity bit storage memory in which a plurality of parity bits added to a plurality of data are allocated to one area in a configuration of n (positive integer) words x m (m≧2) bits. a parity data read control circuit that controls reading of parity data including bits to be rewritten from this parity bit storage memory element; and parity data read by the parity data read control circuit. The position information of the parity bit to be rewritten in the parity data and the value after rewriting of the parity bit to be rewritten are input, and the parity data in which only the parity bit to be rewritten is rewritten is output. a ROM for parity data conversion, and an area on the memory element for storing parity bits of which the parity data outputted by the ROM for parity data conversion is read out by the parity data readout control circuit; A parity bit rewrite circuit comprising: a parity data write control circuit that controls writing to an area; and a parity bit rewrite circuit.