JPH03113889A - Method for reproducing ferroelectric memory - Google Patents

Method for reproducing ferroelectric memory

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Publication number
JPH03113889A
JPH03113889A JP1248921A JP24892189A JPH03113889A JP H03113889 A JPH03113889 A JP H03113889A JP 1248921 A JP1248921 A JP 1248921A JP 24892189 A JP24892189 A JP 24892189A JP H03113889 A JPH03113889 A JP H03113889A
Authority
JP
Japan
Prior art keywords
voltage
polarization
ferroelectric
shaped electrodes
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1248921A
Other languages
Japanese (ja)
Inventor
Hideo Adachi
日出夫 安達
Hitoshi Watanabe
均 渡辺
Hiroyuki Yoshimori
由森 博之
Atsushi Yusa
遊佐 厚
Yoshinori Ota
好紀 太田
Takashi Mizusaki
水崎 隆司
Jun Funazaki
純 船崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP1248921A priority Critical patent/JPH03113889A/en
Publication of JPH03113889A publication Critical patent/JPH03113889A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent the crosstalk at the time of reading out and to allow the non-destructive reproducing of data by stopping the impression of the voltage before the inversion polarization area generated by the impression of a reading out voltage grows and identifying the polarity of residual polarization from the value of the currents flowing in 1st and 2nd band-shaped electrodes. CONSTITUTION:The voltage is impressed to the 1st band-shaped electrodes 17, 18 positioned above and below the ferroelectric film formed with the residual polarization. The voltage impression is stopped before the inversion polarization formed in the ferroelectric film by the voltage impression grows to the size at which the polarization remains in the film even after the impressed voltage is removed. The currents flowing in the 1st and 2nd band-shaped electrodes 17, 18 are subjected to current-voltage conversion by an amplifier 24, by which the currents are amplified. The amplified currents are inputted to a comparator circuit 26 which discriminates the polarity of the recorded residual polarization, by which the binary data is reproduced. The loss of the data by the crosstalk at the time of reading out is prevented in this way and the non-destructive reading out of the recorded data is executed.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は記録材料に強誘電体を使用する強誘電体メモ
リーの再生方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for reproducing a ferroelectric memory using a ferroelectric material as a recording material.

[従来の技術] 強誘電体材料は電圧が印加されると分極を生じ、その分
極特性は印加される電圧に対してヒステリシスを有する
。従って、電圧が印加された後、印加電圧が除去されて
も強誘電体にはPoまたは−Poの値の残留分極が残る
。記録材料に強誘電体を用い、例えば残留分極Poにデ
ータ“0”−Poにデータ“1”を対応させて2値デー
タを記録する強誘電体メモリーが提案されている。当初
、半導体メモリー等の駆動電圧と同等の低電圧で駆動で
きる強誘電体膜は、印加される実効的な電圧を大きくす
るため、薄く形成されなければならず、耐久性の点で問
題があったが、ゾルゲル法やMOD法、MOCVD法に
より、良好なヒステリシスと耐久性を有する強誘電体薄
膜が得られるようになった。
[Prior Art] Ferroelectric materials undergo polarization when a voltage is applied, and their polarization characteristics have hysteresis with respect to the applied voltage. Therefore, after a voltage is applied, even if the applied voltage is removed, residual polarization with a value of Po or -Po remains in the ferroelectric material. A ferroelectric memory has been proposed that uses a ferroelectric material as a recording material and records binary data by associating, for example, data "0" with residual polarization Po and data "1" with Po. Initially, ferroelectric films, which could be driven at low voltages equivalent to those of semiconductor memories, had to be made thin in order to increase the effective voltage applied, which caused problems in terms of durability. However, the sol-gel method, MOD method, and MOCVD method have made it possible to obtain ferroelectric thin films with good hysteresis and durability.

一般に強誘電体メモリーは、強誘電体膜の上部及び下部
に、膜を介して互いに直交する多数の帯状電極を備え、
上部帯状電極と下部帯状電極が重なる領域にメモリーセ
ルが形成される。−本の上部帯状電極と一本の下部帯状
電極を指定することによって特定のメモリーセルが選択
され、指定された上部帯状電極と下部帯状電極との間に
V。
Generally, a ferroelectric memory has a large number of strip-shaped electrodes on the top and bottom of a ferroelectric film, which are perpendicular to each other with the film in between.
A memory cell is formed in a region where the upper strip electrode and the lower strip electrode overlap. - A particular memory cell is selected by specifying one upper strip electrode and one lower strip electrode, and V between the designated upper strip electrode and the lower strip electrode.

または−voの電圧が印加されることにより、選択され
たメモリーセルに′0”または1”が記録される。記録
されたデータは、例えば、メモリーセルの上部電極に1
/2Vo、下部電極に一1/2Voを所定時間印加し、
このとき電極に流れる電流の量から、“0”であるが“
l”であるかが判別される。
By applying a voltage of -vo or -vo, '0' or '1' is recorded in the selected memory cell. The recorded data, for example,
/2Vo, applying 11/2Vo to the lower electrode for a predetermined time,
At this time, from the amount of current flowing through the electrode, it is "0", but "
1” is determined.

[発明が解決しようとする課8] このような強誘電体メモリーにおいて、例えば、書き込
みの際に上部電極に一1/2 vo、下部電極に1/2
Voが印加されて“1”が記録されたメモリーセルに、
読み出しの際に上部電極に1/2Vo、下部電極に一1
/2VOが印加されると、“1”に対応する残留分極に
対して反対方向の分極がメモリーセルに形成され、読み
出し後の記録状態は“0゛になる。すなわち、強誘電体
メモリーは破壊メモリーであり、1回の読み出しでデー
タが破壊される。しかし、メモリーとしては繰り返し再
生できる非破壊メモリーが望ましく、非破壊で読み出し
できる強誘電体メモリーの提供が望まれている。
[Issue 8 to be solved by the invention] In such a ferroelectric memory, for example, during writing, 1 1/2 vo is applied to the upper electrode and 1/2 vo is applied to the lower electrode.
To the memory cell to which Vo is applied and “1” is recorded,
When reading, 1/2Vo is applied to the upper electrode, and 1/2Vo is applied to the lower electrode.
When /2VO is applied, polarization in the opposite direction to the residual polarization corresponding to "1" is formed in the memory cell, and the recorded state after reading becomes "0". In other words, the ferroelectric memory is destroyed. It is a memory, and the data is destroyed by one readout. However, it is desirable that the memory be a nondestructive memory that can be repeatedly played back, and it is desired to provide a ferroelectric memory that can be read out nondestructively.

また、強誘電体メモリーには、読み出し時におけるクロ
ストークの問題がある。強誘電体メモリーではデータ読
み出し際、所定の上部帯状電極および下部帯状電極の各
々に、例えば1/2Vo及び−1/2Voが印加される
。このとき、上部または下部帯状電極を電極の一つに有
する他のメモリーセルにも1/2Voまたは一1/2V
oが印加される。
Furthermore, ferroelectric memory has the problem of crosstalk during reading. In a ferroelectric memory, when reading data, for example, 1/2Vo and -1/2Vo are applied to a predetermined upper band-shaped electrode and a lower band-shaped electrode, respectively. At this time, other memory cells having an upper or lower strip electrode as one of the electrodes also have 1/2Vo or 11/2V.
o is applied.

1/2Voまたは一1/2voが印加されたメモリーセ
ルの残留分極は、印加電圧が除去された後に元の値に戻
らない。この様子を説明する分極特性が第3図に示され
る。例えば、残留分極−Poを有する強誘電体にVlの
電圧が印加されると、その分極はメジャーループ42に
従ってA点に移行する。印加電圧が除去されると、残留
分極は−P1になる。残留分極−Plの強誘電体にさら
に電圧v1が印加されると、その分極は、メジャールー
プ42の内側に形成されるこれと相似なマイナーループ
44に従って変化してB点に移行し、印加電圧が除去さ
れると残留分極は−P2になる。従って、メモリーセル
の残留分極は、電圧が印加される度にその大きさが小さ
くなる。例えば、第4図に示される電極パターンにおい
て、上部電極46の一本を選択してl/2V、を印加し
、下部電極48に順番に一1/2Voを印加し、すべて
の下部電極48に電圧を印加し終えた後、上部電極46
を変えて同様の操作を行うことによって、すべてのメモ
リーセルのデータを読み出す場合、上部電極46がN本
あるとすると、N本口の上部電極46に読み出し用の電
圧が印加されるまでに、N来月の上部電極を有するメモ
リーセルには一1/2Voの電圧がN−1回印加される
。このため、メモリーセルの残留分極が非常に小さくな
り、データとして読み出せなくなるという問題がある。
The residual polarization of a memory cell to which 1/2Vo or 11/2Vo is applied does not return to its original value after the applied voltage is removed. Polarization characteristics explaining this situation are shown in FIG. For example, when a voltage of Vl is applied to a ferroelectric material having residual polarization -Po, the polarization shifts to point A according to the major loop 42. When the applied voltage is removed, the residual polarization becomes -P1. When a voltage v1 is further applied to the ferroelectric material with residual polarization - Pl, the polarization changes according to a minor loop 44 similar to this formed inside the major loop 42 and moves to point B, and the applied voltage When is removed, the residual polarization becomes -P2. Therefore, the residual polarization of the memory cell decreases in magnitude each time a voltage is applied. For example, in the electrode pattern shown in FIG. 4, one of the upper electrodes 46 is selected and 1/2V is applied, 11/2Vo is sequentially applied to the lower electrode 48, and all the lower electrodes 48 are applied with 1/2V. After applying the voltage, the upper electrode 46
When reading data from all memory cells by performing the same operation by changing A voltage of 11/2 Vo is applied N-1 times to the memory cell having an upper electrode of N next month. For this reason, there is a problem in that the residual polarization of the memory cell becomes extremely small, making it impossible to read it as data.

この発明は、読み出し時のクロストークの問題を解決す
るとともに、データが非破壊で再生される強誘電体メモ
リーの再生方法を提供することを目的とする。
The present invention aims to solve the problem of crosstalk during reading and to provide a method for reproducing ferroelectric memory in which data can be reproduced non-destructively.

[課題を解決するための手段] この発明の強誘電体メモリーの再生方法は、強誘電体薄
膜の上面に多数の第1の帯状電極が設けられ、前記強誘
電体膜を介して前記第1の帯状電極に交差する多数の第
2の帯状電極が前記強誘電体膜の下面に設けられ、前記
第1の帯状電極と前記第2の帯状電極との間に印加され
る電圧の向きに応じて形成される2つの残留分極を0ま
たは1に対応させて2値データを記録する強誘電体メモ
リーにおいて、残留分極が形成された前記強誘電体膜の
上下に位置する第1及び第2の帯状電極に電圧を印加す
る過程と、電圧印加により前記強誘電体膜中に形成され
る反転分極が、印加電圧が除去された後も膜中に残る大
きさに成長する以前に電圧の印加を停止する過程と、前
記第1及び第2の帯状電極に流れる電流を検出し、前記
強誘電体膜に記録された残留分極の極性を判別すること
により2値データを再生する過程とを有する。
[Means for Solving the Problems] In the ferroelectric memory reproducing method of the present invention, a large number of first strip-shaped electrodes are provided on the upper surface of a ferroelectric thin film, and the first strip electrodes are A large number of second strip-shaped electrodes are provided on the lower surface of the ferroelectric film to intersect with the strip-shaped electrodes, and the second strip-shaped electrodes are arranged in a manner that depends on the direction of the voltage applied between the first strip-shaped electrode and the second strip-shaped electrode. In a ferroelectric memory that records binary data by associating two residual polarizations formed by a ferroelectric film with 0 or 1, first and second ferroelectric films located above and below the ferroelectric film on which residual polarizations are formed are provided. The process of applying a voltage to the strip electrode and the application of the voltage before the inverted polarization formed in the ferroelectric film due to the voltage application grows to a size that remains in the film even after the applied voltage is removed. and a step of reproducing binary data by detecting the current flowing through the first and second strip electrodes and determining the polarity of residual polarization recorded in the ferroelectric film.

[作用] 強誘電体メモリーにおいて、データが記録された強誘電
体膜30は、第2A図に模式的に示されるように、記録
領域33の分極が同一方向に揃っている。読み出しの際
、この強誘電体膜30の上下に設けられる電極31及び
32に逆極性の電圧が印加されると、第2B図に示され
るように、既に形成されている分極に対して逆向きの分
極を有する反転分極域34が電極31及び32の近傍に
発生する。この状態で印加電圧が除去されると、反転分
極域34の先端部で逆向きの分極が接し、静電エネルギ
ー的に非常に不安定なため、反転分極域34は消失する
ことが知られている。第2B図に示される状態の強誘電
体膜30への電圧印加がさらに続けられると、反転分極
域34は成長し、第2C図に示されるように、反対側の
面に到達する。この状態はエネルギー的に安定で、印加
電圧が除去されても反転分極域34は消失することなく
、図に示される状態で膜中に残る。これは、強誘電体の
ヒステリシス特性の減極を示す。さらに電圧が印加され
続けると、反転分極域34が拡大し、最終的には第2D
図に示されるように、メモリーセルの記録領域33は反
転分極で占められるようになる。
[Function] In the ferroelectric memory, in the ferroelectric film 30 on which data is recorded, the polarization of the recording area 33 is aligned in the same direction, as schematically shown in FIG. 2A. During readout, when a voltage of opposite polarity is applied to the electrodes 31 and 32 provided above and below this ferroelectric film 30, as shown in FIG. 2B, the polarization is opposite to the already formed polarization. An inverted polarization region 34 having a polarization of is generated near the electrodes 31 and 32. It is known that when the applied voltage is removed in this state, the opposite polarizations touch at the tip of the reversed polarization region 34 and the reversed polarization region 34 disappears because it is extremely unstable in terms of electrostatic energy. There is. When the voltage application to the ferroelectric film 30 in the state shown in FIG. 2B continues, the reversed polarization region 34 grows and reaches the opposite surface as shown in FIG. 2C. This state is energetically stable, and even if the applied voltage is removed, the reversed polarization region 34 does not disappear and remains in the film in the state shown in the figure. This indicates the depolarization of the hysteresis property of the ferroelectric. As the voltage continues to be applied, the inverted polarization region 34 expands and eventually reaches the second D.
As shown in the figure, the recording area 33 of the memory cell becomes occupied by reversed polarization.

この発明の強誘電体メモリーの再生方法は、読み出し電
圧の印加によって発生する反転分極域34が、第2C図
の状態に移行する以前の第2B図の状態で電圧の印加を
停止する。強誘電体膜に記録されているデータ、すなわ
ち残留分極の極性の判別は、強誘電体膜の上下面に設け
られる第1及び第2の帯状電極31及び32に流れる電
流値から容易に判別される。これにより、読み出し電圧
が除去された後の残留分極は、電圧が印加される以前の
値に戻る。従って、強誘電体メモリーに記録されたデー
タを非破壊で読み出すことができるようになる。さらに
、アクセス対象以外のメモリーセルの残留分極が減少す
ることがなくなるので、読み出し時のクロストークによ
るデータの消失を防止できる。
In the ferroelectric memory reproducing method of the present invention, the voltage application is stopped in the state shown in FIG. 2B before the inverted polarization region 34 generated by the application of the read voltage shifts to the state shown in FIG. 2C. The data recorded on the ferroelectric film, that is, the polarity of residual polarization, can be easily determined from the current values flowing through the first and second strip electrodes 31 and 32 provided on the upper and lower surfaces of the ferroelectric film. Ru. As a result, the residual polarization after the read voltage is removed returns to the value before the voltage was applied. Therefore, data recorded in the ferroelectric memory can be read out non-destructively. Furthermore, since the residual polarization of memory cells other than those to be accessed does not decrease, data loss due to crosstalk during reading can be prevented.

[実施例コ この発明の強誘電体メモリーの基本的な回路図が第1図
に示される。列デコーダ11及び行デコーダ12は、そ
れぞれ512本のビット線17及びワード線18を備え
、これらのビット線17及びワード線18は、強誘電体
薄膜を介して互いに直交するように設けられる。ビット
線17及びワード線18は例えば2μmの幅を有し、両
信号線17.18が強誘電体膜を介して交差する2μm
×2μmの面積の領域に1個のメモリーセルが形成され
る。すなわち、512X512−262144個のメモ
リーセルがマトリックス状に設けられる。書き込み及び
読み出しの際には、262144個のメモリーセルの中
から特定のメモリーセルが選択され、選択されたメモリ
ーセルへのデータの書き込みまたは読み出しが行われる
[Embodiment 2] A basic circuit diagram of a ferroelectric memory according to the present invention is shown in FIG. The column decoder 11 and the row decoder 12 each include 512 bit lines 17 and word lines 18, and these bit lines 17 and word lines 18 are provided so as to be orthogonal to each other via a ferroelectric thin film. The bit line 17 and the word line 18 have a width of, for example, 2 μm, and both signal lines 17 and 18 have a width of 2 μm that intersects with each other via a ferroelectric film.
One memory cell is formed in a region having an area of x2 μm. That is, 512×512-262144 memory cells are provided in a matrix. During writing and reading, a specific memory cell is selected from among the 262,144 memory cells, and data is written to or read from the selected memory cell.

書き込みについて説明すると、まず書き込みの対象とな
るメモリーセルに対応する列アドレス及び行アドレスが
それぞれ列デコーダ11及び行デコーダ12に入力され
、所定のメモリーセルが選択される。端子fを介してス
イッチ16に書き込み指示パルスが入力されると、パル
ス発生器13と端子16aが電気的に接続され、パルス
発生器13から発生された電圧パルスが列デコーダを介
して、選択されたビット線17に印加される。これと同
時に書き込み指示パルスは端子gを介してパルス発生器
14に入力され、パルス発生器14は電圧パルスを発生
し、この発生された電圧パルスは行デコーダ12を介し
て選択されたワード線18に印加される。2つのパルス
発生器13及び14は、クロック発生回路15から発生
されるクロック信号によって駆動され、同期した電圧パ
ルスを発生する。選択されたメモリーセルに“1“を書
き込む場合は、パルス発生器13は一1/2Voの電圧
パルスをパルス発生器14は+1/2Voの電圧パルス
を発生し、“0#を書き込む場合は、パルス発生器13
は+1/2Voの電圧パルスをパルス発生?S14は一
1/2Voの電圧パルスを発生する。
To explain writing, first, a column address and a row address corresponding to a memory cell to be written are input to a column decoder 11 and a row decoder 12, respectively, and a predetermined memory cell is selected. When a write instruction pulse is input to the switch 16 via the terminal f, the pulse generator 13 and the terminal 16a are electrically connected, and the voltage pulse generated from the pulse generator 13 is selected via the column decoder. is applied to the bit line 17. At the same time, the write instruction pulse is input to the pulse generator 14 via the terminal g, the pulse generator 14 generates a voltage pulse, and the generated voltage pulse is transmitted to the selected word line 18 via the row decoder 12. is applied to The two pulse generators 13 and 14 are driven by a clock signal generated from a clock generation circuit 15 and generate synchronized voltage pulses. When writing "1" to the selected memory cell, the pulse generator 13 generates a voltage pulse of 1/2 Vo, and the pulse generator 14 generates a voltage pulse of +1/2 Vo. When writing "0#", the pulse generator 14 generates a voltage pulse of +1/2 Vo. Pulse generator 13
Does it generate a voltage pulse of +1/2Vo? S14 generates a voltage pulse of 11/2Vo.

次に図を参照しながら、読み出し動作について説明する
。読み出しの対象となるメモリーセルに対応する列アド
レス及び行アドレスが、それぞれ列デコーダ11及び行
デコーダ12に入力され、読み出し対象のメモリーセル
が選択される。端子fを介してスイッチ16に読み出し
指示パルスが入力されると、パルス発生器13と端子1
6bが電気的に接続されるとともに、パルス発生器13
からパルス幅100nsを有する5■の電圧パルスが発
生される。このパルスはNANDゲート21及びAND
ゲート22に入力される。最初、比較器26からの出力
はなく、従ってNANDゲート21は5Vを出力し、A
NDゲート22は5Vを出力する。ANDゲート22か
らの出力電圧は増幅器23で増幅されて列デコーダ11
に人力され、選択されたビット線17に印加される。
Next, the read operation will be explained with reference to the drawings. A column address and a row address corresponding to a memory cell to be read are input to a column decoder 11 and a row decoder 12, respectively, and the memory cell to be read is selected. When a read instruction pulse is input to the switch 16 via the terminal f, the pulse generator 13 and the terminal 1
6b is electrically connected, and the pulse generator 13
5 voltage pulses with a pulse width of 100 ns are generated. This pulse is connected to NAND gate 21 and AND
The signal is input to gate 22. Initially, there is no output from comparator 26, so NAND gate 21 outputs 5V and A
ND gate 22 outputs 5V. The output voltage from the AND gate 22 is amplified by the amplifier 23 and sent to the column decoder 11.
is manually applied to the selected bit line 17.

また、読みだし指示パルスは端子gを介してパルス発生
器14に入力され、パルス発生器13から発生されるパ
ルスと同期する、パルス幅100nsの一5Vの電圧パ
ルスがパルス発生器14から出力される。このパルスは
行デコーダ12を介して選択されたワード線18に印加
される。
Further, the read instruction pulse is input to the pulse generator 14 via the terminal g, and a voltage pulse of -5V with a pulse width of 100 ns, which is synchronized with the pulse generated from the pulse generator 13, is output from the pulse generator 14. Ru. This pulse is applied to the selected word line 18 via the row decoder 12.

メモリーセルのビット線17及びワード線18に電圧が
印加されると、“1”が記録されたメモリーセルの分極
が変化し、ビット線17及びワード線18に電流が流れ
る。この電流は増幅器24によって電流−電圧変換され
るとともに、その電圧が増幅されて出力されるとともに
、比較回路26に入力される。比較回路26は人力され
る電圧信号と、しきい値設定電源で設定される電圧と比
較し、入力電圧信号が設定電圧以上になったとき5Vを
出力する。比較回路26から5vが出力されると、NA
NDゲート21の出力は0■になり、ANDゲート22
の出力もOVになる。従って、パルス発生回路13から
出力されるパルスがOvになる以前であっても、比較回
路26から5vが出力されると、メモリーセルへの電圧
の印加が停止される。
When a voltage is applied to the bit line 17 and word line 18 of the memory cell, the polarization of the memory cell in which "1" is recorded changes, and current flows through the bit line 17 and word line 18. This current is subjected to current-to-voltage conversion by the amplifier 24, and the resulting voltage is amplified and output, and is also input to the comparison circuit 26. The comparison circuit 26 compares the manually input voltage signal with the voltage set by the threshold setting power supply, and outputs 5V when the input voltage signal exceeds the set voltage. When 5V is output from the comparison circuit 26, NA
The output of the ND gate 21 becomes 0■, and the output of the AND gate 22
The output of is also OV. Therefore, even before the pulse outputted from the pulse generation circuit 13 reaches Ov, when 5V is outputted from the comparison circuit 26, the application of voltage to the memory cell is stopped.

しきい値設定電源で設定される電圧は使用する強誘電体
メモリーに応じて適宜設定されるが、設定電圧が高すぎ
ると破壊読み出しとなり、反対に低すぎると出力電流が
小さすぎて読み出しの信頼性が低下する。従って、予め
適用する強誘電体メモリーに、しきい値を変えながら記
録・再生を行い、繰り返しの読み出しが可能なしきい値
が実験的に選定される。
The voltage set by the threshold setting power supply is set appropriately depending on the ferroelectric memory used, but if the set voltage is too high, it will lead to destructive reading, and if it is too low, the output current will be too small, making reading unreliable. Sexuality decreases. Therefore, recording and reproduction are performed while changing the threshold value in a ferroelectric memory applied in advance, and a threshold value that allows repeated reading is experimentally selected.

[発明の効果] この発明の強誘電体メモリーの再生方法によれば、読み
出し時のクロストークによるデータの損失を防止すると
ともに、強誘電体に記録されたデータが非破壊で読み出
すことが可能になる。
[Effects of the Invention] According to the ferroelectric memory reproducing method of the present invention, data loss due to crosstalk during reading can be prevented, and data recorded in the ferroelectric can be read out non-destructively. Become.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の強誘電体メモリーの基本的な回路図
、第2A図乃至第2D図は強誘電体膜の分極の様子を示
す図、第3図は強誘電体の分極特性を示す図、第4図は
誘電体メモリーの電極パターンを示す図である。 11・・・列デコーダ、12・・・行デコーダ、13゜
4・・・パルス発生器、15・・・クロック発生回路、
7・・・ビット線、18・・・ワード線。
Fig. 1 is a basic circuit diagram of the ferroelectric memory of the present invention, Figs. 2A to 2D are diagrams showing the state of polarization of the ferroelectric film, and Fig. 3 shows the polarization characteristics of the ferroelectric material. FIG. 4 is a diagram showing an electrode pattern of a dielectric memory. 11... Column decoder, 12... Row decoder, 13°4... Pulse generator, 15... Clock generation circuit,
7...Bit line, 18...Word line.

Claims (1)

【特許請求の範囲】  強誘電体薄膜の上面に多数の第1の帯状電極が設けら
れ、前記強誘電体膜を介して前記第1の帯状電極に交差
する多数の第2の帯状電極が前記強誘電体膜の下面に設
けられ、前記第1の帯状電極と前記第2の帯状電極との
間に印加される電圧の向きに応じて形成される2つの残
留分極を0または1に対応させて2値データを記録する
強誘電体メモリーにおいて、 残留分極が形成された前記強誘電体膜の上下に位置する
第1及び第2の帯状電極に電圧を印加する過程と、 電圧印加により前記強誘電体膜中に形成される反転分極
が、印加電圧が除去された後も膜中に残る大きさに成長
する以前に電圧の印加を停止する過程と、 前記第1及び第2の帯状電極に流れる電流を検出し、前
記強誘電体膜に記録された残留分極の極性を判別するこ
とにより2値データを再生する過程とを有する強誘電体
メモリーの再生方法。
[Scope of Claims] A large number of first band-shaped electrodes are provided on the upper surface of the ferroelectric thin film, and a large number of second band-shaped electrodes that intersect with the first band-shaped electrodes via the ferroelectric film are provided on the upper surface of the ferroelectric thin film. Two residual polarizations provided on the lower surface of the ferroelectric film and formed depending on the direction of a voltage applied between the first strip electrode and the second strip electrode correspond to 0 or 1. In a ferroelectric memory that records binary data using a remanent polarization, the process includes: applying a voltage to first and second strip-shaped electrodes located above and below the ferroelectric film in which remanent polarization is formed; stopping the application of voltage before the inverted polarization formed in the dielectric film grows to a size that remains in the film even after the applied voltage is removed; A method for reproducing a ferroelectric memory comprising the steps of detecting a flowing current and reproducing binary data by determining the polarity of residual polarization recorded in the ferroelectric film.
JP1248921A 1989-09-25 1989-09-25 Method for reproducing ferroelectric memory Pending JPH03113889A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1248921A JPH03113889A (en) 1989-09-25 1989-09-25 Method for reproducing ferroelectric memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1248921A JPH03113889A (en) 1989-09-25 1989-09-25 Method for reproducing ferroelectric memory

Publications (1)

Publication Number Publication Date
JPH03113889A true JPH03113889A (en) 1991-05-15

Family

ID=17185401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1248921A Pending JPH03113889A (en) 1989-09-25 1989-09-25 Method for reproducing ferroelectric memory

Country Status (1)

Country Link
JP (1) JPH03113889A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6865101B2 (en) 2001-08-23 2005-03-08 Matsushita Electric Industrial Co., Ltd. Memory system and semiconductor integrated circuit in which operation timings can be set externally

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6865101B2 (en) 2001-08-23 2005-03-08 Matsushita Electric Industrial Co., Ltd. Memory system and semiconductor integrated circuit in which operation timings can be set externally
US7075811B2 (en) 2001-08-23 2006-07-11 Matsushita Electric Industrial Co., Ltd. Memory system and semiconductor integrated circuit
US7262986B2 (en) 2001-08-23 2007-08-28 Matsushita Electric Industrial Co., Ltd. Memory system and semiconductor integrated circuit
US7433221B2 (en) 2001-08-23 2008-10-07 Matsushita Electric Industrial Co., Ltd Memory system and semiconductor integrated circuit
US7697315B2 (en) 2001-08-23 2010-04-13 Panasonic Corporation Memory system and semiconductor integrated circuit

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