JPH03113547A - Storage controller - Google Patents

Abstract

PURPOSE:To perform an access to a memory at a speed N times as high as the memory cycle time by giving accesses successively to N pieces of memories having the same cycle time with the phases shifted by 1/N memory cycle time. CONSTITUTION:A generating means (b) produces a pulse train having the same cycle as a memory cycle time 12ns, and a generating means (c) produces three pulse trains having a cycle of 12ns and the phases shifted by 4ns from each other based on the pulse train produced by the means (b). Thus an access means (b) has the independent accesses to three memories (a) based on each pulse train having the same cycle as the memory cycle time, i.e., the cycle 12ns where the phases are shifted by 4ns from each other. As a result, three memories (a) receive aparently three accesses as a whole for each memory cycle time 12ns even though these memories (a) receive actually the accesses in the cycle 12ns proper to each memory (a).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage control device suitable for accessing memory at high speed.

[Summary] The present invention enables a storage control device to sequentially access N memories having the same memory cycle time by shifting the phase by 1/N period of the period of the memory cycle time. Although each memory is accessed once per memory cycle time, when viewed as a whole, the apparent memory cycle time is N
It has been made accessible twice.

[Prior Art] As shown in FIG. 6, a conventional storage control device executes access at a memory cycle time period specific to the memory, which is determined depending on the characteristics of the memory.

That is, as shown in the figure, one access is performed per memory cycle time.

[Problems to be Solved by the Invention] In other words, it is not possible to access the memory multiple times per memory cycle time, and high-speed access has been desired.

However, since the memory cycle time depends on the characteristics of the memory, the memory cycle time itself cannot be shortened, and high-speed access cannot be achieved by shortening the memory cycle time. Also, if you use memory with a short memory cycle time, you can achieve faster access, but such memory is expensive, and above all, you cannot achieve high-speed access beyond the memory cycle time constraint. .

So, after careful consideration, we decided to utilize multiple memories.
We came up with the idea that these memories could be accessed multiple times per memory cycle time.

An object of this invention is to enable multiple accesses per memory cycle time.

[Means to solve the problem] The means of this invention are as follows.

The N memories a (see the functional block diagram of FIG. 1, the same applies hereinafter) are memories such as semiconductor memories, and their memory cycle times are the same T.

The generating means C generates a pulse train having the same period as the memory cycle time T.The generating means C generates a pulse train having the same period as the memory cycle time T.The generating means C generates a pulse train whose phase is shifted from each other by 'I'/N periods based on the pulse train generated by the lower generation stage.
The pulse train with the same period as the memory cycle time “I” is N.
Generate columns.

The access means d individually accesses each of the N memories a based on each pulse train generated by the generation means C.

[Effect 1 The operation of the means of this invention is as follows.

It is assumed that three memories a each having a memory cycle time of 12 ns are provided.9 In this case, the generating means has a memory cycle time of 12 n s.
A pulse train with the same period as s is generated.

Then, the generating means C generates 12
Based on the pulse train with a period of ns, three pulse trains with a period of 12 ns are generated, the phases of which are shifted by 4 ns from each other.

Then, the access means d individually accesses each of the three memories a based on each pulse train whose phases are shifted from each other by 4 ns and whose period is 12 ns, that is, the same period as the memory cycle time.

As a result, although each of the three memories a is accessed at a period with a unique memory cycle time of 12 ns, when viewed as a whole, it appears that the three memories a are accessed three times per 1 memory cycle time of 12 ns. Become.

Therefore, ■Memory can be accessed multiple times per memory cycle time.3 [Embodiment] An embodiment will be explained below with reference to FIGS. 2 to 5.9 FIG. 2 is a block diagram of the memory control device. As shown in the figure, the memory controlled by this storage control device is the memory Ml? : and memory MO. In these memories ME and MO, for example, a series of data DO, Di, D2, D3, . . . , which was conventionally stored in one memory as shown in FIG. As shown in FIG. 3(b), the memory 9 is stored alternately in the memory ME and the memory MO.
E and memory MO are assigned addresses in the same address space. In addition, memory ME and memory MO are
Those with the same memory cycle time are used.

As shown in FIG. 2, the storage control device includes a memory ME,
In addition to the memory MO, it has a pulse generator 1, an inverter 2, an address generator 3, an address delay circuit 4, two try date buffers γ5, 6, and a data register 7.

The pulse generator ■ generates a pulse PA having the same period as the memory cycle time of the memory ML2 and the memory MO, and a pulse PB having a period twice that of this pulse PA.
A is output to the inverter 2, address generator 3, and tri-state buffer 5, and pulse PB is output to the data register 7.

Inverter 2 inverts pulse PA from pulse generator 1 and outputs it as pulse PAO to address delay circuit 4 and trice date buffer γ6.

Due to this inversion, the phases of pulse PA and pulse PAO are shifted from each other by an amount corresponding to the opposite period.

The address generator 3 sequentially generates access addresses,
Based on the pulse PA from the pulse generator 1, the address delay circuit 4 outputs it to the address delay circuit 4 and the memory ME. 3
By outputting the access address from , the access address is delayed and output to the memory MO. As a result, the same access address from the address generator 3 given to the memory MO and the memory M1.] is shifted from each other by half the memory cycle time.

The tri-state buffer γ5 relays transmission data between the memory ME and the data register 7, and inputs and outputs data when the pulse PA is at the "L" level, that is, when the data is determined. The tri-state buffer γ6 relays transmission data between the memory MO and the data register 7, and inputs and outputs data when the pulse PAO is at the "1." level, that is, when the data is determined.

The data register 7 exchanges data between the tri-state buffer 5 or the tri-state buffer 6 and other components based on the pulse IJH.

Next, access control will be explained with reference to FIG.

As shown in FIG. 4, pulse PB is
The period is doubled.

The access address generated by the address generator 3 in synchronization with the pulse PA (two pulses PAE are shown in FIG. 4 for ease of understanding) is as follows:
The address delay circuit 4 outputs the pulse PA (PAE) directly to the memory ME and the address delay circuit 4 to the memory MO by an inverse period from the pulse PAE. The access address from the address generator 3 is output to the memory MO based on the delayed pulse PAO. Therefore, memory ME
Although the same access address is output to the memory MO and the memory MO, the output timing is shifted by half of the memory cycle time.

Further, each negative logic gate terminal of the tri-state buffer 5 and the tri-state buffer 6 receives a pulse P.
Since AE and pulse PAO are input, as shown by the hatching in FIG. 4, the memory ME and memory MO
As a result, accesses to the memory ME and memory MO are performed once per memory cycle tie 11, respectively, as shown by DAE and DAO in FIG. Despite the fact that
This means that two accesses are performed per memory cycle time.

[Modification] FIG. 5 is a time chart in a modification in which three memories are used.

In this case, as shown in FIG. 5, each pulse A1, A2, which has the same period as one memory cycle time and whose phase is shifted by 1/3 period of the pulse,
In synchronization with A3, the access addresses ADI and AC are respectively
3. Give AC3 to each memory.

Then, although each of the three memories is accessed once per memory cycle time,
Overall, it appears that three accesses are performed per one memory cycle time (Di, D2
, see D3).

In other words, if N memories are accessed using the same method, N accesses can be made per (1) memory cycle time, and the access speed can be N times faster than in the past.

Such a technique is particularly effective when accessing memory continuously, such as when reading programs continuously based on a program counter.

Note that it is not necessary to allocate the same address to a plurality of memories, and different addresses may be allocated to each other.

[Effects of the Invention] According to the present invention, high-speed access is possible because multiple accesses can be made per one memory cycle time, and in particular, the greater the number of consecutive accesses, the greater the utility.9

[Brief explanation of drawings]

Fig. 1 is a functional block diagram of the present invention, Fig. 2 is a block configuration diagram of an embodiment, Fig. 313 is a diagram for explaining distribution of data to multiple memories, and Fig. 4 explains access timing for each memory. Fig. 5 is a time chart for explaining a modified example.
FIG. 6 is a time chart for explaining the prior art. 91...Pulse interventional device, 2...Inverter, 3-
・7' address generator, 4...address delay circuit, 5.
6...I・Light state buffer, Mlg, MO...
・Memory 9 patent applicant Casio Computer Co., Ltd.

Claims (1)

[Scope of Claims] N memories all having the same memory cycle time T, a generating means for generating a pulse train having the same period as the memory cycle time T, and based on the pulse train generated by the generating means, T/
a generating means for generating N pulse trains whose phases are shifted from each other by N periods and having the same period as the memory cycle time T; and individually accessing each of the N memories based on each pulse train generated by the generating means. A storage control device comprising: an access means;