JPH03113442U - - Google Patents
Info
- Publication number
- JPH03113442U JPH03113442U JP2226190U JP2226190U JPH03113442U JP H03113442 U JPH03113442 U JP H03113442U JP 2226190 U JP2226190 U JP 2226190U JP 2226190 U JP2226190 U JP 2226190U JP H03113442 U JPH03113442 U JP H03113442U
- Authority
- JP
- Japan
- Prior art keywords
- address
- signal
- error
- processing unit
- central processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 230000001934 delay Effects 0.000 claims 1
- 230000003111 delayed effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2226190U JPH03113442U (cs) | 1990-03-06 | 1990-03-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2226190U JPH03113442U (cs) | 1990-03-06 | 1990-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03113442U true JPH03113442U (cs) | 1991-11-20 |
Family
ID=31525276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2226190U Pending JPH03113442U (cs) | 1990-03-06 | 1990-03-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03113442U (cs) |
-
1990
- 1990-03-06 JP JP2226190U patent/JPH03113442U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0149049A3 (en) | Data memory with simultaneous write and read | |
| KR910001517A (ko) | 데이타 처리 시스템 | |
| KR910015999A (ko) | 반도체 메모리장치 | |
| EP0365023A3 (en) | Address control circuit for data memory employed in signal delay circuit | |
| JPH03113442U (cs) | ||
| CA2012318A1 (en) | Microprocessor system having an extended address space | |
| JPH03110546U (cs) | ||
| JPS6055916B2 (ja) | タイミング回路 | |
| JPS6225798Y2 (cs) | ||
| JPH029401Y2 (cs) | ||
| JPH03107749U (cs) | ||
| JP2915707B2 (ja) | ダイナミックｒａｍ | |
| JP2919357B2 (ja) | Ｃｐｕインタフェース回路 | |
| JPH0438545A (ja) | メモリ保護回路 | |
| JP2578874B2 (ja) | パルス回路 | |
| JPH0561714B2 (cs) | ||
| JPS6251600U (cs) | ||
| JPS5654696A (en) | Memory device | |
| JPH04160487A (ja) | 半導体集積回路 | |
| JPH1055317A (ja) | バックアップメモリ回路 | |
| JPH0474342U (cs) | ||
| JPS59128619A (ja) | マイクロコンピユ−タ装置 | |
| JPS59192755U (ja) | エラステイツク・ストア回路 | |
| JPS55134461A (en) | Memory unit control system | |
| JPH0485183U (cs) |