JPH03112155A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPH03112155A JPH03112155A JP25104589A JP25104589A JPH03112155A JP H03112155 A JPH03112155 A JP H03112155A JP 25104589 A JP25104589 A JP 25104589A JP 25104589 A JP25104589 A JP 25104589A JP H03112155 A JPH03112155 A JP H03112155A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- recess
- lead
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000002184 metal Substances 0.000 abstract description 7
- 239000012212 insulator Substances 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000000881 depressing effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 8
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置のパッケージに関し、特に、半
導体装置のライン（信号ライン、電源ライン及びアース
ライン）を外部に導出する端子を改良することにより、
破損や静電破壊等の危険性が低減されるようにしたもの
である。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a package for a semiconductor device, and in particular, to improving terminals for leading lines (signal lines, power lines, and ground lines) of a semiconductor device to the outside. According to
This reduces the risk of damage, electrostatic damage, etc.
従来の半導体装置のパッケージとしては、例えば第３図
に示すようなものがある。As a conventional semiconductor device package, there is one shown in FIG. 3, for example.
第３図は、半導体装置１を封入した状態のパッケージ２
の断面図であり、パッケージ２は、キャップ３．基板４
及び図示しないシール部材によって、半導体装置ｌを外
部雰囲気から遮断している。FIG. 3 shows a package 2 in which a semiconductor device 1 is enclosed.
FIG. Board 4
The semiconductor device 1 is isolated from the external atmosphere by a sealing member (not shown).
なお、キャップ３及び基Ｆｉ４は絶縁体から成形されて
いて、半導体装置１は、接着剤等によって基板４の上面
に固定されている。Note that the cap 3 and the base Fi4 are molded from an insulator, and the semiconductor device 1 is fixed to the upper surface of the substrate 4 with an adhesive or the like.
パッケージ２のキャップ３及び基板４間には端子として
の多数のピン５が挟持されている。これらピン５はパッ
ケージ２外部において屈曲してその先端が下方を向くと
共に、パッケージ２内に位置するそれらピン５のそれぞ
れの内端は、ワイヤ６を介して半導体装置ｌの各ライン
（信号ライン、電源ライン、アースライン等）に接続さ
れている。A large number of pins 5 as terminals are held between the cap 3 and the substrate 4 of the package 2. These pins 5 are bent outside the package 2 so that their tips point downward, and the inner ends of the pins 5 located inside the package 2 are connected to each line (signal line, (power line, ground line, etc.).
従って、ピン５を介して、半導体装置ｌとの信号の送受
（言や、半導体装置ｌへの電源の供給等を行うことがで
きる。Therefore, via the pin 5, it is possible to transmit and receive signals to and from the semiconductor device l, and to supply power to the semiconductor device l.
このようなパッケージ２に封入された半導体装置ｌを実
装するには、実装基板（図示せず）に設けられた凹型端
子に各ピン５の先端を差し込むと共に、その差し込んだ
部分をはんだ付は等により固着保持ずればよい。In order to mount the semiconductor device l enclosed in such a package 2, the tip of each pin 5 is inserted into a recessed terminal provided on a mounting board (not shown), and the inserted portion is soldered, etc. All you have to do is hold it firmly and shift it.
しかしながら、上述した従来のパッケージ２にあっては
、半導体装置１のラインを外部に導出する端子としての
ピン５がパッケージ２外部に突出していて、運搬や実装
の際に人や機械等がピン５に触れ易いため、ピン５が折
れ曲がる等して破損したり、半導体装置ｌで静電破壊が
発生するという危険があった。However, in the conventional package 2 described above, the pins 5 as terminals for leading the lines of the semiconductor device 1 to the outside protrude outside the package 2, and people, machines, etc. Since the pins 5 are easily touched, there is a risk that the pins 5 may be bent or damaged, or electrostatic damage may occur in the semiconductor device 1.
この発明は、このような従来の技術が有する未解決の課
題に着目してなされたものであり、収容された半導体装
置の各ラインを外部に導出する端子部分の構造を改良す
ることにより、上述した破損や静電破壊等の危険性を低
減することができる半導体装置のパッケージを提供する
ことを目的としている。This invention was made by focusing on the unresolved problems of the conventional technology, and by improving the structure of the terminal portion that leads out each line of the housed semiconductor device to the outside, the invention solves the above-mentioned problem. The purpose of the present invention is to provide a package for a semiconductor device that can reduce the risk of damage caused by electrostatic discharge, damage caused by electrostatic discharge, and the like.
〔課題を解決するための手段］
上記目的を達成するために、本発明は、半導体装置を封
入し且つその半導体装置のラインを外部に導出する端子
を備えたパッケージにおいて、前記端子をパッケージ内
に凹陥させた。[Means for Solving the Problems] In order to achieve the above object, the present invention provides a package that encapsulates a semiconductor device and is provided with a terminal for leading out lines of the semiconductor device to the outside, in which the terminal is placed inside the package. It caved in.
本発明にあっては、端子がパッケージ内に凹陥している
ので、端子自体に外力が加わって破損するようなことは
ないし、人や機械等に触れ難くなるから、運搬や実装の
際に静電破壊が発生ずる危険性が低くなる。In the present invention, since the terminals are recessed inside the package, the terminals themselves will not be damaged by external force and are less likely to be touched by people or machines, so they can be carried and mounted quietly. The risk of electrical damage occurring is reduced.
（実施例〕 以下、この発明の実施例を図面に基づいて説明する。(Example〕 Embodiments of the present invention will be described below based on the drawings.
第１図及び第２図は本発明の一実施例を示した図である
。なお、従来技術の説明で用いた第３図と同様の部位及
び部材には、同じ符号を付し、その重複する説明は省略
する。FIGS. 1 and 2 are diagrams showing an embodiment of the present invention. Note that the same parts and members as those in FIG. 3 used in the description of the prior art are given the same reference numerals, and redundant description thereof will be omitted.
第１図は、゛ト導体装置１を封入した状態のパンケージ
２の部分断面図であり、半導体装置１のラインの内、一
つの信号ラインと、一つのアースラインとを外部に導出
する部分を示している。FIG. 1 is a partial cross-sectional view of the pancase 2 in which the conductor device 1 is enclosed, and shows a portion where one signal line and one ground line among the lines of the semiconductor device 1 are led to the outside. It shows.
同図に示すように、基板４には、金属製のリード線７及
び８が埋設されていて、それらリード線７及び８の内端
はパッケージ２内に露出すると共に、一方のリード線７
の内端はワイヤ６ａを介して半導体装置ｌの信号ライン
に接続され、他方のリード線８の内端はワイヤ６ｂ（一
部省略）を介して半導体装置ｌのアースラインに接続さ
れている。As shown in the figure, metal lead wires 7 and 8 are embedded in the substrate 4, the inner ends of these lead wires 7 and 8 are exposed inside the package 2, and one lead wire 7
The inner end of lead wire 8 is connected to the signal line of semiconductor device l via wire 6a, and the inner end of the other lead wire 8 is connected to the ground line of semiconductor device l via wire 6b (partially omitted).
また、基板４には、基板４下面側に開口し且つ金属製の
有底円筒形の凹陥体９及びＩＯが埋設されていて、一方
の凹陥体９はリード線７の外端に接触し、他方の凹陥体
１０はリード線８の外端に接触している。ここで、本実
施例では、凹陥体９及び１０が、端子を構成している。In addition, in the substrate 4, a recessed body 9 and an IO are buried in the substrate 4, which are opened on the lower surface side of the substrate 4 and are made of metal and have a bottomed cylindrical shape, and one of the recessed bodies 9 contacts the outer end of the lead wire 7, The other concave body 10 is in contact with the outer end of the lead wire 8. Here, in this embodiment, the recessed bodies 9 and 10 constitute a terminal.
そして、基板４の下面には、金属製の接地層１１が設け
られていて、凹陥体ＩＯの開口端部はその接地層１１に
接触している（即ち、凹陥体ｌＯは接地されている）が
、凹陥体９と接地層１１とは、リング状の絶縁体１２に
よって非接触状態となっている。A metal ground layer 11 is provided on the lower surface of the substrate 4, and the open end of the recessed body IO is in contact with the ground layer 11 (that is, the recessed body IO is grounded). However, the recessed body 9 and the ground layer 11 are in a non-contact state due to the ring-shaped insulator 12.
第２図は、絶縁体からなる実装基板１３にパッケージ２
を実装した状態の部分断面図であり、本実施例では、実
装基板１３を裏面側から貫通し且つ先端部が凹陥体９又
は１０に嵌合する金属製の固定ピン１４及び１５によっ
て、パッケージ２を実装基板１３に固定している。FIG. 2 shows a package 2 mounted on a mounting board 13 made of an insulator.
In this embodiment, the package 2 is mounted by metal fixing pins 14 and 15 that penetrate the mounting board 13 from the back side and whose tips fit into the recessed body 9 or 10. is fixed to the mounting board 13.
この際、実装基板１３の裏面に必要な配線を施すと共に
、その配線に接触するように固定とン１４又は１５を貫
通させれば、半導体装置１のラインの外部への導出が容
易に行える。At this time, if necessary wiring is provided on the back surface of the mounting board 13 and a fixing hole 14 or 15 is penetrated so as to contact the wiring, the lines of the semiconductor device 1 can be easily led to the outside.
また、予め凹陥体９及びｌＯの内面にはんだを塗布して
おくと、第２図に示すように固定ピン１４及び１５を凹
陥体９及び１０に嵌合させた後、パッケージ２全体を加
熱すれば、はんだ付けを一度に行うことができ、多くの
手間が省かれる。Furthermore, if solder is applied to the inner surfaces of the concave bodies 9 and 10 in advance, the entire package 2 can be heated after fitting the fixing pins 14 and 15 into the concave bodies 9 and 10 as shown in FIG. For example, soldering can be done all at once, saving a lot of effort.
そして、上記実施例の構成であれば、端子としての凹陥
体９及び１０がパッケージ２の外部に突出していないの
で、それらに外力が加わって破損することはないし、パ
ッケージ２の外部に露出しているのは接地側だけであり
、その他の部分は人や機械等に触れ難いから、静電破壊
の危険性が低減される。With the configuration of the above embodiment, the recessed bodies 9 and 10 serving as terminals do not protrude to the outside of the package 2, so they will not be damaged by external force, and they will not be exposed to the outside of the package 2. The risk of electrostatic damage is reduced because only the ground side is exposed, and other parts are difficult to touch by people or machinery.
さらに、端子（凹陥体９及び１０）がパンケージ２内に
凹陥しているため、基板４の下面に広くて強い接地層１
１を容易に設けることができると共に、半導体装置１の
アースラインを容易に接地することができる。Furthermore, since the terminals (recessed bodies 9 and 10) are recessed in the pan cage 2, a wide and strong ground layer 1 is provided on the lower surface of the board 4.
1 can be easily provided, and the ground line of the semiconductor device 1 can be easily grounded.
なお、上記実施例では、端子としての凹陥体９及び１０
を、パッケージ２の下面側に開口した場合について説明
したが、これに限定されるものではなく、それに代えて
又はそれと共に、パッケージ２の側面側に開口させるこ
とも可能である。In addition, in the above embodiment, the recessed bodies 9 and 10 as terminals are
Although the case where the opening is opened on the lower surface side of the package 2 has been described, the opening is not limited to this, and it is also possible to open on the side surface side of the package 2 instead of or in addition thereto.
〔発明の効果］
以上説明したように、本発明にあっては、半導体装置の
ラインを外部に導出する端子をパッケージ内に凹陥させ
たため、破損や静電破壊等の危険性が低減されるという
効果がある。[Effects of the Invention] As explained above, in the present invention, since the terminals leading out the lines of the semiconductor device are recessed in the package, the risk of damage, electrostatic damage, etc. is reduced. effective.
第１図は本発明の一実施例を示す部分断面図、第２図は
パッケージを実装した状態での部分断面図、第３図は従
来のパッケージを示す断面図である。
■・・・半導体装置、２・・・パッケージ、３・・・キ
ャップ、４・・・基板、６ａ、６ｂ・・・ワイヤ、７，
８・・・リード線、９，１０・・・凹陥体、１１・・・
接地層、１２・・・絶縁体、１３・・・実装基板、１４
．１５・・・固定ピンFIG. 1 is a partial cross-sectional view showing an embodiment of the present invention, FIG. 2 is a partial cross-sectional view showing a package mounted, and FIG. 3 is a cross-sectional view showing a conventional package. ■...Semiconductor device, 2...Package, 3...Cap, 4...Substrate, 6a, 6b...Wire, 7,
8... Lead wire, 9, 10... Concave body, 11...
Ground layer, 12... Insulator, 13... Mounting board, 14
．． 15...Fixing pin
Claims (1)
を外部に導出する端子を備えたパッケージにおいて、前
記端子をパッケージ内に凹陥させたことを特徴とする半
導体装置のパッケージ。(1) A package for a semiconductor device, which encloses a semiconductor device and is provided with a terminal for leading a line of the semiconductor device to the outside, characterized in that the terminal is recessed inside the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25104589A JPH03112155A (en) | 1989-09-27 | 1989-09-27 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25104589A JPH03112155A (en) | 1989-09-27 | 1989-09-27 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03112155A true JPH03112155A (en) | 1991-05-13 |
Family
ID=17216795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25104589A Pending JPH03112155A (en) | 1989-09-27 | 1989-09-27 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03112155A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996012299A1 (en) * | 1994-10-17 | 1996-04-25 | W.L. Gore & Associates, Inc. | Integrated circuit package |
| US5701032A (en) * | 1994-10-17 | 1997-12-23 | W. L. Gore & Associates, Inc. | Integrated circuit package |
| EP0817267A1 (en) * | 1994-03-11 | 1998-01-07 | The Panda Project | Semiconductor package having pins connected to inner layers of multilayer structure |
| US7221830B2 (en) | 2003-06-30 | 2007-05-22 | Tdk Corporation | Method and apparatus for connecting optical transmission module and core position detection method for optical waveguide |
-
1989
- 1989-09-27 JP JP25104589A patent/JPH03112155A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0817267A1 (en) * | 1994-03-11 | 1998-01-07 | The Panda Project | Semiconductor package having pins connected to inner layers of multilayer structure |
| WO1996012299A1 (en) * | 1994-10-17 | 1996-04-25 | W.L. Gore & Associates, Inc. | Integrated circuit package |
| US5525834A (en) * | 1994-10-17 | 1996-06-11 | W. L. Gore & Associates, Inc. | Integrated circuit package |
| US5701032A (en) * | 1994-10-17 | 1997-12-23 | W. L. Gore & Associates, Inc. | Integrated circuit package |
| US7221830B2 (en) | 2003-06-30 | 2007-05-22 | Tdk Corporation | Method and apparatus for connecting optical transmission module and core position detection method for optical waveguide |
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