JPH03108739A - Method of arranging and wiring block in high-density integrated circuit - Google Patents

Abstract

PURPOSE:To achieve minimum total wiring length and compact wiring of blocks automatically and to obtain a method which can determine the aspect ratio of each block automatically by providing specified initial arranging procedure, reassigning procedure, compactform providing procedure, a shape changing procedure, wiring-area allocating procedure and aspect-ratio adjusting procedure, respectively. CONSTITUTION:In a block arranging and wiring method for a high-density integrated circuit by which blocks 1-12 having different sizes are arranged and wired automatically, the following procedures are included. The blocks 1-12 without sizes are linked with springs and a spring model in a mass system formed in this way is used. Thus the initial arrangement is performed in the first procedure. The sizes are imparted for at least parts of the block as circles, and the blocks 1-12 are rearranged so that the overlapped parts between the blocks 1-12 are eliminated in the second procedure. The outer shape is made compact in conformity with a frame 20 of a circuit board in the third procedure. The shapes of the blocks 1-12 are changed into actual shapes in the fourth procesure. The blocks 1-12 are expanded, and wring regions (a) are allocated in the fifth procedure. The aspect ratios of the blocks 1-12 are adjusted in the sixth procedure.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a block placement and wiring method for highly integrated circuits,
In particular, it is suitable for fully automatically arranging blocks of different sizes and determining wiring, which is suitable for use when performing SOG (Sea Of Gate) 7o Abrun and macro cell placement using CAD (Computer Aided Design Device). The present invention relates to a possible block placement and wiring method for highly integrated circuits.

[Conventional technology]

SOG is known as a highly integrated circuit that allows macro cells to be placed and wired in any area within a chip and has a high degree of freedom in design. In this SOG, the arrangement of each macrocell,
When determining the wiring, for example, depending on the size of the predetermined circuit board (frame size, die size, or chip size) of about 4 types,
It is necessary to arrange macrocells having a predetermined size and shape so that the wiring length between the macrocells is minimized. Here, in order to reduce signal transmission delay time and wiring area, it is desirable that the wiring length between macrocells be the minimum, and if the SOG has the same function, the die size,
That is, it is desirable that the chip size is also small. Therefore, without suddenly placing a small transistor,
A hierarchical design method is used in which functions are divided, and areas are first set aside for each large macrocell and then wired, and then small transistors are placed and wired within each area. Even in this hierarchical design method, it is necessary to arrange macrocells with a predetermined size and shape so that the wiring length between macrocells is minimized within a predetermined chip size, and this is a kind of cutout problem. The number of configuration combinations is infinite. For this reason, conventionally, the placement and shape adjustment of macrocells was
This was done manually through trial and error using the interactive graphic screen of the AD development tool, which was time-consuming. As an example of the above-mentioned development tool, for example, Japanese Patent Laid-Open No. 181348/1983 discloses a layout specification storage section, a rough layout determining means, a rough layout information storage section,
An LSI layout design device using a hierarchical layout method is disclosed, which includes a block layout determining means, a block layout information storage section, a chip layout determining means, a chip layout information storage section, and a mask pattern synthesis means. . In addition, very large scale integrated circuits (VL) using the hierarchical design method
As an example of the layout design of SI), for example, [
Information Processing Society of Japan Design Automation Study Group Materials, 18-3 (19
83, 9) proposes a method for semi-automatically performing chip floor planning that performs block-level placement, which is the first stage of layout. This method first uses the AR method (A
ttractive and repulsive
(Force Method), the initial arrangement of blocks is performed using a spring model of a mass point system in which blocks of no size are connected by springs. Next, the size of each block is given as a rectangle corresponding to the actual shape for this arrangement, and the blocks are manually moved through trial and error so that there is no overlap between blocks. Perform block backing processing to In addition, in the latter half of the process, the overlap is removed by manually changing the aspect ratio of the variable-shaped blocks. Furthermore, the area required for inter-block wiring is calculated from inter-block connection information and block position information. On the other hand, IEICE Transactions 89/I VOL, J
72-A No. 1 proposes a block arrangement method in which a mechanical model is set in which an attractive force according to the number of wire connections and a repulsive force according to the overlapping area are applied between blocks. This block arrangement method first uses only the attraction force from the wire connections to arrange blocks 1 to 17 so that the sum of the squares of the wire lengths is the minimum.
is initially arranged within the frame of the die 20 (see FIG. 12). Next, a repulsive force is applied to this arrangement with an initial value of 1/100 of the attractive force, and overlapping is gradually eliminated through repeated calculations until the ratio of the overlapping area to the total block area is 8.2% or less. Blocks 1 to 1 so that
The relative positional relationship of 7 is approximately determined (see Fig. 13). Next, the orientation of each block is considered in order from the block furthest from the center of the placement area (20) (see FIG. 14). Next, the equilibrium position is determined, the orientation of the blocks is considered again, and the layout is determined (see FIG. 15). In addition, with this method, a slight overlap remains that is sufficient to balance the suction force due to the wire connection, so the blocks are expanded to a small length before placement, and the maximum overlap length between blocks is equal to or less than the enlarged amount. By proceeding with the overlap removal until the block becomes , and then returning the block to its original size, as shown in Figure 16,
A method for obtaining a non-overlapping arrangement has also been proposed.

[Task M that the invention seeks to accomplish]

However, in all of the above methods, each block is treated as a rectangle, so it is not easy to move the block. In addition, the latter method does not adjust the aspect ratio (vertical/horizontal ratio) of each block, so it is not always possible to create a compact overall shape, especially when using variable-shaped blocks such as soft macros with variable aspect ratios. Placement may not be achieved. Furthermore, in both methods, in order to eliminate the overlap between blocks that occurred in the initial arrangement,
Since this is a method of shifting the block position within the die frame 20, the block position may be shifted more than necessary in the process of determining the layout, and conditions such as minimum total wiring length and minimum dead space may be violated. It had the following problems. The present invention has been made to solve the above-mentioned conventional problems, and is capable of automatically minimizing the total wiring length, compactly arranging blocks, and automatically determining the aspect ratio of each block. An object of the present invention is to provide a block placement and wiring method for highly integrated circuits.

[Means to achieve the task]

The present invention automatically arranges blocks of different sizes,
In the block placement and routing method for highly integrated circuits for determining wiring, there is a procedure for initial placement using a spring model of a mass point system in which blocks with no size are connected by springs, and a method for determining the size of at least some blocks. Steps to rearrange the blocks so that there is no overlap between blocks by giving the size as a circle, steps to compact the external shape to fit the frame of the circuit board, and change the shape of the block from a circle to the actual shape. The above object is achieved by including a procedure for expanding the blocks to allocate an area for wiring, and a procedure for adjusting the aspect ratio of each block within a permissible range. Further, the size of the block is given as a circle and a rectangle.

[Action and effect]

In the present invention, when rearranging blocks so that there is no overlap between initially arranged blocks, the size of at least some of the blocks (particularly soft blocks with variable aspect ratios) is given as a circle. Therefore, compared to the case where all the blocks are left rectangular in shape as in the conventional example, it is easier to move the blocks when compacting, and the processing time is shortened. Furthermore, since the outer shape is made compact to match the frame of the circuit board while avoiding overlap between the blocks, the blocks can be arranged in the smallest size frame that realizes the same circuit function. Further, after changing the shape of the block from a circle to an actual shape, the block is expanded and a region for wiring is allocated, so that the wiring region can be automatically allocated. In addition, since the aspect ratio of each block is adjusted within the allowable range, it is possible to eliminate overlap and minimize the put space within the given frame, making it possible to compactly fit blocks within the circuit board frame. can be accommodated in Furthermore, a series of operations such as initial placement, chip frame placement, wiring area allocation, and aspect ratio adjustment can be fully automated. Furthermore, if the sizes of the blocks are given as circles and rectangles, more efficient arrangement may be possible.

【Example】

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention applied to an SOG macro cell arrangement will be described in detail below with reference to the drawings. The macro cell placement and wiring device for carrying out this first embodiment includes, for example, as shown in FIG. a central processing unit (CPU) 31 that executes processing according to the present invention; a layout information storage section 38 that stores layout information being processed by the CPU 31; and a processing status of the CPU 31. , and output means 42 for outputting layout information determined by the CPU 31. The CPU 31 takes in necessary information from the layout specification storage unit 30, performs initial arrangement using a spring model of a mass point system in which macro cells whose sizes are ignored and are set to zero are connected by springs, and the result is used as described above. Layout information storage section 3
8, the rough layout determining means 32, the layout specification storage section 30, and the layout information storage section 38, take in necessary information from the layout specification storage section 30 and the layout information storage section 38, and consider the size of the macrocell by giving the size (equivalent to the area of the macrocell) in a circle, In addition to rearranging the blocks so that there is no overlap between the blocks, and considering that the aspect ratio of the macrocell is variable, the external shape is adjusted to the frame of the circuit board (for example, 4 a layout determining means 34 that gradually downsizes the layout according to the type (type) and stores the result in the layout information storage section 38; and the layout specification storage section 30 and the layout information storage section 38.
Incorporating the necessary information from the source, changing the shape of the macrocell from a circle to the actual shape, expanding the macrocell, allocating an area for wiring, and adjusting the aspect ratio of each macrocell within a certain area tolerance. and a layout adjusting means 36 for adjusting the layout. Macro cell placement and wiring according to the first embodiment of the present invention using this macrocell placement and wiring device (macrocells are 1 to 12
12 macros, all of which are soft macros with variable aspect ratios, are executed according to the procedure shown in FIG. That is, first in step 100, a netlist and pad conditions (fixed, free) are retrieved from the layout specification storage section 30.
, macro type (the rough I macro, hard macro with fixed aspect ratio), etc. are input to the rough layerer 1-determining means 32. Next, in step 110, the rough layout determining means 32 uses a spring model of a mass point system in which macro cells with no size are connected by springs to determine, for example, the third
Initial layout as shown in the figure. For this initial arrangement,
For example, in an attraction/reaction spring model as shown in FIG. 4, it is possible to use a balance equation as shown by the solid line A in which only the attraction force is given. Note that the boundary condition is a free boundary, and the shape of the frame is free. Next, the process proceeds to step 120, and based on the initial arrangement determined by the rough layout determining means 32, the layout determining means 34 gives the sizes of all the macro cells in circles, takes the size of the macro cells into consideration, and determines the distance between the macro cells. The macrocells are rearranged so that there is no overlap, and balance is achieved by free boundaries, as shown in FIG. 5, for example. For example, in Fig. 4, when balancing by this free boundary,
A balance equation such as that shown by the solid line C that gives both attractive force and reaction force can be used. Note that the boundary condition is still a free boundary. Next, the process proceeds to step 130, as shown in FIG. 6, where the external shape is gradually made compact to match the chip size 20 (for example, one of four types). When making this compact, for example in FIG. 4, if the distance between the two macro cells 1 and J is greater than or equal to their contact position aij,
Attractive spring model (f” Cij (L
aij)), when the distance L = aB j, it is on the broken line B, and when the distance is less than aij, the quadratic relationship (f”kij
・A reaction force spring model according to aij2/L2) can be used. Note that the boundary condition is the die frame. When a spring model based on this attractive force/reaction force balance is used, it is possible to compactly arrange macro cells within a predetermined frame without compromising the minimum wiring length requirement2. The mechanical model used for the compaction is a spring model with attraction/anti-cabalance and ten-anticabalance as shown by the solid line C in FIG. It is also possible to cut the attraction spring immediately after that and eliminate the problem by balancing the reaction force. Alternatively, a spring model based only on reaction force balance as shown by the solid line in FIG. 4 may be used, and all the attractive springs may be cut to make the spring compact, thereby eliminating overlaps and dead spaces. After the compaction is completed in step 130, the process proceeds to step 140, where the layout adjustment means 36 performs the following steps:
As shown in FIG. 7, the shape of the macrocell is changed from a circle to an actual shape (here, a rectangle). When changing the shape, the boundary condition may be a die frame, and the balance equation may be a reaction force spring, for example. Next, the process proceeds to step 150, as shown in FIG. 8, by expanding the macrocells and allocating an area for wiring (the shaded area in the figure) around each macrocell. When allocating this wiring area, the boundary condition is the die frame, and a balance equation using only the reaction force can be used. Next, the process proceeds to step 160, and as shown in FIG. 9, the layout is determined by adjusting the aspect ratio of each macro cell (soft macro) within a fixed area tolerance. In this case, too, the boundary condition is the die frame, and since it is a fine adjustment, the balance equation of only the reaction force can be used without considering the attractive force. Note that if a hard macro whose block shape cannot be changed is included, the aspect ratio of the hard macro is fixed except for the wiring area. After step 160, the process proceeds to step 170, where the determined macrocell position is output from the output means 42. Next, a second embodiment of the present invention will be described in detail. In this second embodiment, in the same procedure as the first embodiment shown in FIG. 1, in step 120, as shown in FIG. The size is given, for example, by a rectangle corresponding to the actual shape, and balance is achieved by free boundaries. Next, the process proceeds to step 130, where the external shape is made compact to match the chip size 20, as shown in FIG. The subsequent steps are the same as those in the first embodiment, so the explanation will be omitted. According to this second embodiment, the size of some macrocells is given as a rectangle instead of a circle, so efficient arrangement is possible, especially when the aspect ratio of the macrocell is fixed. . Note that in all of the above examples, the present invention is applicable to SO
Although the present invention has been applied to the G macrocell arrangement, the scope of application of the present invention is not limited thereto, and it is clear that it can be similarly applied to general block arrangements.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the procedure of a first embodiment of the block placement and wiring method according to the present invention, and FIG. 2 is a block diagram showing the basic configuration of an apparatus for implementing the first embodiment. , Fig. 3 is a line diagram showing an example of the display screen at the end of the initial arrangement in the first embodiment, Fig. 4 is a line diagram showing the dynamic model used in the first embodiment, and Fig. 5 is a diagram showing an example of the display screen after free boundary balance in the first embodiment, FIG. 6 is a diagram showing an example of the display screen after compaction, and FIG. 7 is a diagram showing an example of the display screen after shape change. FIG. 8 is a line diagram showing an example of a display screen after wiring area allocation; FIG. 9 is a line diagram showing an example of a display screen after aspect ratio adjustment; FIG. 10 is a line diagram showing an example of the display screen after free boundary balance in the second embodiment of the present invention, FIG. 11 is a line diagram showing an example of the display screen after compaction, and FIGS. FIG. 16 is a diagram for explaining the procedure of processing 6 in the conventional example. 28... Input means, 30... Layout specification storage section, 31... Central processing unit (CPU), 32... Rough layout determining means, 34... Layout determining means, 36... Layout adjustment Means, 3.8... Layout information storage section, 40... Display, 42... Output means.

Claims (2)

[Claims] (1) In a block placement and routing method for highly integrated circuits that automatically places blocks of different sizes and determines wiring, a spring model of a mass point system is used, in which blocks of no size are connected by springs. the initial arrangement procedure, the procedure to give the size of at least some blocks as a circle, and the procedure to rearrange the blocks so that there is no overlap between the blocks, and the procedure to compact the external shape to fit the circuit board frame. changing the shape of the blocks from circles to actual shapes; expanding the blocks to allocate space for wiring; and adjusting the aspect ratio of each block, within tolerance. , A block placement and routing method for a highly integrated circuit, comprising: (2) A block placement and wiring method for a highly integrated circuit according to claim 1, characterized in that the size of the block is given as a circle and a rectangle.