JPH0760856B2 - Block layout and wiring method for highly integrated circuits - Google Patents

Description

Detailed Description of the Invention [Industrial applications]

The present invention relates to a block layout and wiring method for highly integrated circuits,
In particular, it is possible to fully automatically arrange blocks of different sizes and determine the wiring, which is suitable for use when performing SOG (Sea Of Gate) floorplans and macrocell placement with CAD (Computer Assisted Design Device). The present invention relates to a possible block layout and wiring method for a highly integrated circuit.

2. Description of the Related Art SOG is known as a highly integrated circuit in which macrocells can be arranged and wired in an arbitrary area in a chip and which has a high degree of design freedom. In this SOG, when deciding the arrangement and wiring of each macro cell, the wiring length between macro cells should be minimized within the frame size (die size or chip size) of a predetermined circuit board of, for example, about 4 types. , Predetermined size,
It is necessary to arrange a macro cell having a shape. Here, in order to reduce the delay time of signal transmission and the wiring area, it is desirable that the wiring length between the macro cells is minimum, and if the SOG has the same function, the die size, that is, the chip size is also small. Is desirable. Therefore, without suddenly placing a small transistor,
The function is divided, and wiring is first made through a region in units of large macro cells, and then a small transistor is placed in the wiring. A hierarchical design method is used. Even in this hierarchical design method, it is necessary to arrange macrocells having a predetermined size and shape so that the wiring length between macrocells is within a predetermined chip size, which is a type of planing problem. The number of unions is unlimited. For this reason, conventionally, macro cell placement and shape adjustment are
Using the interactive graphical screen of the development tool for CAD, I was manually performing trial and error, and the work was time consuming. An example of the above-mentioned development tool is, for example,
63-181348, a layout specification storage unit, a rough layout determination unit, a rough layout information storage unit, a block layout determination unit, a block layout information storage unit, a chip layout determination unit, and a chip layout information storage unit, There is disclosed a layout designing apparatus for a hierarchical layout type LSI, which is provided with a mask pattern synthesizing means. In addition, a very large scale integrated circuit (VLS
As an example of the layout design of I), for example, "Information Processing Society of Japan Design Automation Study Group Material, 18-3 (1983, 9)"
A method for semi-automatically performing a chip floor plan, which is the first stage of layout and is arranged at a block level, has been proposed. This method is based on the AR method (Attractive and R
The epulsive force method) is used to perform the initial placement of the blocks using a mass-type spring model in which blocks with no size are connected by springs. Then, the size of each block is given to this arrangement as a rectangle corresponding to the actual shape, and the blocks are manually moved by trial and error so that there is no overlap between the blocks, and the blocks that are far apart are brought into close contact. A block packing process is performed. Further, in the latter half of the processing, the overlap is taken by manually changing the aspect ratio of the variable shape block. Further, the area required for wiring between blocks is calculated from the connection information between blocks and the position information of the blocks. On the other hand, IEICE Transactions 89/1 VOL.J72-A No.
In block 1, a block placement method is proposed in which a dynamic model is set in which a suction force according to the number of connections and a repulsive force according to the overlapping area are applied between the blocks. In this block arranging method, first, the blocks 1 to 17 are initially arranged in the frame of the die 20 so that the sum of squares of the wiring length is minimized only by the suction force due to the connection (see FIG. 12). Then for this arrangement,
The repulsive force is applied with 1/100 of the suction force as the initial value, and the overlap is gradually eliminated by repeated calculation so that the ratio of the overlap area to the total block area is 8.2% or less. Approximately determine the relative positional relationship of (see Figure 13). Next, the orientation of each block is examined in order from the block farthest from the center of the arrangement area (20) (14th block).
See figure). Then, the equilibrium position is obtained, the direction of the block is examined again, and the layout is determined (see FIG. 15). In this method, since there is a slight overlap that balances the suction force due to the connection, the blocks are expanded to a slight length before placement, and the maximum overlap length between the blocks is less than the expansion amount. There is also proposed a method of obtaining an arrangement without overlapping as shown in FIG. 16 by advancing removal of overlapping until it becomes uniform and then returning the block to its original size.

[Problems to be achieved by the invention]

However, in each of the above methods, each block is handled in a rectangular shape, so that the movement is not easy. In the latter method, the aspect ratio (aspect ratio) of each block is not adjusted. Therefore, especially when a variable shape block such as a soft macro with a variable aspect ratio is used, it is not always compact as a whole. The placement may not be achieved. Furthermore, both methods eliminate the overlap between blocks that occurs in the initial placement.
Since it is a method of shifting the block position within the die frame 20, the block position may be displaced more than necessary in the process of layout determination, and the conditions such as the minimum total wiring length and the minimum dead space may collapse. I had a problem. The present invention has been made to solve the above-mentioned conventional problems, and it is possible to automatically perform the minimum ratio of the total wiring length and the compact arrangement of the blocks, and automatically determine the aspect ratio of each block. An object of the present invention is to provide a block placement and routing method for a highly integrated circuit that is possible.

[Means for achieving the object]

The present invention automatically arranges blocks of different sizes,
In a block placement and routing method of a highly integrated circuit for determining the wiring, a procedure for initial placement using a mass-type spring model in which blocks having no size are connected by a spring,
Give at least part of the block size in circles, relocate the blocks so that there is no overlap between the blocks, the procedure to make the outline compact to fit the frame of the circuit board, and the shape of the block By changing the shape of the block from a circle to an actual shape, expanding the block, allocating a region for wiring, and adjusting the aspect ratio of each block within an allowable range. Has been achieved. The size of the block is given by a circle and a rectangle.

[Action and effect]

In the present invention, the size of at least some of the blocks (particularly, soft blocks with variable aspect ratio) is given by a circle when rearranging the blocks so that the blocks initially arranged do not overlap each other. Therefore, as compared with the case where all the blocks have a rectangular shape as in the conventional example, the movement during compaction is easier and the processing time is shortened. Further, since the outer shape is adapted to the frame of the circuit board to be compact while avoiding the overlap between the blocks, the blocks can be arranged in the frame of the smallest size for realizing the same circuit function. Further, since the block shape is changed from a circle to an actual shape and the block is expanded to allocate the area for wiring, the wiring area can be automatically allocated. Also, since the aspect ratio of each block is adjusted within the allowable range, it is possible to eliminate overlap and minimize the dead space within a given frame, making the block compact within the circuit board frame. Can fit in. In addition, initial placement, chip frame placement, wiring area assignment,
A series of operations for adjusting the aspect ratio can be fully automated. Further, if the block size is given by a circle or a rectangle, more efficient arrangement may be possible.

【Example】

A first embodiment of the present invention applied to SOG macro cell arrangement will be described in detail below with reference to the drawings. A macro cell placement and routing apparatus for carrying out this first embodiment is, for example, as shown in FIG. 2, an input means 28 for inputting necessary information and a layout specification required for determining placement and routing of macro cells. A layout specification storage unit 30, a central processing unit (CPU) 31 for executing the processing according to the present invention, a layout information storage unit 38 for storing layout information being processed by the CPU 31, and a processing status of the CPU 31. Is displayed, and an output means 42 for outputting the layout information determined by the CPU 31. The CPU 31 fetches necessary information from the layout specification storage unit 30, connects the macrocells ignoring the size with zeros by springs, and makes an initial arrangement using a spring model of a mass system, and the result is Rough layout determining means 32 stored in the layout information storage unit 38, necessary information is fetched from the layout specification storage unit 30 and the layout information storage unit 38, and the size (corresponding to the area) of the macrocell is given in a circle to Considering the size, rearrange the blocks so that there is no overlap between the blocks, and consider the fact that the aspect ratio of the macrocell is variable. A layout determining unit 34 that gradually reduces the size of the frame (for example, four types) and stores the result in the layout information storage unit 38. , The layout specification storage unit
30 and necessary information from the layout information storage unit 38 are fetched, the shape of the macro cell is changed from a circle to an actual shape, the macro cell is expanded, and a region for wiring is allocated. Then, the layout adjusting means 36 for adjusting the aspect ratio of each macro cell is provided. Using this macro cell placement and routing device, the macro cell placement and routing according to the first embodiment of the present invention (the macro cells are 1 to 12
It is assumed that there are 12 soft macros with variable aspect ratios) and the soft macros are executed according to the procedure shown in FIG. That is, first, in step 100, the layout specification storage unit 3
From 0, a net list, pad conditions (fixed, free), macro type (the soft macro, hard macro with fixed aspect ratio) and the like are input to the rough layout determining means 32.
Next, at step 110, the rough layout determining means 32 uses a spring model of a mass system in which macrocells having no size are connected by springs to perform initial arrangement, for example, as shown in FIG. At the time of this initial arrangement, for example, in the attractive force / reaction force spring model as shown in FIG. 4, it is possible to use a balance equation as shown by the solid line A in which only attractive force is applied. The boundary condition is a free boundary, and the shape of the frame is free. Next, in step 120, based on the initial layout determined by the rough layout determining means 32, the layout determining means 34 gives the sizes of all the macro cells in circles and considers the macro cell sizes. The macro cells are rearranged so that there is no overlap between the two, and the free boundaries are balanced as shown in FIG. 5, for example. For the balance by the free boundary, for example, in FIG. 4, a balance equation as shown by a solid line C to which both attractive force / reaction force is applied can be used. The boundary condition is also a free boundary. Next, in step 130, as shown in FIG. 6, the outer shape is gradually made compact according to the chip size 20 (for example, any of four types). To make this compact, for example, in FIG. 4, the distance L between the two macro cells i and j is L.
, If the contact positions are a _ij or more, the solid line A
Using the attractive spring model (f = −c _ij (L−a _ij )) according to, when the distance L = a _ij is on the broken line B,
When the distance L is less than a _ij , a reaction force spring model that follows the quadratic relationship (f = k _ij · a _ij ² / L ² ) as shown by the solid line D can be used. The boundary condition is a die frame. When the spring model based on this attractive force / reaction force balance is used, the macro cell can be compactly arranged in a predetermined frame without breaking the requirement of the minimum wiring length. As the mechanical model used for the compactification, a spring model based on the attractive force / reaction force balance + reaction force balance as shown by the solid line C in FIG. Immediately after that, the attractive spring can be cut to eliminate it by the reaction force balance.
Alternatively, the spring model based only on the reaction force balance as shown by the solid line D in FIG. 4 may be used to cut all the attraction springs to make them compact and eliminate the overlap and dead space. Step 1 after compaction by step 130
Proceeding to step 40, the layout adjusting means 36 changes the shape of the macro cell from a circle to an actual shape (here, a rectangle) as shown in FIG. In changing the shape, the boundary condition may be a die frame, and the balance equation may be a reaction force spring, for example. Next, in step 150, as shown in FIG. 8, the macrocell is expanded to form an area for wiring (hatched area in the figure).
To around each macrocell. Also in this wiring area allocation, the boundary condition is the die frame, and the balance equation of only the reaction force can be used. Next, in step 160, as shown in FIG. 9, the layout is determined by adjusting the aspect ratio of each macro cell (soft macro) within the allowable range of constant area. Also in this case, the boundary condition is the die frame, and since the fine adjustment is performed, the balance equation of only the reaction force can be used without considering the attractive force. When a hard macro whose block shape cannot be changed is included, the aspect ratio of the hard macro is fixed except for the wiring area. After the end of step 160, the process proceeds to step 170, and the determined position of the macro cell is output from the output means 42. Next, a second embodiment of the present invention will be described in detail. In the second embodiment, in the same procedure as in the first embodiment shown in FIG. 1, in step 120, as shown in FIG.
The size of (0) is given by, for example, a rectangle corresponding to the actual shape to balance the free boundary. Next, step
Proceed to 130 and set the external shape to chip size 20 as shown in Fig. 11.
To make it compact. The subsequent procedure is the same as that of the first embodiment, and therefore the description is omitted. According to the second embodiment, the size of some of the macrocells is given as a rectangle instead of a circle. Therefore, particularly when the aspect ratio of the macrocells is fixed, efficient placement is possible. . In each of the above examples, the present invention is based on SOG.
However, the scope of application of the present invention is not limited to this, and it is obvious that the invention can be similarly applied to general block arrangement.

[Brief description of drawings]

FIG. 1 is a flow chart showing a procedure of a first embodiment of a block layout and wiring method according to the present invention, and FIG. 2 is a block diagram showing a basic configuration of an apparatus for carrying out the first embodiment. FIG. 3 is a diagram showing an example of a display screen at the end of the initial placement in the first embodiment, FIG. 4 is a diagram showing a mechanical model used in the first embodiment, and FIG. FIG. 6 is a diagram showing an example of a display screen after free boundary balancing in the first embodiment, FIG. 6 is a diagram showing an example of a display screen after being made compact, and FIG. 7 is a display screen similarly after being changed in shape. Fig. 8 is a diagram showing an example of a display screen after wiring area allocation, Fig. 9 is a diagram showing an example of a display screen after similarly adjusting the aspect ratio, Fig. 10 Is a diagram showing an example of a display screen after free boundary balancing in the second embodiment of the present invention, and FIG. Diagram showing an example of a display screen after the shaft compaction, FIG. 12 through FIG. 16 is a diagram for explaining the processing procedure in the conventional example. 28 …… input means, 30 …… layout specification storage section, 31 …… central processing unit (CPU), 32 …… rough layout determining means, 34 …… layout determining means, 36 …… layout adjusting means, 38 …… layout Information storage, 40 ... Display, 42 ... Output means.

Claims (2)

[Claims] 1. A mass-type spring model in which blocks having no size are connected by a spring in a block layout wiring method of a highly integrated circuit for automatically arranging blocks of different sizes and determining wiring. Use the procedure for initial placement, and the size of at least some blocks in circles to relocate the blocks so that there is no overlap between blocks, and adjust the outline to the frame of the circuit board. Steps to make it compact, steps to change the shape of the block from a circle to the actual shape, steps to inflate the block to allocate area for wiring, and adjust the aspect ratio of each block within the allowable range. A block placement and routing method for a highly integrated circuit, comprising: 2. The block arranging and wiring method for a highly integrated circuit according to claim 1, wherein the size of the block is given by a circle and a rectangle.