JPH03108367A - Integrated circuit - Google Patents

Abstract

PURPOSE:In a integrated circuit which has plural capacity elements made into IC, to remove the capacitance ratio error due to parasitic capacity so as to obtain a circuit high in capacitance ratio accuracy by proportioning the parasitic capacity arising at the intersection between the wiring of the upper electrode of the capacity element and the lower electrode to the capacitance of each capacity element. CONSTITUTION:In an integrated circuit which has an operational amplifier AMP, a switch SW, an input terminal IN, an output terminal OUT, and two integrated capacity elements C1 and C2 wherein the ratio accuracy of capacitance is required, the total areas of elements C1 and C2 are prescribed as follows. That is, the areas of the upper electrode 1 and the lower electrode 2 are specified respectively to be proportional to the capacitances C1 and C2, and at this intersection 3 between them, a connecting wiring 5 for drawing out upper electrodes 1, which are in the same shape and form a pair in the opposite direction of 180 deg., is provided. By doing it this way, the capacitance ratio error by parasitic capacity vanishes, and the effect of slippage in alignment of a mask used in making vanishes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used in integrated circuits, and particularly relates to integrated circuits including capacitive elements that require relative accuracy.

〔overview〕

The present invention provides an integrated circuit having an integrated capacitive element that requires relative accuracy of capacitance values, wherein the capacitive element has an upper electrode and a lower electrode whose total area is proportional to each capacitance value. By including an intersection with the electrode and a connection wiring that leads the upper electrode to the outside, which are provided in pairs in the same shape and 180 degrees opposite directions, the influence of parasitic capacitance due to the intersection and misalignment is eliminated, A capacitive element having high specific accuracy can be obtained.

[Conventional technology]

Semiconductor integrated circuits that require capacitance ratio accuracy include integrators and switched capacitor circuits. Here, a switched capacitor filter will be explained as an example.

FIG. 4 shows a circuit diagram of a first-order switched capacitor low-pass filter. In Figure 4, IN is an input terminal, O
UT is an output terminal, AMP is an operational amplifier, C, , C, are capacitive elements (capacitance values are also assumed to be CI and C2), and SW is a switch. Here, C,=0.2 PF, C2=2
PF.

FIG. 5 is a mask pattern diagram showing an example of a conventional semiconductor integration port b;i in which the circuit shown in FIG. 4 is integrated. Fifth
In the figure, IN is an input terminal, OUT is an output terminal, and AM
P is an operational amplifier, C, , C, is a capacitive element, SW is a MOS
) A switch constituted by a transistor, l is a wiring.

The transfer function of the low-pass filter in Figure 4 is given by,
The characteristics are determined by the ratio Cr/C2 of the capacitances C,,C,.

In this way, when integrating a semiconductor device in which the relative accuracy rather than the absolute value of the capacitance value is a problem, a mask pattern is designed by connecting unit capacitances in parallel as shown in FIG. This method has the advantage that errors in planar processing accuracy do not become capacitance ratio errors.

Another cause of the capacitance ratio error is the parasitic capacitance that occurs at the intersection 3 between the wiring of the upper electrode 1 (section 22i) of the capacitive element and the lower electrode 2 (section 22i).

In order to explain parasitic capacitance, the capacitive element C in FIG.
Part 3 is shown in FIG. In FIG. 6, C1 is a capacitive element, l is a wiring of the upper electrode 1, and 4 is a contact connecting the wiring l and the upper electrode 1 of the capacitor C1. When integrating a capacitive element, the intersection 3 between the wiring 1 of the upper electrode 1 and the lower electrode 2 of the capacitive element (the blacked out area in Figure 6, and reference numbers are given only to representative parts in Figure 5). Parasitic capacitance occurs in the Assuming that the width of the wiring 1 is II, the length of the intersection 3 between the wiring 1 and the lower electrode 2 is 12, and the unit capacitance is 0.4 Xl0-'PF/2, then A.

When = 12 = 2.5μ, the capacitance value is 0.4 x 1
0-' x 2.52=0.00025PF.

Regarding the capacitive element CI that patterns the switched capacitor low-pass filter shown in FIG. 4 as shown in FIG. 5, the intersection 3 is! ! , x12 is present at one location, and the capacitive element C
Regarding 2, there are 14 locations of llXβ2. Therefore, the parasitic capacitance of capacitive element CI is 0.00025PF, and the parasitic capacitance of capacitive element C2 is 0.00025 X14=0.00
35PF, and the capacitance value is C'+ =0.20025pt''C'2 =2.0035PF.

Furthermore, misalignment of the mask between the upper electrode 1 and the lower electrode 2 occurs, and as shown in FIG.
Consider the case where 2 is formed. FIG. 7 shows only the capacitance and wiring portions of FIG. 5. In Figure 7, l, l
lS β, 2 and C3 represent the length in the X-axis direction of the intersection 3 between the wiring l of the upper electrode 1 and the lower electrode 2, and 1, 1, f
, 2 and ly3 represent the lengths in the y-axis direction. Now, l□=j'y+=1.25M1.1-2=i
y2=2.5μ■, l X3 = l y3=3.75
Let it be μm. At this time, the parasitic capacitance of the capacitive element CI is 0.
000125PF, the parasitic capacitance of capacitive element C2 is 0.0
0025 x13+0.000125=0.0033
75PF, and the capacitance value is C'r = 0.200125
P.F.

C'z =2.003375PF For the desired capacitance ratio c, /C2=0.1, c'+ /c
'2=0.09989, 9.56 x 10-'
This results in a very large gain error of dB.

[Problem that the invention seeks to solve]

Although the conventional integrated circuit described above requires high capacitance ratio accuracy, it is affected by parasitic capacitance that occurs at the intersection between the upper electrode wiring and the lower electrode of the capacitive element, making it difficult for the circuit design characteristics to match. There are disadvantages that cannot be obtained.

An object of the present invention is to provide an integrated circuit having a capacitive element with high precision in capacitance ratio by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides an integrated circuit having a plurality of integrated capacitance elements, wherein the capacitance elements include an intersection between an upper electrode and a lower electrode, the total area of which is proportional to the capacitance value of each; It is characterized in that it includes a connection wiring for leading the upper electrodes, which are arranged in pairs in the same shape and 180 degrees opposite directions, to the outside.

becomes.

[Effect]

Since the total area of the intersection between the upper electrode wiring and the lower electrode has a size proportional to its capacitance value,
The value of the capacitance ratio CI/C2 is kept constant regardless of the parasitic capacitance caused by the intersection. In addition, since the external wiring of the lower electrode is provided in pairs in 180-degree opposite directions, even if misalignment of the mask occurs, the wiring of the external wiring will also shift in the vertical and horizontal directions, resulting in As such, its area does not change, and its capacitance value remains constant.

Therefore, it is possible to eliminate the influence of parasitic capacitance due to intersections and misalignment, and achieve high capacitance ratio accuracy.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a mask pattern diagram showing a first embodiment of the present invention, in which the first-order switched capacitor low-pass filter of FIG. 4 is integrated.

The present embodiment includes an operational amplifier AMP, a switch SW, an input terminal IN, an output terminal OUT, and two integrated capacitor elements C1 and C2 (the capacitance value of which is also C3 and C2), in which the capacitive elements C8 and C2 are provided as upper electrodes whose total area is proportional to the capacitance values CI and C2, respectively. 1 ([SS part) and lower electrode 2 (I221 part)
and a connecting wiring 5 for leading out the upper electrodes 1, which have the same shape and are provided in pairs in 180-degree opposite directions. In the figure, reference numbers are attached only to representative parts.

Next, the capacitance ratio C1/C2 of the capacitive elements C1 and C2 of the present embodiment is calculated.

As in the case of the conventional example described above, the numerical values that serve as the basis for calculation are as follows: Width of wiring l is IIs Length of intersection 3 is 12, Rr
= j! 2 = 2.5μC11, and the unit capacity is 0.4 x 10-'PF/am2.

There are two intersections 3 in the capacitive element CI and 20 in the capacitive element C2, and their total area is equal to the capacitance value (C, = 0
．． 2PP, C2=2PF).

That is, the parasitic capacitance of the capacitive element C1 is 2,5 I2.
5 xO, 4Xl0-' x 2 = 0.0005PF
Therefore, the parasitic capacitance of capacitive element C2 is 2, 5 I2.5 Xo, 4 Xl0-' X20=
It becomes 0.005PF.

Therefore, the capacitance value is c;=0.2005PFSC;=2.005PF, and the capacitance ratio c,/C2=1/10 is realized.

Also, consider a case where misalignment of the mask occurs and a capacitance is formed as shown in FIGS. 2(a) and 2(b).

All the symbols in FIG. 2 are the same as in FIG. 7 of the conventional example described above. That is, I X1% Rx2.183 and l Y I% IY 2,ly are the lengths of the intersection 3 in the X direction and the X direction, and 1x+ = 1271 = 1.25p.

L2=fy2=2.5μm, i! ,=1! , +=3.
75 is a fake, the parasitic capacitance of the capacitive element CI is 1 +
x(1y++ 1yz) xo, 4xlO-'=0.0
The parasitic capacitance of the 005PF capacitive element C2 is H! +x(Jy++Jy3)I4 10j! +X1y2X4+j! , Xβ112 I83 I
0.4 x 10'=0.005PF, and it can be seen that it is not affected by misalignment of the mask.

FIG. 3 is a mask pattern diagram showing a second embodiment of the present invention.

FIG. 3 is also a patterned version of the circuit diagram shown in FIG. 4, but unlike the first embodiment shown in FIG. 1, the semiconductor integrated circuit of the second embodiment uses parallel connection of unit capacitance. Not yet. This is the case when realizing a capacity smaller than the unit capacity, or when realizing a fraction that cannot be represented by the unit capacity.

In FIG. 3, parts corresponding to those in FIG. 1 are given the same reference numerals. Also, 4 is a contact, WI is a capacitive element C
The wiring width of the upper electrode 1 of I and W2 is the wiring width of the upper electrode 1 of the capacitive element C2.

For example, C+ =0. When IPF SC2=0.5PF,! ! If I=lySW, :W2=1:5, the capacitance ratio including parasitic capacitance is C,/C2=115. Furthermore, as shown in FIG. 3, when the wiring of the upper electrode 1 is drawn out to the outside of the lower electrode 2, the wiring of the upper electrode 1 and the lower It is possible to prevent the parasitic capacitance generated at the intersection 3 with the electrode 2 from changing due to misalignment of the mask.

Although the above description deals with a semiconductor integrated circuit as an integrated circuit, the same applies to a hybrid integrated circuit in which a capacitive element is formed of a thin film or a thick film.

〔Effect of the invention〕

As explained above, the present invention reduces the capacitance ratio error caused by the parasitic capacitance by making the parasitic capacitance that occurs at the intersection between the wiring of the upper electrode and the lower electrode of the capacitor constituting an integrated circuit proportional to each capacitance value. In addition, when the upper electrode wiring is drawn out to the outside of the lower electrode, the same number of wiring lines and the same shape are drawn out in pairs in 180° opposite directions to prevent the effects of misalignment of the mask and improve the capacitance ratio accuracy. This has the effect of realizing highly integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a mask pattern diagram showing the configuration of a first embodiment of the present invention. FIGS. 2(a) and 2(a) are mask pattern diagrams also showing a case where misalignment of the mask occurs in the capacitive element portion of FIG. 1. FIG. 3 is a mask pattern diagram showing the configuration of a second embodiment of the present invention. FIG. 4 is a circuit diagram of a first-order low-pass filter. FIG. 5 is a mask pattern diagram showing the configuration of a conventional example. FIG. 6 is an enlarged view of the capacitive element 01 portion in FIG. 5. FIG. 7(a) and FIG. 7(a) are mask pattern diagrams showing a case where misalignment of the mask occurs in the capacitive element portion of FIG. 5. l...upper electrode, 2...lower electrode, 3...intersection, 4...contact, 5...connection wiring, AMP...
・Operation amplifier, C1, C2...capacitive element, IN...
Input terminal, OUT...output terminal, SW...switch,! ... Upper electrode wiring, I2. , W, SW2... Wiring width, A2, f,, l x8, IK2.183, βY,
Ll, β, 2, l, 3... Length of intersection. 3

Claims (1)

[Claims] 1. In an integrated circuit having a plurality of integrated capacitance elements, the capacitance elements include an upper electrode and a lower electrode whose total area is proportional to each capacitance value. 1. An integrated circuit comprising: an intersection; and connection wiring for leading the upper electrodes to the outside, which are provided in pairs in the same shape and 180 degrees opposite directions.