JPH03108314A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH03108314A JPH03108314A JP1246129A JP24612989A JPH03108314A JP H03108314 A JPH03108314 A JP H03108314A JP 1246129 A JP1246129 A JP 1246129A JP 24612989 A JP24612989 A JP 24612989A JP H03108314 A JPH03108314 A JP H03108314A
- Authority
- JP
- Japan
- Prior art keywords
- patterning
- film
- resist
- entire surface
- resist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000059 patterning Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 abstract description 7
- 238000003848 UV Light-Curing Methods 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000007943 implant Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
Landscapes
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
〔産業上の利用分野〕
本発明は、半導体素子、特に感光性材料(光レジスト)
を用いて、エツチングによりパターニングを行うような
半導体素子の製造方法に関するものである。
〔発明の概要J
本発明は、半導体素子の製造法において、レジストの重
ねパターニングを可能にするための技術に関しており、
具体的には、紫外線照射ベーキング(UVキエア)を用
いて、重ねパターニングが可能となることを示したもの
である。[Industrial Application Field] The present invention relates to semiconductor devices, particularly photosensitive materials (photoresists).
The present invention relates to a method of manufacturing a semiconductor device in which patterning is performed by etching. [Summary of the Invention J The present invention relates to a technique for enabling overlapping patterning of resist in a method of manufacturing a semiconductor device,
Specifically, it was shown that overlapping patterning is possible using ultraviolet irradiation baking (UV irradiation baking).
第2図(a)〜(C)に重ねパターニングを行なわない
従来の半導体素子の製造方法を示す、ここでは下層レジ
スト20と上層レジスト21の2層のパターンの関係が
示しである。つまり第2図(a)において、レジスト2
0のパターンを用いて窒化膜22がエツチングによりパ
ターニングされたあとに、レジスト20は1度除去され
て、第2図(b)の状態となる。この状態でレジスト2
1をこの上からパターニングして、イオンインプラ24
を行い、第2図(C)に示すようにインプラ領域25を
形成していた。
〔発明が解決しようとする課題l
第2図(C)におけるインプラ領域25を見ると、第2
図(a)のレジスト20の領域にはイオンインフラがさ
れていない、よって第2図(a)のレジスト20を除去
する必要はないことが分かる6本発明は、この無駄な工
程が存在するという課題を解決しようとするものである
。
〔課題を解決するための手段J
上記課題を解決するために、本発明では紫外線照射ベー
キング(UVキュア)を用いてレジストを硬化させ、レ
ジストの重ねパターニングを行う、ここでUVキュアと
は、紫外線をレジストに照射しながら、同時に熱処理を
行うもので通常はレジストの耐熱性を高めるために用い
られるものである。
〔作用1
本発明による半導体素子の製造工程によれば、下層レジ
ストがパターニングされた状態で、下層レジストにUV
キュアをかける。これにより、レジストの上にレジスト
を塗っても、下層のレジストのパターンの形は崩れず、
安定に塗布することができる。するとレジストの重ねパ
ターニングが可能となり、1度レジストを除去するとい
う無駄な工程を省くことができる。
〔実施例J
実施例1
第1図(a)〜(f)に本発明による半導体素子の製造
方法の工程順断面図を示す。
まず第1図(a)のように、Si基板lの上にSi窒化
膜な全面に堆積する0次に第1図(b)のように下層レ
ジスト3をパターニングして残し、窒化112をエツチ
ングして下層レジスト3と同じ形に残す0次に第1図(
b)の状態でUVキュアをかける。このときのUVキュ
アのプログラムを第3図及び第4図に示した。ここで第
3図は温度のプログラムであり、第4図は紫外線の照射
強度に対するプログラムである0次に第1図(C)のよ
うに上層レジスト4を下層レジスト3の上から重ねパタ
ーニングして、この状態でイオンインプラ6を行い、フ
ィールドインプラ領域5を作る0次にレジスト3.4を
すべて除去して、酸化を行う、すると第1図(d)のよ
うに、窒化膜2のないところだけが酸化される1次に第
1図(e)のように窒化膜2を除去する。そのあとは第
1図(f)に示した素子を以下の順序で作る。
まず、ポリシリコン8を、全面堆積してパターニングす
ることにより作り、次にソース・トレインインプラ9を
作り、中間絶縁膜10を全面堆積したあと、コンタクト
ホールlOをパターニングする。そしてAI配線12を
AIの全面堆積とパタニングによって作る。
なお、ここでは、UVキュアの効果を確かめるために2
枚の基板を用意し工程を基板毎に変えた。つまり、片方
は実施例1と全く同じであるが1片方は第1図(b)の
状態でUVキュアをかけずに第1図(C)のレジスト4
を塗布した。
ここで用いたUVキュアのプログラムは実施例1と同じ
第3図及び第4図であり、これから最高温度が170℃
であることがわかる。
その結果、UVキュアを施さない基板は、第1図(C)
の下層レジスト3の形が崩れてしまい、あとの工程に進
めないことが分った。
実施例2
本例では、実施例1と同じ工程を通したが、第1図下層
レジスト3の厚みの変化を工程の区切り毎に測定した。
その結果が以下の通りである。
下層レジスト3現像後 1.1Mm下層レジ
スト3UVキュア後 1.05Mm上層レジスト4
現像後 1.05Mmこれから、上層レジス
ト4を露光、現像しても下層レジスト3はほとんど膜減
りしないことが明らかとなった。
〔発明の効果J
以上の実施例で示したように本発明によれば、安定に重
ねパターニングすることができ、これにより簡明な工程
を実現することができる。FIGS. 2A to 2C show a conventional method of manufacturing a semiconductor device without overlapping patterning. Here, the relationship between the patterns of two layers, a lower resist 20 and an upper resist 21, is shown. In other words, in FIG. 2(a), resist 2
After the nitride film 22 is patterned by etching using the pattern 0, the resist 20 is removed once, resulting in the state shown in FIG. 2(b). In this state, resist 2
1 from above, ion implanter 24
By doing so, an implant region 25 was formed as shown in FIG. 2(C). [Problem to be solved by the invention l Looking at the implant area 25 in FIG. 2(C), the second
It can be seen that there is no ion infrastructure in the area of the resist 20 in FIG. 2(a), so there is no need to remove the resist 20 in FIG. It is an attempt to solve problems. [Means for Solving the Problems J] In order to solve the above problems, in the present invention, ultraviolet irradiation baking (UV cure) is used to cure the resist, and overlapping patterning of the resist is performed. This is a method in which heat treatment is performed at the same time as the resist is irradiated with the resist, and is usually used to improve the heat resistance of the resist. [Operation 1] According to the manufacturing process of a semiconductor device according to the present invention, UV is applied to the lower resist in a state where the lower resist is patterned.
Apply cure. As a result, even if you apply resist on top of resist, the pattern shape of the underlying resist will not change.
Can be applied stably. Then, overlapping patterning of the resist becomes possible, and the wasteful process of removing the resist once can be omitted. [Example J Example 1 FIGS. 1(a) to 1(f) show cross-sectional views in the order of steps of the method for manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 1(a), a Si nitride film is deposited on the entire surface of the Si substrate 1. Next, as shown in FIG. 1(b), the lower resist 3 is patterned and left, and the nitride 112 is etched. and leave it in the same shape as the lower resist 3 as shown in Figure 1 (
Apply UV curing in the state of b). The UV curing program at this time is shown in FIGS. 3 and 4. Here, FIG. 3 is a temperature program, and FIG. 4 is a program for ultraviolet irradiation intensity. , In this state, ion implantation 6 is performed, and the zero-order resist 3.4 that forms field implantation region 5 is completely removed and oxidized. Then, as shown in FIG. 1(d), there is no nitride film 2 In the first step, only the nitride film 2 is oxidized, as shown in FIG. 1(e). After that, the device shown in FIG. 1(f) is manufactured in the following order. First, polysilicon 8 is deposited on the entire surface and patterned, then a source/train implant 9 is formed, an intermediate insulating film 10 is deposited on the entire surface, and then contact holes 1O are patterned. Then, the AI wiring 12 is formed by depositing AI on the entire surface and patterning. In addition, here, in order to confirm the effect of UV cure, 2
We prepared several boards and changed the process for each board. In other words, one side is exactly the same as in Example 1, but the other side is the resist 4 shown in FIG. 1(C) without UV curing in the state shown in FIG. 1(b).
was applied. The UV curing program used here is the same as in Example 1, as shown in Figures 3 and 4, and the maximum temperature is 170°C.
It can be seen that it is. As a result, the substrate that was not subjected to UV curing was as shown in Figure 1 (C).
It was discovered that the shape of the lower resist layer 3 had collapsed, making it impossible to proceed to the next step. Example 2 In this example, the same steps as in Example 1 were carried out, but changes in the thickness of the lower resist 3 in FIG. 1 were measured at each step. The results are as follows. After developing lower resist 3 1.1 mm Lower resist 3 after UV curing 1.05 Mm upper resist 4
1.05 mm after development From this, it became clear that even if the upper layer resist 4 was exposed and developed, the lower layer resist 3 hardly decreased in thickness. [Effect of the Invention J As shown in the above embodiments, according to the present invention, stable overlapping patterning can be performed, and thereby a simple process can be realized.
【図面の簡単な説明】
第1図(a)〜(f)は1本発明による半導体素子の製
造方法の工程順断面図、第2図(a)〜(C)は従来の
半導体素子の製造方法の工程順断面図、第3図は、本発
明の実施例において用いたUVキュアの温度プログラム
図、同じく第4図は紫外線照射のプログラム図である。
・Si基板
・St窒化膜
・下層レジスト
・上層レジスト
・フィールドインプラ領域
・イオンインプラ
・酸化膜
・ポリシリコン
・ソース・トレインインプラ
・中間絶縁賎
・コンタクトホール
・AI配線
以[Brief Description of the Drawings] Figures 1 (a) to (f) are cross-sectional views in the order of steps of a method for manufacturing a semiconductor device according to the present invention, and Figures 2 (a) to (C) are conventional process steps for manufacturing a semiconductor device. FIG. 3 is a cross-sectional view showing the steps of the method, and FIG. 3 is a temperature program diagram for UV curing used in the embodiment of the present invention, and FIG. 4 is a program diagram for ultraviolet irradiation.・Si substrate, St nitride film, lower layer resist, upper layer resist, field implant area, ion implant, oxide film, polysilicon, source, train implant, intermediate insulation layer, contact hole, AI wiring and more
Claims (1)
ターニングによって製造する際に感光性材料に、170
℃以下の温度での紫外線照射ベーキングを行う工程と、
紫外線照射ベーキングを行った前記感光性材料の上に、
感光性材料を塗布して露光、現像する工程とを用いる半
導体素子の製造方法。When manufacturing a semiconductor element by patterning a photosensitive material using exposure and development steps, 170% is added to the photosensitive material.
a step of performing ultraviolet irradiation baking at a temperature below ℃;
On the photosensitive material subjected to ultraviolet irradiation baking,
A method for manufacturing a semiconductor device using a process of applying a photosensitive material, exposing it to light, and developing it.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1246129A JPH03108314A (en) | 1989-09-21 | 1989-09-21 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1246129A JPH03108314A (en) | 1989-09-21 | 1989-09-21 | Manufacture of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03108314A true JPH03108314A (en) | 1991-05-08 |
Family
ID=17143912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1246129A Pending JPH03108314A (en) | 1989-09-21 | 1989-09-21 | Manufacture of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03108314A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6403423B1 (en) * | 2000-11-15 | 2002-06-11 | International Business Machines Corporation | Modified gate processing for optimized definition of array and logic devices on same chip |
JP2005252165A (en) * | 2004-03-08 | 2005-09-15 | Semiconductor Leading Edge Technologies Inc | Pattern forming method |
-
1989
- 1989-09-21 JP JP1246129A patent/JPH03108314A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6403423B1 (en) * | 2000-11-15 | 2002-06-11 | International Business Machines Corporation | Modified gate processing for optimized definition of array and logic devices on same chip |
US6548357B2 (en) | 2000-11-15 | 2003-04-15 | International Business Machines Corporation | Modified gate processing for optimized definition of array and logic devices on same chip |
JP2005252165A (en) * | 2004-03-08 | 2005-09-15 | Semiconductor Leading Edge Technologies Inc | Pattern forming method |
JP4480424B2 (en) * | 2004-03-08 | 2010-06-16 | 富士通マイクロエレクトロニクス株式会社 | Pattern formation method |
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