JPH03107845A - Method for inspecting resist pattern - Google Patents

Abstract

PURPOSE:To exactly and rapidly inspect whether resist patterns are defective or non-defective by providing a dummy resist pattern including a part of the real patterns in the peripheral part of a chip, observing the end part of the resist patterns with an electron microscope from diagonally above and comparing and studying the same with a design value. CONSTITUTION:The resist patterns are formed on a wafer including a dummy region 6 by a three-layer resist method. Projection exposing of UV rays is then executed and after the upper resist layer is developed, an intermediate layer resist 8 is dry etched with tetrafluorocarbon (CF4) as an etchant and a lower resist 9 with O2 as an etchant by a reactive ion etching device. The dummy region 6 is then observed by the scanning type electron microscope from diagonally above to form the dummy pattern 10 having the resist layer contg. the linear patterns 7, 7' in the dummy region 6. The size thereof is compared with the design value. Thus, whether the resist patterns are defective or non-defective are exactly and rapidly inspected.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to establish a method for inspecting a resist pattern with a high aspect ratio. A dummy resist pattern including a part of the actual pattern is provided in the region, and the end portion of the 8-m resist pattern is observed diagonally from above using an electron microscope and compared with a design value, and the method according to claim 1 The dummy resist pattern includes a pattern in which the central linear pattern is set back from the linear patterns on both sides, and if the substrate has a step, the dummy resist pattern is also formed on the step, and then A resist pattern inspection method is characterized in that the edge of the resist pattern is observed obliquely from above using an electron microscope and compared with design values.

[Industrial application field]

The present invention relates to an L/resist pattern inspection method.

Due to the need to process large amounts of information at high speeds, information processing technology has advanced significantly, and information processing equipment has become smaller and larger in capacity, and the semiconductor devices that make up the main body of this equipment have become more integrated due to the miniaturization of unit elements. LSI and νLSI have been put into practical use.

In order to form semiconductor integrated circuits, thin film formation technology, photo-etching technology, impurity ion diffusion technology, etc. are used, and resist coating and etching equipment are used to form patterns such as electrodes and conductor lines. This is done using photo-etching technology.

However, as the degree of integration advances, patterns are becoming increasingly finer; for example, the minimum line width of conductor lines that connect circuits to the electrodes of each unit element has reached the submicron range2.
It has become increasingly difficult to form fine patterns with high precision.

Therefore, in order to improve the yield of non-defective semiconductor chips, if a pattern that deviates from the design dimensions is formed in the resist patterning process, re-patterning must be performed.

Therefore, an appropriate method for inspecting resist pattern dimensions has become important.

[Prior art] Photo-etching technology uses a vacuum evaporation device or a chemical vapor deposition device (abbreviated as CVD device) to form a thin film made of metal, semiconductor, or insulator on a semiconductor substrate to be processed (hereinafter referred to as a wafer). A thin film of resist is formed on this by the Svinco method, and then UV projection exposure, X-ray projection exposure, or electron beam scanning is performed to selectively expose the cysts to the exposed areas. When a negative type resist is used, the photosensitive area becomes insoluble in the developer, and when a positive type resist is used, it becomes soluble, so a T-cyst pattern is created, and this is used as a mask to coat the wafer. This is a technique of dry etching or etching a thin film to form a fine pattern made of the thin film.

child! Initially, only the intermediate layer resist method was used to form resist patterns, and patterns were formed using chemical etching or dry etching, but as the degree of integration increased, it became necessary to multilayer circuits, and Due to the large number of steps involved in etching, multi-layer resist methods such as two-layer resist methods and three-layer resist methods have come to be used, and dry etching has also come to be used mainly from the standpoint of pattern accuracy. Ta.

For this reason, the two-layer resist method uses a lower layer resist such as phenol novolac resin or cresol novolac resin, which is resistant to etching gases such as carbon tetrafluoride (CF4) ions, but is easily attacked by oxygen ions. The unevenness of the substrate is flattened by spin-coating the material to make it thicker.
On top of this, a resist that contains silicon and is resistant to oxygen ions is coated as a two-layer resist to prepare a pattern-forming structure. This is a method of transferring the image to the underlying resist.

In addition, in the three-layer resist method, a silicon organic compound such as organosilsesquioxane is spin-coded onto a lower resist layer made of phenol novolac resin to form a thin film, and then heated to cross-link and polymerize oxygen ions. A structure was prepared by forming a polymer thin film made of silicon oxide, which is resistant to water, as an intermediate layer, and coating this with a conventional resist as an upper layer resist. In this method, the pattern of the upper resist layer is transferred to the intermediate layer by an anisotropic dry etching method, and then the pattern of the intermediate layer is transferred to the lower resist layer by an anisotropic dry etching method using oxygen.

Now, single-layer resist patterns formed by ultraviolet exposure, X-ray exposure, or electron beam scanning require a thickness of 1 μa or more in order to be used as a mask for dry etching. The aspect ratio of the resist pattern with a pattern width of °ζ is extremely large, and the pattern used has a forward taper or reverse taper shape that is very close to the vertical.

In addition, in the multilayer resist method, when the lower layer resist is etched by anisotropic dry etching method and the pattern of the upper layer or intermediate layer is transferred to the lower layer, the film thickness of the lower layer resist is smaller than that of the single layer resist method. Because it is thick,
When the pattern width is small, the aspect ratio becomes very large, and the pattern tends to have a forward tapered shape or a reverse tapered shape that is very close to a vertical shape.

FIG. 2 shows the cross-sectional shape of the resist pattern 2 formed on the substrate 1 to be processed.

Note that the pattern accuracy of the thin film pattern produced by dry etching the thin film on the substrate using the resist pattern as a mask is determined by the dimensions of the resist pattern at the root in contact with the thin film, so it is necessary to inspect the dimensions of the root when inspecting the resist pattern. However, since the aspect ratio was not so large and a forward tapered resist pattern was used, scanning electron microscopy (SEM) inspection from vertically upward was sufficient.

However, as the minimum width of the single-layer or multilayer thin film pattern to be formed becomes submicron and the aspect ratio of the cross-sectional shape of the pattern becomes large, it becomes impossible to inspect the resist pattern using conventional methods, so this countermeasure is It was necessary.

[Problem to be solved by the invention]

With conventional SEM observation performed vertically from above, the pattern width at the top of the resist pattern can be easily measured. If the resist pattern is thinner than the upper layer or the middle layer in the three-layer resist method, it is impossible to measure the resist pattern at the base in contact with the thin film.

Furthermore, because the aspect ratio of the resist pattern is large, if the shape is very close to a vertical shape even if it is a vertical shape or a forward taper shape, it is extremely difficult to distinguish it from a reverse taper shape using conventional SEM observation from vertically above. It is difficult to attach the resist, and measurements of the root dimensions cannot be trusted.

Therefore, the challenge is to be able to accurately measure the resist pattern at the base.

[Means to solve the problem]

The above problem is solved when forming a resist pattern on a substrate to be processed, by providing a dummy resist pattern containing a part of the actual pattern in the peripheral area of the chip, and observing the edge of the resist pattern obliquely from above using an electron microscope. The dummy resist pattern according to claim 1 includes a pattern in which the central linear pattern is set back from the linear patterns on both sides, and a step is formed on the substrate. In such a case, the resist pattern inspection method is characterized in that, after the dummy pattern is also formed in the step part, the edge of the resist pattern is observed diagonally from above using an electron microscope and compared with the design value. The problem can be solved by

[Effect]

The present invention provides a dummy resist pattern including a part of the actual pattern with the minimum width of the actual pattern in the peripheral area of the chip,
By observing this dummy pattern obliquely from above using a SEM, all necessary inspection items can be observed with high precision.

Therefore, when inspecting resist patterns, it is necessary to: ■ be able to measure the dimensions of the root portions of the end faces of resist patterns; It shall be possible to measure the dimensions of the base of the end face of the linear pattern that is set back.

■ If there is a step on the substrate, the dimensions of the root of the edge of the resist pattern formed on the step can be measured.

It is.

In this case, a pattern that is set back from the linear patterns on both sides is sometimes used because the shape of the pattern end at the most protruding position of the dummy pattern is likely to collapse.

The present invention creates a dummy resist pattern that includes a part of the end of the actual pattern and meets these conditions.

In addition, since this dummy pattern is created in the peripheral area of the chip, which is separate from the main pattern, it is possible to avoid the actual pattern that may obstruct the field of view during SEM observation, and to observe the resist pattern with a high aspect ratio with an SEM from diagonally above.
Observations can be made to accurately measure dimensions (1) to (2).

FIGS. 3(A) to 3(F) are examples of dummy patterns that include part of the actual pattern of electrodes 3 and conductor lines 4 made of sputtered aluminum alloy films used in the formation of semiconductor devices. , (A) is an example where the electrode is in the middle and there is no retreat pattern, (B) is an example where the electrode is in the middle and there is a retreat pattern every other time, (C) is an example where the electrode is at the edge and there is no retreat pattern. An example without (D
) is an example where the electrode is at the edge and there is a retreat pattern on every other one, (E) is an example where the electrode is on the edge and there is a retreat pattern on every other one, but the opening degree on both sides of the pattern is not equal. (F) The electrode is at the end, and the recessed pattern is 7.・There is one example.

The present invention makes it possible to conduct a sufficient inspection simply by observing the end portion of the dummy pattern, which includes a portion of the actual pattern, using a SEM and comparing it with the design value.

(Example) A1. alloy (Aff
A case of forming a conductor line made of (i + Si) will be explained.

When forming an A1 alloy film with a thickness of about 1 μm by sputtering on an evaporator with steps, the A1 alloy film is formed in a similar shape to the substrate surface shape, resulting in steps. When the invention is applied, a dummy area is provided around the chip, and the same level difference as the actual pattern is provided in the dirt.

In FIG. 1, the broken line indicates the presence of a step 5 made of the A1 alloy film.

A resist pattern is thus formed on the wafer including the dummy region 6 by the conventional three-layer resist method.

That is, a lower resist 9 was formed by coating a phenol novolac resin to a thickness of about 2 μm using a spin code method, and the step 5 on the substrate was flattened.

Next, organosilsesquioxane dissolved in a solvent is spin-coded and then heated to form an intermediate layer resist 8 made of silicon oxide (SiO2) with a thickness of about 2000 mm, and on top of this, a spin-code method is applied. A novolac positive type resist having a thickness of approximately 5000 mm was coated to form an upper resist layer.

Next, after performing projection exposure to ultraviolet rays and developing the upper FIV cyst layer, the intermediate layer resist 8 is etched using carbon tetrafluoride (CF4) as an etchant, and the lower layer resist 9 is etched using a reactive ion etching device using O7 as an etchant. Dry etched.

Then, by observing the dummy area 6 from diagonally above with a SEM, the dummy area 6 with a step as shown in FIG.
It was possible to form a resist layer including linear patterns 7 and 7' which had the minimum width of the actual pattern and were set back from the linear patterns on both sides.

Incidentally, FIG. 1 shows a state in which the "-" layer resist layer disappears due to dry etching, and the intermediate layer resist 8 and the lower layer resist 9 remain.

The dummy pattern 10 formed in this way has all the conditions that make it easy for defects to occur during dry etching, so if the dimensions of the dummy pattern 10 match the design values, the actual pattern will completely meet the design values. I'm satisfied.

(Effects of the invention) A dummy pattern is provided in a dummy area around a chip that has all the conditions that are likely to cause defects in dry enoching, and this dummy pattern is observed with an SEM from diagonally above and compared with the design dimensions. By implementing the invention, it is possible to accurately and quickly inspect the quality of a resist pattern.

It is.

[Brief explanation of drawings]

FIG. 1 is a perspective view of a dummy pattern according to the present invention, FIG. 2 is a cross-sectional view showing the shape of a resist pattern, and FIG. 3 is a plan view of the dummy pattern including an actual pattern. In the figure, l is the substrate to be processed, 2 is the resist pattern 3 is the electrode, 4 is the conductor line, 5 is the step,
6 is a dummy area, 7.7' is a receded linear pattern, 8 is an intermediate layer resist, 9 is a lower layer resist, 10 is a dummy pattern, )) j Tapered shape! Formation of a straight upside-down inverted tapered resist han "7-" T sectional view Fig. 2

Claims (2)

[Claims] (1) When forming a resist pattern on the substrate to be processed, a dummy resist pattern containing a part of the actual pattern is provided in the peripheral area of the chip, and the end of the resist pattern is observed diagonally from above using an electron microscope, A resist pattern inspection method characterized by comparing and examining design values. (2) When the dummy resist pattern according to claim 1 includes a pattern in which the central linear pattern is set back from the linear patterns on both sides, and the substrate has a step,
A method for inspecting a resist pattern, characterized in that, after the dummy pattern is also formed in a portion with a step, an end portion of the resist pattern is observed obliquely from above using an electron microscope and compared with a design value.