JPH07169813A - Step measuring method for wafer surface - Google Patents

Abstract

PURPOSE:To provide the method for measuring the step difference at the surface of a wafer without damaging the wafer and to improve the reduction of the inspecting cost, productivity and yield in the manufacturing process of a semiconductor device. CONSTITUTION:In the first step, resist 10 is applied under the state, wherein the surface is flat, on the upper surface of a wafer 1. In the second step, lithography using sepcified exposing energy is performed on the resist 10, a plurality of patterns 11-15, whose pattern widths w11-w15 are changed, are formed at the positions, where the resist 10 is applied at a constant thickness (t), on the wafer 1, and the inspection patterns 11-15 having the different resolutions in correspondence with the pattern widths w11-w15 are arranged on the wafer 1. In the third step, the inspection patterns 11 and 12, where the pattern defects occur, are detected among the inspection patterns 11-15, and a step difference T of the wafer 1 is obtained on the basis of the pattern widths w11 and w12. Therefore, the step difference T of the surface of the wafer 1 is obtained without damaging the wafer 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring a level difference on a wafer surface, and more particularly to a method for measuring a level difference formed on a wafer surface in a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have become highly integrated and highly functional, the number of device structures has increased. As the number of layers increases, the steps formed on the wafer surface, for example, due to the formation of wiring, tend to increase. For example, in the wafer 4 shown in FIG. 4, the field 402 is formed on the substrate 401, and the gate 403 is formed on the field 402. And the gate 403
A first interlayer insulating film 404 is formed on the upper surface of the substrate 401 so as to cover the field 402. Then, a lower layer wiring 405 is formed on the upper surface of the first interlayer insulating film 404 corresponding to the upper portion of the gate 403. Lower layer wiring 40
A second interlayer insulating film 406 is formed on the first interlayer insulating 404 so as to cover the first interlayer insulating film 404. Further, a wiring forming layer 407 for forming an upper wiring is formed on the upper surface of the second interlayer insulating film 406. A field 402, a gate 403, and a lower layer wiring 40 are formed on the surface of the wafer 4.
A step T is formed by stacking 6 layers.

In the wafer 4 having the above structure, when the wiring forming layer 407 is processed to form the upper wiring, first, the resist 40 is applied to the upper surface of the wiring forming layer 407 so that the surface becomes flat. To do. Next, this resist 4
0 is patterned by lithography to form a wiring pattern (not shown). Then, the wiring forming layer 407 is etched by using this wiring pattern as a mask to form an upper layer wiring composed of the wiring forming tank 407 on the surface of the wafer 4.

In the above-mentioned lithography, when the wiring pattern made of the resist 40 is formed by the lithography, the exposure energy depends on the film thickness t of the resist 40 applied on the wafer 4 so that no defect is caused by the excess or deficiency of the exposure energy. Need to be optimized. For example, when the resist 40 is of a positive type, the exposure energy is insufficient, so that a resist residue occurs in a portion where the resist 40 is applied most thickly. Then, as shown in the plan view of FIG. 4B, the wiring pattern 501 made of the resist 40 is short-circuited between the lower layer wirings 405 due to the remaining resist.

However, the resist 40 shown in FIG.
The film thickness t of is a value that changes depending on the step T on the surface of the wafer 4. For example, when the step T on the surface of the wafer 4 increases, the film thickness t of the resist 40 for compensating for the step T and flattening the surface increases. Therefore, when a resist pattern is formed by lithography on the upper surface of the wafer 4 having the step T formed on the surface as described above,
The step T on the surface of the wafer 4 is measured in advance. Then, the film thickness t of the resist 40 is obtained from the measured value of the step T, and the value of the exposure energy suitable for the film thickness t is determined.

The step T is measured by dividing the wafer 4 in a direction perpendicular to the lower layer wiring 405 to prepare a cross-section sample of the wafer 4 and observing the cross-section sample with an electron microscope.

[0007]

However, the above step measuring method has the following problems. That is, the level difference on the wafer surface depends on changes in the flow temperature of the interlayer insulating film formed above and the concentration of impurity diffusion in the film.
For example, even a wafer formed under the same device design has a large step difference on the surface of a wafer of a lot in which the flow temperature of the interlayer insulating film is set lower than the reference value for some reason. Therefore, the size of the step formed on the surface of the wafers of different lots is different. Therefore, in order to prevent the defect of the resist pattern due to the excess or deficiency of the exposure energy due to the change in the step on the wafer surface, it is necessary to measure the step on the wafer extracted for each lot by the above method. is there. However, this is not only time-consuming, but there is a problem in that the wafer for which the step is measured cannot be commercialized.

Therefore, in the wafer having the step formed on the surface as described above, first, a resist pattern is formed on the wafer by lithography using exposure energy based on the design value of the wafer. Then, in order to find a defective formation of the resist pattern due to the change in the step on the wafer surface, the resist pattern is inspected.

If a defect in the resist pattern is found in the above inspection, the resist pattern on the wafer is removed, and the resist pattern is formed again by lithography with different exposure energy. However, the exposure energy in this case is uncertain only by determining whether it is larger or smaller than the reference exposure energy. Therefore, there is a possibility that the resist pattern formed by changing the exposure energy may have a defect. Therefore, it is necessary to repeat the formation of the resist pattern with different exposure energy and the inspection until the defect of the resist pattern is not found by the inspection, which is very troublesome. Furthermore, if a defect in the resist pattern is missed by the above inspection, processing is performed using the defective resist pattern as a mask. Then, for example, the wiring formed by using this resist pattern as a mask is short-circuited or broken, resulting in a defective product.

Therefore, the present invention provides a step measuring pattern and a step measuring method using the same for solving the above problems, thereby reducing inspection cost and improving productivity and yield in a semiconductor device manufacturing process. The purpose is to

[0011]

A first method for measuring a step on the surface of a wafer for achieving the above object is performed as follows. First, in the first step, a resist is applied to the upper surface of the wafer with the surface being flat. Next, in the second step,
Lithography using predetermined exposure energy is performed on the resist to form a plurality of inspection patterns with varying pattern widths on the wafer at positions where the resist is applied with a constant film thickness. And in the third step,
An inspection pattern having a pattern defect is detected from the inspection patterns, and the step difference of the wafer is obtained from the pattern width of the inspection pattern.

Further, the method of measuring the step difference on the surface of the second wafer is performed as follows. First, in the first step, a resist is applied to the upper surface of the wafer with the surface being flat. Next, in a second step, lithography using a predetermined exposure energy is performed on the resist to form a plurality of inspection patterns having a predetermined pattern width on the wafer at positions where the resist film thicknesses are different from each other. . And
In the third step, an inspection pattern in which a pattern defect has occurred is detected from the inspection patterns, and the step of the wafer is obtained from the formation position of the inspection pattern.

[0013]

In the first wafer surface level difference measuring method described above, a plurality of inspection patterns whose pattern widths are changed by lithography using a predetermined exposure energy are applied at positions where the resist film thickness is constant. Form. Therefore, inspection patterns having different resolutions are arranged on the wafer according to the pattern width, and when each inspection pattern is formed, the level difference on the wafer surface affects the size depending on the resolution. Therefore, by detecting an inspection pattern having a pattern defect in the plurality of inspection patterns, the step difference on the wafer surface can be obtained from the pattern width. Therefore, by observing the inspection pattern formed on the wafer, the level difference on the surface can be obtained without damaging the wafer.

Further, in the second wafer surface level difference measuring method, a plurality of inspection patterns having a predetermined pattern width are formed at positions having different resist film thicknesses by lithography using a predetermined exposure energy. Therefore, inspection patterns with different resolutions are arranged on the wafer according to the resist film thickness, and when forming each inspection pattern, the step difference on the wafer surface affects the size according to each resolution. Therefore, similar to the first method described above, the step difference on the wafer surface can be obtained without damaging the wafer.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG. As shown in FIG. 1A, in a wafer 1 whose surface level difference is measured, a field 102 is formed on a substrate 101, and a gate 103 is formed on the field 102. Then, the gate 103 and the field 10
The first interlayer insulating film 104 is formed on the upper surface of the substrate 101 so as to cover the first and second insulating films. Then, the lower layer wiring 105 is formed on the first interlayer insulating film 104 corresponding to the gate 103.
Are formed. A second interlayer insulating film 106 is formed on the first interlayer insulating 104 so as to cover the lower layer wiring 105. Further, a wiring forming layer 107 for forming an upper wiring is formed on the upper surface of the second interlayer insulating film 106. As described above, the step T is formed on the surface of the wafer 1 by stacking the field 102, the gate 103, and the lower layer wiring 105.

Then, the step T on the surface of the wafer 1 is measured as follows. First, as a first step, the resist 10 is formed on the upper surface of the wafer 1 while the surface is flat.
Apply. Here, for example, a positive resist is used.

Next, as a second step, the inspection patterns 11 to 15 for measuring the step T are formed on the resist 10 of the wafer 1 by lithography. These inspection patterns 11 to 15 are resist patterns (not shown) for forming an actual device by lithography.
Is formed on the wafer 1, it is formed on the wafer 1 at a position that does not affect the formation of the actual device and on the same structure as the wafer structure where the actual device is formed. Then, the exposure energy at that time is set to a predetermined value based on the design of the wafer 1. Further, these inspection patterns 11 to 15 are line-shaped slit patterns, and at least two inspection patterns 11 to 15 are arranged so that the inspection patterns 11 to 15 are arranged at positions where the resist 10 is applied with the thickest film thickness t. It is formed on the resist 10 so as to intersect with the lower layer wiring 105. Then, as shown in the plan view of FIG. 1B, each of the inspection patterns 11 to 15 has, for example, w ₁₁
From 0.5μm, 0.6μm, 0.7μm, 0.8
Pattern width w ₁₁ changed in steps of μm and 0.9 μm
˜w ₁₅ . Also, for example, each inspection pattern 1
The interval of 1 to 15 is 1.0 μm.

After that, as a third step, the inspection patterns 11 to 15 formed on the wafer 1 as described above are observed with an electron microscope to detect the inspection patterns 11 and 12 in which the pattern defects occur. Then, the step T is obtained from the detected pattern widths of the inspection patterns 11 and 12. In this case, for example, using the step T on the surface as a factor, the pattern width in which a pattern defect occurs when the exposure is performed with the same exposure energy as above is confirmed. Then, based on the result, the step T on the surface of the wafer 1
Ask for.

For example, when the step T of the wafer 1 is equal to the design value, a pattern defect occurs in the inspection pattern 11 due to the combination of the resolution of the exposure light and the resist, and the inspection patterns 12, 13, 14, In No. 15, no pattern defect occurs. Here, when the step T on the surface of the wafer 1 becomes larger than the design value, the film thickness t of the resist 10 becomes thick. Therefore, the inspection pattern 1
When forming 1 to 15, the exposure energy is insufficient. Therefore, as shown in FIG.
Inspection pattern 12 with wider pattern width and higher resolution than
A pattern defect occurs in the. The inspection patterns 13 to 1 having a wider pattern width as the amount of expansion of the step T is larger.
Pattern defects extend to 5. Further, in the above case, it is predicted that the resist pattern for forming the actual device also has a pattern defect due to the expansion of the step T.

When the step T on the surface of the wafer 1 is reduced and the resist film thickness is reduced, the exposure energy becomes excessive and the inspection pattern 1 formed as described above.
1 has no defect. Then, it is predicted that the resist pattern for forming the actual device also has a pattern defect due to the reduction in the step T.
Further, if the step on the surface of the wafer 1 is as designed, a pattern defect occurs only in the inspection pattern 11.
In this case, it is predicted that the resist pattern for forming the actual device will not have a pattern defect due to the expansion and contraction of the step T.

In the above step measuring method, the step T on the surface of the wafer 1 is obtained by observing the inspection patterns 11 to 15 formed on the wafer 1 by lithography using a predetermined exposure energy. Therefore, the wafer 1
A step on the surface of the wafer 1 can be obtained without damaging the wafer.

In the above embodiment, the resist pattern for forming the actual device and the inspection patterns 11 to 15 are formed on the same structure. Therefore, in the resist pattern of the actual device, it is possible to easily inspect the occurrence of the pattern defect due to the change in the level difference on the wafer surface by observing the level difference measuring inspection pattern. Further, since the appropriate value of the exposure energy can be obtained from the obtained step T, after the step of the wafer 1 is obtained as described above, the resist 10 on the wafer 1 is removed and the wafer 1 is coated again. Lithography is performed on the resist by the above-mentioned optimum exposure energy to form a resist pattern for an actual device.
As a result, a resist pattern having sufficient exposure energy is formed on the wafer.

In the first embodiment, the case where the positive type resist is used has been described. However, it is also possible to measure the level difference on the wafer surface by using a negative resist. In this case, each inspection pattern is composed of a pattern group composed of, for example, a linear resist pattern.

Next, a second embodiment of the present invention will be described with reference to FIG. Wafer 2 for measuring step difference in the second embodiment
For example, the upper wiring 108 is formed in a state orthogonal to the lower wiring 105 by etching the upper wiring forming layer in the wafer shown in the first embodiment.

When the step T on the surface of the wafer 2 is measured, first, as in the first embodiment, the first step is performed.
In this step, the resist 20 is applied on the upper surface of the wafer 2 with the surface being flat.

Next, as a second step, the inspection pattern 2 for measuring the step T is formed on the resist 20 on the wafer 2.
1 to 23 are formed. These inspection patterns 21-23
As in the first embodiment, when forming a resist pattern (not shown) for forming an actual device on the wafer 2, a position that does not affect the formation of the actual device on the wafer 2. And is formed on the same structure as the wafer 2 structure at the position where the actual device is formed. Then, the exposure energy at that time is set to a predetermined value based on the design of the wafer 2. Further, in these inspection patterns 21 to 23, for example, the resist 20 has the thickest film thickness t.
It is a hole-shaped pattern that is arranged at the position where it is applied. Each of the inspection patterns 21 to 23 has pattern widths w _{21 to} w ₂₃ that are changed stepwise in the direction in which the inspection patterns 21 become wider, for example.

Then, when the step difference on the surface of the wafer 2 is measured using the above inspection patterns 21 to 23, it is performed in the same manner as in the first embodiment.

When the step T on the surface of the wafer 2 is measured as described above, the proper exposure energy for forming a contact hole in the actual device can be easily known.

Next, a third embodiment of the present invention will be described with reference to FIG. The wafer 3 whose surface level difference is to be measured in the third example is configured, for example, in the same manner as the wafer shown in the first example, and a level difference T is formed on the surface.

When measuring the step T on the surface of the wafer 3, first, as a first step, as in the case of the first and second embodiments, the surface of the upper surface of the wafer 3 is flat and the positive type is used. The resist 30 is applied.

Next, as a second step, the inspection pattern 3 for measuring the step T is formed on the resist 30 on the wafer 3.
1-36 are formed. These inspection patterns 31 to 36
When forming a resist pattern (not shown) for forming an actual device on the wafer 3 by lithography as in the first and second embodiments, the formation of the actual device on the wafer 3 is It is formed on the same structure as the wafer structure where there is no influence and where the actual device is formed. Then, the exposure energy at that time is set to a predetermined value based on the design of the wafer 3. Further, these inspection patterns 31 to 36 are hole-shaped patterns having a predetermined pattern width w, and the respective inspection patterns ₃₁ to 36 have the film thickness of the resist 30 of t ₃₁ to.
It is arranged at a position different from t ₃₆ .

Then, as a third step, the inspection patterns 31 to 36 formed on the wafer 3 as described above are observed with an electron microscope to detect the inspection patterns 32 and 35 in which pattern defects have occurred. Then, the step T is obtained from the position on the wafer 3 where the inspection patterns 32 and 35 are formed. In this case, for example, similar to the first and second embodiments, when the exposure is performed with the same exposure energy as described above using the step T of the rough surface as a factor, a pattern defect occurs on the wafer. Check the position of. Then, the step T on the surface of the wafer 3 is obtained based on the result.

For example, when the step T of the wafer 3 is equal to the design value, in the above-mentioned lithography, for example, the resist 30 is selected from the combination of the resolution by exposure energy and the resist.
It is assumed that a pattern defect occurs only in the inspection pattern 35 formed at the position where is coated with the thickest film thickness t ₃₅ . Here, when the step T on the surface of the wafer 3 is larger than the designed value, the film thicknesses t _{31 to} t ₃₆ of the resist 30 become thicker. Therefore, when the inspection patterns 31 to 36 are formed as described above, the exposure energy is insufficient. Therefore, since the resist 30 has a film thickness t ₃₂ thinner than the formation position of the inspection pattern 35, the inspection pattern 3 having a high resolution is obtained.
2 also has pattern defects. Then, the expansion amount of the step T is obtained in the same manner as in the first and second embodiments.

When the step difference on the surface of the wafer 3 is reduced and the resist film thickness is reduced, the exposure energy becomes excessive and the inspection pattern 35 formed as described above.
Does not have any defects. Further, when the step on the surface of the wafer 3 is as designed, a pattern defect occurs only in the inspection pattern 35.

In the above step measuring method, the step T on the surface of the wafer 3 is obtained by observing the inspection patterns 31 to 36 formed on the wafer 3 as described above. Therefore, like the first and second embodiments,
A step difference on the surface is required without damaging the wafer 3.

Further, in the above-described embodiment, similarly to the first embodiment, the resist pattern for forming the actual device and the inspection patterns 31 to 36 are formed on the same structure. . Therefore, in the resist pattern of the actual device, it is possible to inspect the occurrence of the pattern defect due to the change in the step on the wafer surface by observing the inspection patterns 31 to 36. Further, a proper value of the exposure energy can be obtained from the obtained step T to form a resist pattern having sufficient exposure energy on the wafer.

In the third embodiment, the inspection pattern 31
Although the shapes of to 36 are hole-shaped, the present invention is not limited to this and may be slit-shaped or line-patterned.

[0038]

As described above, according to the first wafer surface level difference measuring method, a plurality of inspection patterns having different pattern widths are applied at positions where the resist film thickness is applied at a constant thickness. A plurality of inspection patterns with different resolutions are formed on a wafer having steps by being formed by lithography, and a step on the wafer surface is obtained by detecting defects in the inspection patterns. For this reason,
It is possible to obtain the step difference on the wafer surface without damaging the wafer. Then, it becomes possible to obtain the appropriate exposure energy of the resist pattern formed on the wafer from the obtained step difference value. Further, by forming the inspection pattern in the same step as the resist pattern for the actual device, it is possible to predict the occurrence of the formation defect without inspecting the resist pattern for the actual device. Therefore, it is possible to reduce the inspection cost and improve the productivity and the yield in the manufacturing process of the semiconductor device. Further, according to the second wafer surface level difference measuring method, a plurality of inspection patterns having a predetermined pattern width are formed by lithography at positions where the resist film thicknesses are different, and thus a plurality of level difference wafers having different resolutions are formed. The inspection pattern is formed, and a step on the wafer surface is obtained by detecting a defect in the inspection pattern. Therefore, like the first method, it is possible to reduce the inspection cost and improve the productivity and the yield in the manufacturing process of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a first embodiment.

FIG. 2 is a plan view illustrating a second embodiment.

FIG. 3 is a diagram illustrating a third embodiment.

FIG. 4 is a diagram illustrating a conventional example.

[Explanation of Codes] 1,2,3 Wafers 10, 20, 30 Resists 11, 12, 13, 14, 15 Inspection Patterns 21, 22, 23 Inspection Patterns 31, 32, 33, 34, 35, 36 Inspection Patterns T Steps t resist film thickness t ₃₁ , t ₃₂ , t ₃₃ , t ₃₄ , t ₃₅ , t ₃₆ resist film thickness w ₁₁ , w ₁₂ , w ₁₃ , w ₁₄ , w ₁₅ pattern width w ₂₁ , w ₂₂ , w ₂₃ pattern width w Specified pattern width

Claims (2)

[Claims] 1. A method for measuring a level difference on a wafer surface, comprising a first step of applying a resist on the upper surface of the wafer in a flat surface state, and a lithography using a predetermined exposure energy for the resist. And a second step of forming a plurality of inspection patterns having different pattern widths on the wafer at a position where the resist is applied with a constant film thickness, and a pattern defect occurs in the inspection patterns. A third step of detecting an existing inspection pattern and obtaining the step of the wafer from the pattern width of the inspection pattern. 2. A method for measuring a level difference on a wafer surface, comprising: a first step of applying a resist on the upper surface of the wafer in a flat surface state; and a lithography using a predetermined exposure energy for the resist. A second step of forming a plurality of inspection patterns having a predetermined pattern width on the wafer at positions where the resist film thicknesses are different from each other; and an inspection pattern in which a pattern defect has occurred from the inspection patterns And a third step of obtaining the step of the wafer from the position where the inspection pattern is formed, and a third step of measuring the step of the wafer surface.