JPH03107825U - - Google Patents
Info
- Publication number
- JPH03107825U JPH03107825U JP1627890U JP1627890U JPH03107825U JP H03107825 U JPH03107825 U JP H03107825U JP 1627890 U JP1627890 U JP 1627890U JP 1627890 U JP1627890 U JP 1627890U JP H03107825 U JPH03107825 U JP H03107825U
- Authority
- JP
- Japan
- Prior art keywords
- timer
- output
- circuit
- flop
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案の第１の実施例の等価回路図、
第２図は第１図のタイマ回路を用いた単安定発振
回路の回路図、第３図は第２図の回路の各部電圧
波形図、第４図は本発明の第２の実施例の等価回
路図、第５図は従来技術のタイマ回路の一例の等
価回路図である。
１……ＶＤＤ端子、２……ＶＳＳ端子、３……
スレツシヨルド端子、４……トリガ端子、５〜７
……抵抗、８……スレツシヨルド入力コンパレー
タ、９……トリガ入力コンパレータ、１０……セ
ツト・リセツトフリツプフロツプ、１１……Ｐチ
ヤネルＭＯＳＦＥＴ、１２……ＮチヤネルＭＯＳ
ＦＥＴ、１３，１４……インバータ、１５……ナ
ンドゲート、１６……インバータ、１７……Ｎチ
ヤネルＭＯＳＦＥＴ、１８……出力端子、１９…
…デイスチヤージ端子、２０……タイマ出力制御
回路、２１……インバータ、２２……ナンドゲー
ト、２３……インバータ、２４……抵抗、２５…
…コンデンサ、２６……ノアゲート、２７……ア
ンドゲート、Ａ……フリツプフロツプセツト入力
、Ｂ……フリツプフロツプリセツト入力、Ｃ……
トリガパルス幅、Ｃ′……トリガパルス幅、Ｄ…
…出力パルス幅。
FIG. 1 is an equivalent circuit diagram of the first embodiment of the present invention,
Fig. 2 is a circuit diagram of a monostable oscillation circuit using the timer circuit of Fig. 1, Fig. 3 is a voltage waveform diagram of each part of the circuit of Fig. 2, and Fig. 4 is an equivalent of the second embodiment of the present invention. FIG. 5 is an equivalent circuit diagram of an example of a conventional timer circuit. 1...VDD terminal, 2...VSS terminal, 3...
Threshold terminal, 4...Trigger terminal, 5 to 7
...Resistor, 8...Threshold input comparator, 9...Trigger input comparator, 10...Set/reset flip-flop, 11...P channel MOSFET, 12...N channel MOS
FET, 13, 14... Inverter, 15... NAND gate, 16... Inverter, 17... N channel MOSFET, 18... Output terminal, 19...
... Discharge terminal, 20 ... Timer output control circuit, 21 ... Inverter, 22 ... NAND gate, 23 ... Inverter, 24 ... Resistor, 25 ...
...Capacitor, 26...NOR gate, 27...AND gate, A...Flip-flop set input, B...Flip-flop preset input, C...
Trigger pulse width, C'...Trigger pulse width, D...
...Output pulse width.
Claims (1)
コンパレータ及びセツト・リセツトフリツプフロ
ツプを有するＣＭＯＳ集積回路のタイマ回路にお
いて、前記セツト・リセツトフリツプフロツプの
出力が電位不定となる入力条件の場合に、タイマ
出力電位を一定レベルに固定するタイマ出力制御
回路を有することを特徴とするタイマ回路。 In a timer circuit of a CMOS integrated circuit having a threshold input comparator, a trigger input comparator, and a set/reset flip-flop, when the input condition is such that the potential of the output of the set/reset flip-flop is undefined, the timer output potential is changed. A timer circuit characterized by having a timer output control circuit that fixes the output to a constant level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1627890U JPH03107825U (en) | 1990-02-20 | 1990-02-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1627890U JPH03107825U (en) | 1990-02-20 | 1990-02-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03107825U true JPH03107825U (en) | 1991-11-06 |
Family
ID=31519552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1627890U Pending JPH03107825U (en) | 1990-02-20 | 1990-02-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03107825U (en) |
-
1990
- 1990-02-20 JP JP1627890U patent/JPH03107825U/ja active Pending