JPH03106019A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to limit to the minimum the amount of thinning of an oxide film caused by wet cleaning by a method wherein the etching is started from the wet-cleaned oxide film having low etching rate to higher etching rate. CONSTITUTION:Dependence of the dosage, the type of ion species and the like affecting on the rate of etching is computed in advance. The order of ion implanting processes is selected in such a manner that the ion implanting process for the ion species and the dosage having the lowest etching rate is conducted first, and then the ion implanting process is conducted successively in the order of the etching rate which is becoming higher. For example, when the same ion species are implanted, a high dosage (1X10<14>/cm<-2> or higher) process is conducted after a low dosage (1X10<14>/cm<-2> or less) process. When different ion species such as B<+> of 1X10<14>/cm<-2> and As<+> of 1X10<14>/cm<-2>, for example, are ion-implanted, the B<+> of low etching rate is ion-etched, and then the As of high etching rate is ion-etched. As a result, the amount of thinning of an oxide film can be suppressed to the minimum, and the diffusion of impurities into a substrate from an interlayer insulating film can also be prevented.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device in which a series of steps of resist patterning, ion implantation, resist removal, and wet cleaning are performed multiple times in succession. In semiconductor devices, an ion implantation process is performed multiple times, with the aim of limiting the oxidation process to a minimum, and the ion implantation process is sequentially performed by patterning the resist, implanting ions through the oxide film, removing the resist, and wet cleaning with slight etching of the oxide film. In the manufacturing method, the ion implantation step is performed in order of decreasing etching rate of the oxide film by wet cleaning.

[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device in which a series of steps of resist patterning, ion implantation, resist removal, and wet cleaning are performed multiple times in succession. It is related to.

[Prior Art] In the conventional manufacturing process of semiconductor devices, a series of ion implantation steps including resist patterning, ion implantation, and resist removal is performed multiple times in succession to create ion implanted regions with different conductivity types, concentrations, implant locations, etc. It is common practice to create. Is there an order in which to create these ion implantation regions that will make resist patterning most efficient? It was determined from the points, and the order was said to be variable if there were no restrictions on resist patterning, and the other points were configured unconsciously.

However, when wet cleaning is performed using NH40H/HaO2 to remove dust after removing the resist, the oxide film (SiO
a) is slightly etched.

[Problem to be solved by the invention]

Figure 2 {A} to (C) are 950 to 1100
B" (acceleration energy 50 keV), P" (same < 120 key), As" (same < 180 ke
After ion implantation with y), sH4oH/}IaOi
It is a graph showing the oxide film etching rate with an etching solution (temperatures of 22.5° C. and 80° C.) versus the impurity dose.

From this graph, it can be seen that in the case of high temperature etching, the etching rate changes depending on the dose and ion species.

For this reason, the amount of thinning of the oxide film varies depending on the dose of ion species in ion implantation and the order of the steps.

An example of a conventional process in which B'' ions are implanted twice using the same ion species will be described below with reference to FIG.

In the figure, l is the SL substrate, 2 is the field oxide film, 3 is the resist, 4 is the gate oxide film, 5 is the gate electrode, 6 is the oxide film on the gate electrode, 7 is the resist, and 8 is the interlayer insulation with PSG. It is a membrane.

In Figure 3 (a), B” is, for example, 1×10l8cm.
By implanting into the Si substrate 1 and gate electrode 5 at a dose of "", a process including high-dose ion implantation is performed first. In this step, the resist 3 covers a region (not shown) into which ions will be implanted at a low dose in a subsequent step.

Next, the resist 3 is removed (Fig. 3 (opening)) and cleaned with an NH40H/H202-based etching solution to remove dust, and 39 is implanted at a dose of I For example, 150A/10 minutes? It is dissolved at the etching rate (1 x 1 in Figure 2 (a)).
0lIlcm-" (see the value on the vertical axis corresponding to the horizontal axis), while the Si substrate 1 covered with the resist 3 in FIG. Subsequently, as shown in FIG. 3(C), the Si substrate 1 is selectively covered with a resist 7, and exposed areas (not shown) of the Si substrate 1 are coated with a low dose (for example, IX10''). Perform B3 injection at cm-”).

Next, as in Fig. 3 (b), resist removal and NH40
When cleaning with a 11/HzO*-based etching solution, Sift in the low dose region is dissolved at an etching rate of 50 people/10 minutes, while SiO■ (4.6) in the high dose region shown in Figure 3 is dissolved. is dissolved at an etching rate three times higher than that of 150 people/lO min. Therefore, if each cleaning is carried out for 5 minutes, the oxide film in the high dose area will be 2X (150 people/10 minutes) x 1/2 = 15
0 people were dissolved, while the oxide film in the low dose area was (30 people/
10 minutes + 50 people, 710 minutes) x 1/2 = 40 people will be dissolved. Therefore, if a step including low-dose ion implantation is performed later, the oxide film in the high-dose region becomes extremely thin. Thereafter, when the interlayer insulating film 8 is formed in FIG. 3(E), a problem arises in that impurities spread from the interlayer insulating film 8 to the substrate 1 and the gate electrode 6.

The above explanation was given using a single type of ion implantation as an example, but B
When implanting different types of ions such as 0 and As, if the process with a high dose is performed first, the number of subsequent wet cleanings will increase, and the amount of film loss in the oxide film in the high dose area will be large as well. The oxide film becomes extremely thin.

With the miniaturization of semiconductor devices in recent years, the oxide film has become smaller than 200 mm.
Because it is 400 people thinner, the effect of film thinning is greater, making it easier for impurities to penetrate.

Therefore, an object of the present invention is to minimize the amount of loss of the oxide film during wet cleaning, and to prevent the above-mentioned problems from occurring.

[Means to solve the problem]

The present invention is characterized in that the wet cleaning steps are performed in order of decreasing etching rate of the oxide film.

Since such etching rate depends on the dose, ion species, etc., it is determined in advance, and the ion implantation process with the ion species and dose with the lowest etching rate is performed first, and then the ion implantation process with the ion species and dose with the highest etching rate is performed. The ion implantation step is performed last, and if there are three or more steps, the order of the ion implantation steps is selected so that the etching rate increases sequentially.

In the present invention, for example, when ion implantation is performed using the same ion species, the high-dose process (I x 10 "am-" or more) is performed after the low-dose process (less than 1xl○"cm-"). Let's do it. When implanting different ion species, for example, B0 is 1×10"am-', A
When ion-implanting s"" at IX10"cm-", first ions of B0 having a slow etching rate are implanted, and then As"? ions having a fast etching rate are implanted.

[Effect]

According to the present invention, the number of times of wet cleaning of an oxide film that incorporates a large amount of dopant is minimized by sequentially performing steps in which the etching rate of the oxide film by wet cleaning is low.

Therefore, diffusion of impurities from the interlayer insulating film to the substrate due to thinning of the oxide film can be prevented.

[Example] Figure 1 is a diagram showing an example of the present invention, in which G of the MOSFET is
The process after forming the ate electrode is shown.

In FIG. 1(A), B'' is implanted into the SL substrate l and the gate electrode 5 at a dose of IXIOcm-''. In this step, the resist 3 covers a region (not shown) into which ions will be implanted at a high dose in a subsequent step.

Next, the resist 3 is removed (FIG. 1(b)), and cleaning is performed with an NH401{/H20■ based etching solution to remove dust. Subsequently, as shown in FIG. 3(c), the St substrate 1 is selectively covered with resist and exposed areas (not shown) are coated with a high dose (L x 10'').
Perform B″″ injection at cm-”). Then, perform B″″ injection at
b) Similarly, resist removal and NH. Cleaning is performed using an OH/H202 etching solution (FIG. 1 (2)).

Here, under the same etching conditions as explained with reference to FIG.
(50 people/10 minutes) Xi/2 = 90 people, and in the low dose region, the amount of oxide film destruction is 2X (50 people/10 minutes) x 172 = 50 people. Therefore, the oxide film in the high dose region will not become extremely thin.

[Effects of the Invention] As explained above, according to the present invention, the amount of film loss of the oxide film can be minimized, and the diffusion of impurities from the interlayer insulating film to the substrate can be prevented, thereby improving the performance of such semiconductor devices. It greatly contributes to performance improvement.

[Brief explanation of drawings]

FIG. 1 is an embodiment of the present invention, and FIGS. 2 (a), (b), and (c) are NH. OH/}120
A graph showing the etching rate of an oxide film by a two-system etching solution, and FIGS. 3(A) to 3(E) are process diagrams of the conventional method. In the figure, an l-Si substrate, 2-field oxide film, 3-resist, 4-gate oxide film, 5-gate electrode, 6-oxide film on gate electrode, 7-resist, 8-interlayer insulating film such as PSG IΔF-S゜゛IOJ injection Figure 1 (A) t/Jisl-Reiun/Ezunanq' Figure 1 (mouth) Exclusion/Etsutenofu Figure 1 (2) High F'-Swio J'/Main Figure 3 (Du) I/Last L-Exclusion/Etsutenofu Figure 3 (mouth) Blade 17, 4 Negative Beauty 1 Figure 3 (
c) In Figure 3)

Claims (1)

[Claims] 1. Manufacture of a semiconductor device in which an ion implantation process is performed multiple times, which sequentially includes resist patterning, ion implantation through an oxide film, removal of the resist, and wet cleaning with slight oxide film etching. A method for manufacturing a semiconductor device, wherein the ion implantation step is performed in order of decreasing etching rate of the oxide film by the wet cleaning.