JPH0310518A - Input buffer circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the fluctuation of a threshold voltage due to supply of a different power supply voltage by applying a reference voltage set in a range expressed by a prescribed inequality to a gate of a field effect element connecting in series with a logic gate means between 1st and 2nd power supply levels. CONSTITUTION:A PMOS transistor(TR) 3, an NMOS TR 2a and a reference voltage generating circuit 5a connecting to a gate of the TR 3 are connected in series between a power supply Vcc and ground. A reference voltage generating circuit 5a includes Pmos TRs 51, 52 and an NMOS TR 53 connected in series between the power supply Vcc and ground. Gates and drains of the TRs 51, 52 are connected together and a prescribed reference voltage Vcst is outputted from a common connection node of the TRs 52, 53 and given to a gate of the TR 3. Thus even when the 1st and 2nd power supplies differ, the range of fluctuation of the threshold voltage of a logic gate means is decreased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an input buffer circuit for semiconductor integrated circuits, and in particular, to an input buffer circuit for semiconductor integrated circuits that can operate stably even under different power supply voltages. FIG. 1 is a circuit diagram showing an example of a conventional buffer circuit for a semiconductor integrated circuit. Referring to FIG. 11, this buffer circuit is a PMOS
It includes a CMOS inverter 2b configured by a transistor 21 and an NMOS transistor 22, and the gates of the transistors 21 and 22 are connected to the input terminal 1.

Output node 4 is connected to the next stage processing circuit.

FIG. 12 is a circuit diagram showing another example of a conventional buffer circuit. Referring to FIG. 12, this buffer circuit consists of C
MOS inverter 2b receives power supply voltage Vcc via PMOS transistor 6a. NMOS transistor 6b is connected between output node 4 and ground. Transistors 6a and 6b are connected such that each gate receives chip selection signal C8.

As shown in FIGS. 11 and 12, a logic gate such as an inverter 2b is used in the input buffer circuit. The logic gate has a threshold voltage and operates in response to an input signal Vin. On the other hand, recent semiconductor integrated circuits are required to be able to operate stably even under different power supply voltages. Therefore, it is desirable that the threshold voltage does not change even if different power supply voltages are supplied. However, in the conventional input buffer circuit, when different power supply voltages are supplied, the threshold voltage fluctuates as follows.

FIG. 13 is a schematic diagram illustrating voltages at each electrode of the inverter 2b shown in FIG. 11. (a) shows the transistor 21, and (b) shows the transistor 22. In the figure, "GS" indicates the gate-source voltage, and VDs
indicates the source-drain voltage, and ■ indicates the current flowing between the source and drain.

On the other hand, the VD-ID characteristics of a MOS field effect transistor can be simply expressed by the following Crawford equations (1) and (2).
) is given by

In the region between the three poles... (1) However,! VGs VvHl>1VosAlso, in the pentode region, however, IVGs -VyI41≦IVoswhere,
Decoding is 10 for n-channel transistors and - for p-channel transistors.

Therefore, in the transistor 21 shown in FIG.
It is expressed as follows, where Sonoβ is βr and 1Vvnl is VP.

VG B -V i n -Vc c -(3
a) VD, -Vout-Vcc-
(3b) l-βr 1(Vin-Vcc+Vr)(V
out-... (4a) However, Vin+Vr<Vout! --βP (Vin-VCC+VP)2...
(4b) However, Vin+Vr≧Vout In the transistor 22, β is expressed as follows, with β-1 threshold voltage vTH being VN.

VG 5 = V i n ”・(5
a) Vo 5-Vout -(5b
) is the threshold voltage.

The value of voltage V, is obtained from equations (4b) and (6b) by the following equation.

... (6a) However, Vin-VN > Vout 1 = -73N (V in-VN ) 2- (6b
) However, Vin-V≦Vout FIG. 14 shows equations (4a), (4b), and (6a).

FIG. 6 is a characteristic diagram showing input/output characteristics of a CMOS inverter defined by (6b) and (6b). In Figure 14, ■
In the region, the transistor 22 operates in the pentode region,
Transistor 21 operates in the region between three electrodes. On the other hand, in the region (■), the transistor 22 operates in the region between three poles, and the transistor 21 operates in the region between five poles. In both transistors 21 and 22, transitions in the 3-pole and 5-pole regions occur at voltage vr+. It can be seen from the inverter equation (7) that this value is a monotonically increasing function in which the inverter threshold voltage vrl increases in response to the power supply voltage Vcc.

Figure 15 shows the CM when different power supply voltages are supplied.
FIG. 2 is a characteristic diagram showing input/output characteristics of an OS inverter. As mentioned above, since the threshold voltage VM is expressed by a monotonically increasing function of Vcc, when the power supply voltage Vcc is 4.5.6 volts as shown in FIG.
ml, Vm2°Vm3.

[Problems to be Solved by the Invention] As described above, the threshold voltage of a CMOS inverter generally varies when different power supply voltages Vcc are applied. Therefore, conventional semiconductor integrated circuits have a problem in that malfunctions occur when different power supply voltages are applied.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to reduce fluctuations in threshold voltage caused by supply of different power supply voltages in an input buffer circuit for a semiconductor integrated circuit.

[Means for solving the problem] An input buffer circuit for a semiconductor integrated circuit according to the present invention includes:
a field effect element and logic gate means connected in series between first and second power supply potentials; and a reference voltage source connected between the first and second power supply potentials and generating a predetermined reference voltage. include. The field effect element is connected such that its gate electrode receives a reference voltage, and the predetermined reference voltage is set within a range indicated by a predetermined unreasonable expression with respect to the voltage of a common connection node of the field effect element and the logic gate means. be done.

[Operation] In the input buffer circuit for a semiconductor integrated circuit according to the present invention, a reference voltage within a range indicated by a predetermined inequality with respect to the voltage of the common connection node is always supplied to the gate electrode of the field effect element. Therefore, even if the values of the first and second power supply potentials are different, the range in which the threshold voltage of the logic gate means fluctuates can be reduced.

[Embodiment of the Invention] FIG. 1 is a circuit diagram of an input buffer circuit for a semiconductor integrated circuit showing an embodiment of the invention. Referring to Figure 1,
This input buffer circuit consists of a PMOS transistor 3 and an NMOS transistor connected in series between the power supply VCC and ground.
It includes a transistor 2a and a reference voltage generation circuit 5a connected to the gate of the transistor 3. transistor 2a
has its gate connected to external input terminal 1. An output signal Vout is output from a common connection node (output node) 4 of transistors 3 and 2a. Reference voltage generation circuit 5
a is a PM connected in series between power supply Vcc and ground
Includes OS transistors 51 and 52 and an NMOS transistor 53. The gate of transistor 53 is connected to power supply Vcc. Transistors 51 and 52 are
The gate and drain of each are integrally connected. A constant reference voltage Vest is output from the common connection node of transistors 52 and 53 and applied to the gate of transistor 3.

FIG. 2 is a circuit diagram of an input buffer circuit showing another embodiment of the invention. Referring to FIG. 2, in this input buffer circuit, a CMOS inverter 2b is connected to a power supply Vcc via a PMO transistor 3. Inverter 2
NMOS transistor 6b is connected between output node 4 of transistor b and ground. Transistor 6b is connected such that its gate receives chip selection signal (2). A PMO8) transistor a is connected in parallel with transistors 51 and 52. Transistors 6a and 54 are connected such that each gate receives chip selection signal C8.

Next, regarding the input buffer circuit shown in FIG. 2, the principle behind the stability of the threshold voltage of inverter 2b even if different power supply voltages Vcc are applied will be explained.

FIG. 3 is a schematic diagram showing the transistors 3, 21, and 22 shown in FIG. 2 separately for the following explanation. In this figure, (a) shows the transistor 3, (b) shows the transistor 21, and (c) shows the transistor 22.

First, regarding the transistor 3, let the βa1 threshold voltage be Va, and then the following equation can be obtained in the same way as described above.

VG 3--Vc s t-(8a)V
□ B −VE −VCC・= (8b)■−βa 1
(-Vcsr+Va) (VE-Vcc)-z (ME
Wee)2) -(9a) However, Vc
s t-Va>Vcc-VE■-upper βa(-Vest
+Va)2- (9b) However, Vst-Va≦Vcc
-VE Further, regarding the transistor 21, when β is βb1 and the threshold voltage is vb, the following equation is obtained.

VG 1-Vi n-VE --- (10a
)Vo 1-Vout-VE-(10
b)■-βbl (Vln VE 10vb) (Vo
(ut-VE) However, Vtn+Vb<Vou However, Vin+Vb≧Vout Furthermore, regarding the transistor 22, if β is βN1 and the threshold voltage is VN, the following equation is obtained.

VG $-Vin-(12a)V(
,,-Vout □= (12b)1
=BNl(Vin-VN) Vout-±V"out
1...(13a) However, Vln-Vll >Vout ■-Upper BN (Vin-VM)2 However, Vin-Vll ≦Vout When Vcs t-Va>Vcc-V(, the formula (
9a) gives the following equation.

VE −Vcc−Vest +Va (13b) (14) Here, voltage V= represents the voltage at the common connection node E of transistors 3 and 21 shown in FIG. Therefore, as seen from equation (14), as current I increases, voltage vE decreases.

FIG. 4 shows input voltage Vin and output voltage Vout.

4 is a characteristic diagram showing the relationship between the voltage "E+" and the through current I. As shown in FIG.
It is maximum when n is the threshold voltage. Therefore, at this time, the voltage V[ becomes the minimum, and the voltage VE increases before and after that.

Here, if the output voltage Vcst of the reference voltage generation circuit 5a is set to satisfy the following inequality (15), the following equation (16) can be obtained as the threshold voltage VM.

VE<Vcc−Vcs t+Va −= (15
)... (16) As seen from equation (16), by applying the reference voltage Vest that satisfies the relationship of inequality (15) to the gate of transistor 3 shown in FIG. becomes independent of power supply voltage Vcc.

FIG. 5 is a characteristic diagram showing input/output characteristics when different power supply voltages Vcc are supplied. As shown in Figure 5,
Even when 4.5.6 volts is applied as a different power supply voltage Vcc, the threshold voltages v, , l remain constant.

FIG. 6 is a characteristic diagram showing VDI and characteristics for each input voltage Vin for transistors 21 and 22. In this figure, the solid line indicates the transistor 22, and the dotted line indicates the transistor 21. As input voltage Vin, 1.2,
The case where 3.4 volts are applied is shown. When the same value of input voltage Vin is applied, the intersection of the curves is the through current as an inverter! and output voltage Vout.

When the input terminal Vin is 2 volts, the two curves intersect in the pentode region (straight line portion), which indicates the threshold voltage vi of the inverter.

FIG. 7 is a characteristic diagram showing the Vo IO characteristics of the transistor 21 when different power supply voltages Vcc are applied. This figure shows cases where the power supply voltage Vcc is 5 volts and 6 volts.

As shown in FIG. 7, even though the input voltage Vin remains the same, the voltage IVGsI increases by 1 volt. For example, considering the 5-electrode region, when the input voltage Vin is 3 volts when the voltage Vcc is 5 volts, the input voltage Vin is 4 volts when the power supply voltage Vcc is 6 volts. do. This corresponds to the transistor 22. This can be seen from the fact that the threshold voltage increases as the power supply voltage Vcc increases, since the I0 characteristic does not depend on the power supply voltage Vcc.

FIG. 8 shows the vD when the inverter 2b is connected to the power supply Vcc via the transistor 3 as shown in FIG.
FIG. 3 is a characteristic diagram showing ID characteristics. In this case, the maximum value of the through current I is limited by the transistor 3. Therefore, even if the input voltage Vin changes, the current I will not flow above a certain value. Therefore, even if the power supply voltage Vcc changes, the through current! Since the maximum value of does not change, the voltage of the n-channel transistor 22 is always at this maximum value. I0
By making the characteristics intersect with each other, it is possible to eliminate fluctuations in the threshold voltage due to supply of different power supply voltages Vcc.

The above explanation is based on the power supply voltage Vcc of the inverter threshold voltage.
This is the principle for eliminating dependence on

Since the above-mentioned equations (1) and (2) are approximate equations that ignore substrate effects, etc., in reality, the influence of their dependence on the power supply voltage Vcc appears. For example, in the above description, the current ID was constant in the pentode region without depending on the voltage VD, but in reality, it increases with a slight slope in an n-channel transistor and decreases in a p-channel transistor.

Therefore, as a result, the dependence of the threshold voltage on Vcc remains slightly, but it can still be significantly reduced by using the circuits shown in FIGS. 1 and 2.

FIG. 9 is a characteristic diagram showing the input/output characteristics of the inverter as a result of simulation using 5PICE. 9th
In the figure, the solid line shows the characteristics of the inverter 2c shown in FIG. 11, and the dotted line shows the characteristics of the inverter 2b shown in FIG. As can be seen from this figure, different power supply voltages V
It can be seen that even if cc is given within the range of 4 volts to 6 volts, the fluctuation range of the threshold voltage is reduced. That is, in the conventional inverter 2c shown in FIG. 11, a threshold voltage fluctuation of about 0.8 volts was observed, but in the inverter 2b shown in FIG. There is.

FIG. 10 is a circuit diagram of an input buffer circuit showing still another embodiment of the invention. Referring to Figure 10, the second
The difference compared to the circuit shown in the figure is that transistor 54 is omitted from the circuit of FIG.
and 54 are connected. Even if this circuit is applied, the same effects as described above can be obtained.

In this way, in the input buffer circuits shown in FIGS. 1, 2, and 10, by applying the reference voltage generation circuit 5a or 5b that satisfies the relationship of inequality (15), the threshold voltage power supply Dependency on voltage Vcc can be reduced.

[Effects of the Invention] As described above, according to the present invention, the range indicated by the predetermined inequality is applied to the gate of the field effect element connected in series with the logic gate means between the first and second power supply potentials. Since the reference voltage set at

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an input buffer circuit showing one embodiment of the present invention. FIG. 2 is a circuit diagram of an input buffer circuit showing another embodiment of the invention. FIG. 3 is a schematic diagram showing the three transistors shown in FIG. 2 in isolation. FIG. 4 is a characteristic diagram showing the relationship between the input voltage, the output voltage, the voltage at node E, and the through current l in the circuit shown in FIG. FIG. 5 is a characteristic diagram showing input/output characteristics when different power supply voltages are supplied. FIG. 6 is a characteristic diagram showing Vo I and characteristics for each input voltage of p- and n-channel transistors. FIG. 7 is a characteristic diagram showing Vol and characteristics of a p-channel transistor when different power supply voltages are applied. FIG. 8 is a characteristic diagram showing the VD 10 characteristic of the p-channel transistor in inverter 2b shown in FIG. FIG. 9 is a characteristic diagram showing simulated input/output characteristics of the inverters shown in FIGS. 2 and 11, respectively. FIG. 10 is a circuit diagram of an input buffer circuit showing still another embodiment of the invention. 11 and 12 are circuit diagrams showing examples of conventional buffer circuits for semiconductor integrated circuits. FIG. 13 is a schematic diagram illustrating voltages at each electrode of the inverter shown in FIG. 11. FIG. 14 is a characteristic diagram showing the input/output characteristics of the inverter shown in FIG. 11. In the figure, 1 is an external input terminal, 4 is an output node, and 5a
and 5b is a reference voltage generation circuit.

Claims (1)

[Scope of Claims] A field effect element and logic gate means connected in series between first and second power supply potentials;
a reference voltage source that is connected between power supply potentials and generates a predetermined reference voltage; the field effect element is connected such that its gate electrode receives the reference voltage generated by the reference voltage source; An input buffer circuit for a semiconductor integrated circuit, wherein the predetermined reference voltage is set within a range indicated by a predetermined inequality with respect to a voltage at a common connection node of the field effect element and the logic gate means.